Demo Data from VLDB 2026 / reviewers in the wild / expert
Jean Claude Geffroy
dblp:66/6497
· DBLP profile ↗
6ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Applied, interdisciplinary, general and emerging computing · 2Human-computer interaction and ubiquitous computing · 1Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 44% Electronic design automation · 22% Distributed systems · 11% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
self-checking circuits |
0.0 | 1 | 1982 | Cascaded Self-Checking Bus Arbiters for Multicomputer Systems · RTSS 1982 |
Interconnection networks and networks-on-chip › arbitration
bus arbitration |
0.0 | 1 | 1982 | Cascaded Self-Checking Bus Arbiters for Multicomputer Systems · RTSS 1982 |
Hardware reliability and fault tolerance › self-checking circuits
fail-safe sequential machine |
0.0 | 1 | 1974 | On-Set Realization of Fail-Safe Sequential Machines · IEEE Trans. Computers 1974 |
Electronic design automation › hardware verification and test
fault modeling |
0.0 | 1 | 1974 | On-Set Realization of Fail-Safe Sequential Machines · IEEE Trans. Computers 1974 |
Distributed systems
fault tolerance |
0.0 | 1 | 1974 | On-Set Realization of Fail-Safe Sequential Machines · IEEE Trans. Computers 1974 |
Parallel and multicore computing
multicomputer |
0.0 | 1 | 1982 | Cascaded Self-Checking Bus Arbiters for Multicomputer Systems · RTSS 1982 |
Electronic design automation › hardware verification and test › fault modeling
stuck-at fault |
0.0 | 1 | 1974 | On-Set Realization of Fail-Safe Sequential Machines · IEEE Trans. Computers 1974 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1974 | On-Set Realization of Fail-Safe Sequential Machines · IEEE Trans. Computers 1974 |
Methods — techniques the papers use, named apart from their topics
on-set realization · 0.0k-out-of-n codes · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2003 | Dependable computing: an overview
Gilles Motet, Jean Claude Geffroy |
Theor. Comput. Sci. | 2 |
| 1999 | UML Framework for the Design of Real-Time Robot Controllers
Luis Carroll, Bertrand Tondu, Claude Baron, Jean Claude Geffroy |
Euro-Par | 4 |
| 1998 | Comparison of two significant development methods applied to the design of real-time robot controllersabstractThis paper presents the principal functionalities of robot-manipulator controllers and a comparative study of two development methods for real-time systems applied to this controller. The selected techniques are SART and the unified method associated to UML, because they represent two classical types of modelling techniques: structured design with functional decomposition and object-oriented methodology. We analyse seven design issues associated to the robot controller development process and its utilisation comparing these two methods. Luis Carroll, Bertrand Tondu, Claude Baron, Jean Claude Geffroy |
SMC | 4 |
| 1991 | Identification of structured automata for test evaluationabstractPresents an original approach to the evaluation of test sequences applied to sequential circuits represented by structured-functional models; the method is based on formal identification of the internal modules of the circuit studied. A prototype software tool has been implemented in PROLOG in order to validate the approach.> K. El. Maadani, Jean Claude Geffroy |
VTS | 2 |
| 1982 | Cascaded Self-Checking Bus Arbiters for Multicomputer Systems
Marc Courvoisier, Jean Claude Geffroy |
RTSS | 2 |
| 1974 | On-Set Realization of Fail-Safe Sequential MachinesabstractFail-safe sequential machines can be constructed in such a way that if a failure happens in the sequential part, the ulterior functioning must carry on outside the code chosen to represent the set of states. This paper presents a study of the failures in the input combinational circuit and of the feasibility conditions of sequential machines with states coded by a k-out-of-n code. The electronic circuit is realized in a classical way (on-set realization) and must obey two hypotheses, 1) no failure on clock line C, and 2) single fault (stuck at 0 or stuck at 1) on other connections than C. Michel Diaz, Jean Claude Geffroy, Marc Courvoisier |
IEEE Trans. Computers | 2 |