Printed circuit boards (PCB) with soldered-down arrays of advanced memory devices are growing more common and present a class of difficult testing problems to PCB manufacturing. With the large memory capacities now available, memory expansion connectors are less necessary, and many products have reduced form factors (thinness) that means upright memory DIMM arrays are being phased out. When memory devices are soldered down, they become part of the board test problem, where in the past it was only necessary to test the empty sockets that would later be populated with memory. This paper discusses a Design-for-Test (DFT) technology that can be easily applied to memory devices which is independent of the silicon, and only impacts the design of the package the memory is placed within. This means DFT can be retrofitted to memories already in production without a costly silicon design change.

The practice of initializing a board or system for testing purposes is not an exact science, but rather, pursued empirically and with an increasing risk of undesired side effects. It has been suspected that Boundary-Scan testing can cause such side effects. This paper provides a case study of such a board where a detailed root-cause analysis was performed. Some issues are identified that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing and to leave it in a safe state upon completion of testing.

This paper presents the problem of undetected shorts on IEEE 1149.1 compliant self-monitoring pins. Unidirectional and bidirectional self-monitoring pins may contain sufficient series termination resistance and low enough voltage swings such that shorts between two pins become resistively isolated from the receivers and therefore are undetected during wiring interconnect tests. Potential solutions to mitigate the problem are offered.

Capacitive Leadframe Testing is capable of detecting open solder defects in Printed Circuit Boards (PCB). Principal Component Analysis (PCA)-based approach has been shown to be effective in identifying outlier devices using Capacitive Leadframe Testing measurements. In practice, when a sense plate orientation is shifted or tilted, the resulting measurement variation makes detecting outliers harder. Approaches are introduced to compensate for the `abnormal' measurements due to sense-plate variations. A PCA based technique is developed to estimate the relative amount of tilt and shift in sense plates. Such estimates can be used to compensate for mechanical misalignments. It can also isolate the misalignment related information from the defect related information in the data. The effectiveness of this technique in the presence of the two common forms of mechanical variations is illustrated using experimental measurements from a laboratory setting. The approach is not sensitive to the order of pins, and as such, shows promise for detection of complex but systematic errors introduced by sense plate misalignments.

The practice of initializing a board or system for testing purposes is not an exact science, but rather, pursued empirically and with little help from IC designers. This paper examines some of the issues and trends that justify adding features to IEEE 1149.1 that will facilitate safe, fast and effective initialization of a board or system, to get it ready for testing and to leave it in a safe state upon completion of testing.

Capacitive Leadframe testing is an effective approach for detecting faults in printed circuit boards. Capacitance measurements, however, are affected by mechanical variations during testing and by tolerances of electrical parameters of components, making it difficult to use threshold based techniques for defect detection. A novel approach is presented for identifying boards that are likely to be outliers. Based on Principal Components Analysis (PCA), this approach treats the set of capacitance measurements of individual connectors or sockets in a holistic manner to overcome the measurement and component parameter variations inherent in test data. The effectiveness of the method is evaluated using measurements on three different boards. Enhancements to the technique to increase the resolution of the method are presented and evaluated.

This poster will provide a high-level description of IEEE P1149.8.1 and the manufacturing board test problem set it addresses. The poster will serve as a follow on to a paper (Session 2.1) which will be presented earlier in the conference. The principal goal of the poster is to raise awareness (and participation) for the developing standard.

As printed circuit board dimensions continue to decrease, in-circuit tester (ICT) access using a bed-of-nails plus capacitive sensing is increasingly difficult. Stimulus injection using IEEE 1149.1 boundary-scan has been proposed as an alternative, but without modification it has significant limitations. An IEEE-supported Working Group is developing an extension entitled, ¿1149.8.1 - Draft standard for boundary-scan-based stimulus of interconnects to passive and/or active components¿. It would add capabilities to 1149.1 that facilitate testing of connections to non-boundary-scan components, especially passive components and vacant connectors that are connected to devices equipped with 1149.8.1 facilities. This paper describes existing limitations, IC design changes that would address them, some experimental results, and a summary of how this proposed standard is evolving.

Strict analyses of boundary-scan test coverage performed on real-world printed circuit board topologies reveal significant holes in test coverage. Rather than abandon boundary-scan, it is preferable to augment boundary-scan test with other technologies that improve the overall ability to detect defects.

Most integrated circuits today possess large numbers of power and ground pins in addition to signal pins. Boundary-scan technology will adequately test the signals, but in general does not address open defects on the power/ground pins. Some ICs could get at least partial coverage on some of these pins due to their internal power/ground distribution structure. Thus boundary-scan could be used to test, diagnose and claim coverage for these defects. What is needed is an extension to BSDL to support this capability.

Bead Probe Technology has been developed as alternative In-Circuit Test (ICT) contact points replacing conventional test pads normally integrated into a printed circuit layout [Park04], [Park05], [DoGr06], [Agil07]. This paper discusses the potential of using Bead Probes in Computer Aided Design (CAD) systems when getting a board ready for production. It outlines the requirements that a software package must address in order to incorporate Bead Probes into the board design process. Finally, a software package was developed to implement this process and evaluations were made on a number of circuit boards representing the industry sectors of communications, consumer electronics, military/aerospace and automotive. The evaluations provide insight into the ability of Bead Probes to enhance access, manage board stress, reduce cost and increase ICT test reliability.

Printed circuit boards are steadily becoming faster, and as a result, relatively ordinary defects in connectors and sockets can now have more subtle and damaging effects. At the same time these defects defy detection by conventional technologies. This paper surveys existing tests for these defects and introduces a new solution based on network parameter measurements.

Printed circuit boards are steadily becoming faster. They have higher clock speeds, and edge rates on data signals have dropped down into the 100's of picoseconds. This presents some new challenges to the board test world because certain defects we did not do a good job covering in the past can no longer be ignored

Bead probes, a technology for in-circuit test probing of high-speed and/or high-density printed circuit boards was introduced at the 2004 International Test Conference as stated in K. P. Parker (2004). Since then much experimentation has been done with bead probe technology, and a large, high-density board has been designed and produced that makes use of them. This paper discusses the learning from these efforts

Bullock, in 1987 [Bull87] provided design-for-test (DFT) rules for probing printed circuit boards for in-circuit testing. Many of these rules stand in good stead even today. However, recent technical advances in operational board speed are leading some to believe that in-circuit testing cannot be performed on the high-speed sectors of boards soon to be designed. Due to the increasing usage of high-speed circuitry, there is worry in our industry that in-circuit testing will be marginalized with no good substitute available. It is the purpose of this paper to show how access can be maintained, even on highly dense gigabit logic boards

Bullock in 1987 [Bull87] provided design-for-test (DFT) rules for probing printed circuit boards for in-circuit testing. Many of these rules stand in good stead even today. However, recent technical advances in operational board speed are leading some to believe that in-circuit testing cannot be performed on the high-speed sectors of boards soon to be designed. Due to the increasing usage of high-speed circuitry, there is worry in our industry that in-circuit testing is marginalized with no good substitute available. It is the purpose of This work to show how access can be maintained, even on highly dense gigabit logic boards.

This paper introduced the "PCOLA/SOQ" defect model of board test coverage. The ability to take any board made up of any collection of devices, enumerate all the device and connection defects and grade the effectiveness of a test is a huge step towards really understanding and communicating board test coverage. Measuring expected board quality and the risk you necessarily take when coverage is incomplete it helps board manufacturers make more informed choices.

Very high-speed, digital technology is imposing new requirements on test logic that will limit the effectiveness of current IEEE 1149.1 based testing. IEEE P1149.6 is an extension to IEEE 1149.1 that attempts to standardize the boundary-scan structures and methods required to ensure simple, robust and minimally intrusive boundary-scan testing of advanced digital networks which are not adequately addressed by existing standards. This includes AC-coupled networks, differential networks or both. This paper will describe the work that has been done thus far by the P1149.6 working group including: defects to be targeted by the proposed standard, physical layer implementation for both the driver and receiver, verification of proposed solutions through SPICE modeling, BSDL and tools implications. The paper will also discuss some of the challenges faced by the working group and will discuss new approaches taken on by the working group in the development of the proposed standard.

Characterizing board test coverage as a percentage of devices or nodes having tests does not accurately portray coverage, especially in a limited access testing environment that today includes a variety of diverse testing approaches from visual and penetrative inspection to classical in-circuit test. A better depiction of test coverage is achieved by developing a list of potential defects referred to as the defect universe, where the capabilities of the chosen test strategy are not considered in development of this defect list. Coverage is measured by grading the capabilities of each test process against the defect universe. The defect universe is defined to be meaningful to the bulk of the electronics industry and to provide a consistent framework for coverage metrics and comparisons.

The question is whether “Board Testing has become stagnant” as an ITC topic. The implication is that the board test community has nothing new to invent, report or say that would be of use to the ITC community at large, and board test engineers in particular. This leads to the charge that ITC is really only an IC testing conference. While I must accept the fact that the IC content of ITC is much larger than the Board Test content (measured in sessions and papers), I reject this thesis, simply because board testing is so terribly difficult and more so as every day passes. We can marvel at the technology that goes into testing an IC with 50,000,000 transistors, but yawn at the prospect of testing a board containing hundreds of these ICs, along with hundreds of analog components sprinkled in. (At least those not charged with doing this job may yawn. Those who are should be petrified!) The board testing community is also very conservative. Quite simply, as a board test engineer, you are expected to move mountains every day, stay on schedule, produce high-yield product and not blink an eye as Moore’s law exponentially increases your problems. (If you do blink, you’re fired!) In this environment, you tend to stick with what works and avoid “risky” new adventures into topics like Boundary-Scan, until there are no other options. And yet, market forces produce new risks every day. The conservative nature of the board test community does produce some conundrums. Take the issue of “test coverage”. There is ample evidence that we do not know how to measure test effectiveness. Fifteen years ago a study [Schl87] showed that tests that might be rated a good (claims of “98.5% coverage”) might have significant defect escape rates. Then there is “tester myopia” that we indulge in – where classes of defects are simply ignored [Tege96] because our favored tester can’t test for them. The inexorable increases in board density give us test access limitations, and yet we still use test coverage concepts that assume full access [HPF02]. It’s what we’re familiar with, and rocking that boat could get you some “unwanted management attention”. I do not denigrate the problems of the IC testing community, they are huge; but it appears that the IC community has done a better job of getting the spotlight. This may simply be due to the price tags on their purchase orders for test equipment. Someone up the management chain is saying, “Why is this so expensive? Go find a better way!” and so you come to ITC, to find that better way. Board tester systems are stable-to-declining in price, even as the difficulty of creating and maintaining tests increase. This apparently does not justify plane tickets to conferences. And besides, you’ve got a schedule to hit and can’t afford a few days at ITC. I claim that board testing is not a mature technology. Some would argue that standards like IEEE 1149.1 and 1149.4 “prove” it is mature. They say, “We’ve standardized away your problems, now simply execute well!” Then a new technology like AC-coupled ICs comes along and your standards suddenly no longer work. This can be seen at this year’s ITC, where new board test problems are being addressed [EPB02] and new standards are being implemented. This particular change came quite precipitously and the board test community responded quickly. Note that they chose ITC as a place to rally.

The use of AC coupling capacitors on high-speed interconnects prevents the use of traditional DC-based boundary-scan techniques to test for board manufacturing defects. A solution is provided by a novel scheme that makes use of frequency discrimination using simple digital circuits that are easily integrated with the 1149.1 boundary-scan standard. Simulation results are presented which show the effectiveness of this method, and its robustness and scalability are compared with alternative solutions.

Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of poor documentation. While boundary-scan (IEEE Std 1149.1) is a powerful test tool, test engineers are finding out that yesterday's DFT rules and test approaches may actually be detrimental to successfully testing systems on a board. One culprit is the boot up process of the board and even individual ICs. The author attempts to answer the question of what can be done to address this.

The goals of the studies of the MNABST-1 IC device were as follows: study the technical and economic feasibility of adding P1149.4 structures into mixed-signal devices; elicit design considerations at the silicon level and for silicon design software; study the interoperability of P1149.4 with 1149.1 interconnection test algorithms; study the efficacy of discrete component and network value measurements; establish limits on analog value measurements; and predict the capabilities of P1149.4 in the future. The results shows that we can emulate the capabilities of in-circuit test for most types of components currently tested this way. This will preserve the advantages of this well-known technology into the future when direct nodal access will no longer be the rule, but rather the exception.

This is the second year of an ITC experiment, the ITC Lecture Series on Unpowered Opens Testing (UOT). Open solder joints on printed circuit boards have become a frustrating problem in today’s era of advanced component packaging. This forum brings condensed technical and product information to board test engineers (and their managers) that will be immediately useful in their daily endeavors.

In this paper we discuss board test coverage of opens for power pins of large ASICs soldered to electronic boards. Multiple power pin connections cannot be tested by typical electrical testing techniques because they are connected in parallel between the package and the board. We present in this paper an estimate of the probability of these power pin opens, outline the impact of the lack of test coverage in system performance, and offer possible solutions to the problem,.

Five years of experience with the IEEE 1149.1 standard are discussed. It has been widely accepted across the electronics industry. It has made major contributions to board level testability. However, the advancement of the 1149.1 standard has not been as rapid as one might have imagined and there are some outstanding problems that it does not well address. As a member of the 1149.1 and P1149.4 working groups, as well as a developer of software for ATE systems, the author is interested in what one can learn from the 1149 and discusses his experiences in this field.

This paper gives a proposal for an analog testability bus that could be used as the basis for a standard such as IEEE P1149.4. The proposed testability structure is imposed on the I/O pin cells of the analog and mixed technology ICs. It is a superset of the existing IEEE/ANSI 1149.1 testability standard for digital ICs and is intended to cooperate with it. This allows for the testing of interconnect failures such as shorts and opens, the testing of discrete analog components and networks between ICs, and supports the testing of analog functions within the ICs themselves. This paper is a companion to the result of a cooperative effort between AT&T, Ford Motor, Hewlett-Packard, Motorola and the University of Colorado at Colorado Springs.>

It is pointed out that boundary-scan (IEEE Standard 1149.1-1990) technology is beginning to be embraced in chip and board designs. One key need is a way to describe simply and effectively the feature set of a boundary-scan compliant device in a manner both user friendly and suitable for software to utilize. A language subset of VHDL is proposed for this purpose. A derivative effect of the proposed language is that, if a device is not describable by the language, the device does not comply with the 1149.1 standard. Although the converse is not true, the language still allows a syntactic check for compliance as well as a number of semantic checks.>

This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.

The correspondence between Boolean network probabilities and the design formalisms of Ledley and Aiken is demonstrated.

This paper presents a number of methods for finding sequential circuit output probabilities using regular expressions. Various classes of regular expressions, based on their form, are defined and it is shown how to easily find multistep transition probabilities directly from the regular expressions. A new procedure for finding steady-state probabilities is given which proceeds either from a regular expression or a state diagram description. This procedure is based on the concept of synchronization of the related machine, and is useful for those problems where synchronization sequences exist. In the cases where these techniques can be utilized, substantial savings in computation can be realized. Furthermore, application to other areas such as multinomial Markov processes is immediate.

In this correspondence two methods are given for calculating the probability that the output of a general combinational network is 1 given the probabilities for each input being 1. We define the notions of the probability of a signal and signal independence. Then several proofs are given to show the relationship between Boolean operations and algebraic operations upon probabilities. As a result of these, two simple algorithms are presented for calculating output probabilities. An example of the usefulness of these results is given with respect to the generation of tests for the purpose of fault detection.

A probabilistic treatment of general combinational networks has been developed. Using the notions of the probability of a signal and signal independence, algorithms have been presented to calculate the probability of the output of a logic circuit being 1. Simplifications to the algorithm result when sets of input probabilities are given the same value, and this process called bundling is described in the paper. Finally, a series of examples illustrate the application of the probabilistic approach to the analysis of faulty logic circuits.