Repeated modular additions and overflow detection are possible in redundant hybrid number systems (RHNS). In this paper a circuit is proposed that implements the overflow-detecting procedure in such systems and allows a mean addition time of about 10.5 gate delays for numbers having a magnitude order normally distributed in the range [−233, 233 − 1], versus a 14 gate delay required by 32-bit CLA adders.

A lower bound AT/sup 2/= Omega (n/sup 2/) for the conversion from positional to residue representation is derived according to VLSI complexity theory, and existing solutions for the same problem are briefly reviewed in the light of such a bound. A VLSI system is proposed, one that operates according to a pipeline scheme and works asymptotically emulating an optimal structure, independently of residue number system parameters. This solution has been applied to a design of specific size (64-b input stream), and it has been found that a single CMOS custom chip can implement the design with a throughput of one residue representation every 30-40 ns.>

A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROM-based structures is also provided. The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design. This structure can be used to implement a residue multiplier in arithmetic structures using residue number systems (RNSs). The complexity of this residue multiplier has been evaluated and lower complexity figures than for ROM-based multiply structures have been obtained under several hypotheses on RNS parameters.>

Residue Number Systems (RNS) are suited for high-speed applications and VLSI implementations, because of the modular and parallel nature of their arithmetic. In this paper a new solution is provided to the problem of designing VLSI structures for converting integers to and from residue number systems in the area of pipelined applications, with the constraint that the layout width is comparable with the data stream width. The proposed structure is suited for both direct and reverse conversion and has complexity figures better than previously known results, evaluated under several hypotheses on the RNS parameters.

In this paper a fast procedure is presented to fairly interpolate a given set of points, which is mainly based on the use of table look-up techniques. Storage amounts required can be easily supplied by present memories technology. Though our procedure can be applied to any interpolation method, it is well suited for a spline, using an angle as a parameter, which was defined by the authors in a previous paper. Benefits and limits of the procedure are discussed and several examples of its behaviour are given.

Special devices to generate curves are more and more convenient because of ever growing performance graphic tools are requested for. In this paper an approach to the design of fast hardware curve generators is proposed, mainly based on the use of vector generators and of stored tables. The needed precision can be achieved, while the final point and a selected subset of intermediate points are reached with an error of half a pixel at most; output rate is very close to available vector generators rate. Our method was applied to circle generation: for radius values up to some thousands of pixels, single-chip implementation results feasible. The method is easily extensible to threedimensional curves.