Probe cards are essential components in semiconductor manufacturing, acting as the electrical interface between wafers and automated test equipment during wafer probing. As integrated circuit dimensions continue to shrink, probe cards have become increasingly complex, introducing challenges in design, production, and maintenance. This paper presents a framework for real-time monitoring and management of probe cards in Electrical Wafer Sort applications. By analyzing eight months of historical failure data, we prioritize critical failure modes and identify associated challenges. We propose a sensor network system designed to collect operational data in real-time, enabling future development of machine learning models for anomaly detection and predictive maintenance. This framework aims to enhance probe card reliability and efficiency, leading to improved performance and reduced costs in Electrical Wafer Sort applications.

With the rise of Machine Learning (ML) and Artificial Intelligence (AI), the semiconductor industry is undergoing a revolution in how it approaches manufacturing. The SMART-IC project (DATE'24 MPP category: initial stage) works in this direction, by proposing an AI-enabled framework to support the smart monitoring and optimization of the semiconductor manufacturing process. An AI-powered engine examines sensor data recording physical parameters during production (like gas flow, temperature, voltage, etc.) as well as test data, with different goals: (1) the identification of anomalies in the production chain, either offline from collected data-traces or online from a continuous stream of sensed data; (2) the forecasting of new data of the future production; and (3) the automatic generation of synthetic traces, to strengthen the data-based algorithms. All such tasks provide valuable information to an advanced Manufacturing Execution System (MES), which reacts by optimizing the production process and management of the equipment maintenance policies. SMART-IC is a 300k€ academic project funded by the Italian Ministry of University and supported by STMicroelectronics and Technoprobe with industrial expertise and real-world applications. This paper shares the view of SMART-IC on the future of semiconductor manufacturing, the preliminary efforts, and the future results that will be reached by the end of the project, in 2025.

Embedded nano-electronic devices have spread in daily life over the past ten years. Chip and embedded system manufacturing has thus become more challenging in recent years.When safety-critical sectors like the automobile are considered, addressing system anomalies and faults is crucial. Therefore, it is necessary to develop and research innovative ways to maintain high reliability in safety-critical sectors despite the complexity of present Systems-on-Chip (SoCs).In order to ensure high reliability, and be compliant with reliability standards, designers started to add additional circuitry to perform on-device tests. Built-In-Self-Test (BIST) is a technology that allows to conduct exhaustive tests within devices and, most importantly, without the need for external equipment. BIST can detect faults by outputting a signature at test end, which can be compared with a known value. Thus such known signatures are key, and in case of a signature mismatch it is not trivial to understand the root cause of the failure.This paper proposes a methodology to find the first failing pattern which causes the BIST’s signature to deviate and a way to collect good signatures from in-field devices, at key on/off, where BISTs are programmed and executed by the firmware at maximum frequency for an industrial case study produced by STMicroelectronics.The transition delay fault model is the primary target for the described work.

Electronics play a significant role in modern society in various areas of our daily lives. Companies producing embedded nano-electronic systems have responded to the ever-increasing demand for high-performance chips with the development and production of structurally complex design, both in terms of the number of gates they are composed of and how they are arranged on the silicon surface. Especially devices intended for safety-critical fields, such as the Automotive field, require a thorough and precise testing process before they are fielded. This paper proposes a correlation analysis between candidate faulty logical gates as possible sources of a given failure identified during the Manufacturing Test Flow and their layout characteristics on the silicon. It is meaningful feedback for manufacturers about the quality of their applied tests. The experimental results are reported for data regarding a production lot of an Automotive System-on-Chip belonging to the SPC58 family produced by STMicroelectronics.

Functional test programs are increasingly used as flexible approaches to verify device functionality, both online (e.g., Software-Based Self Tests encapsulated in Software Test Library) and during the manufacturing test flow (e.g., System-Level Test). However, a traditional integrated development environment seldom analyzes functional test program weaknesses regarding fault-masking and propagation in CPU registers. Therefore, understanding the presence of errors in the programs due to logic faults at the end of the test program is only assessed by a signature computation, e.g., xor operation between all registers. The presence of program weaknesses in terms of data or control flow is not assessed, and it may lead to fault escapes and/or masking. In particular, those are perfect conditions for proliferating Silent data corruption and unrecoverable errors at the system level.This work aims to introduce a guided debugger-based fault injector framework to verify the fault propagation and masking capabilities of functional test programs by eventually catching program errors without relying on time-consuming simulation-based approaches. The fault-free instruction trace is dumped and analyzed to provide information about possible target registers of specific instructions for injecting faults, e.g., in jump instructions, where errors into registers may change the execution flow or not, to verify the presence of silent data corruptions and errors.The experimental results are carried out on an automotive device from the SPC58 family manufactured by STMicroelectronics, and faults are injected through a script running on Power Debug E40 from Lauterbach.

Burn-In test equipment usually owns extensive memory capabilities to store pre-computed patterns to be applied to the circuit inputs as well as ad-hoc circuitries to drive and read the DUT pins during the BI phase. The solution proposed in this paper dramatically reduces the memory size requirement and just demands a generic microcontroller unit (MCU) equipped with a couple of embedded processors, some standard common peripheral units, and a few KB memories. Moreover, the proposed Burn-In tester could be integrated into a System Level Test equipment which is typically based on MCUs to communicate functionally with the DUT. This paper provides full details about the architecture of such a low-cost innovative tester, which can supply the DUT with unlimited pseudo-random patterns created autonomously by the MCU firmware from any selected seed. The tester prototype developed to collect experimental results includes a low-cost System-on-Chip based on a multi-core MCU and a set of peripheral cores, encompassing timers and Direct Memory Access modules. The tester prototype is used to stress an automotive chip accounting for about 20 million gates, 700 thousand scan flip-flops, and several scan modes. The combination of pseudo-random pattern generation with the ability to control different scan and Design for Testability (DfT) modes, including LBIST, permits to reach a higher coverage of stress metrics than by the application of a limited set of pre-computed ATPG patterns. The toggle coverage level reached is up to 95.89%. The application speed achieved by the tester with non-optimized connections is up to about 10MHz.

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life.

The complexity of automotive Systems-on-a-Chip (SoCs) has enormously grown in the last decades. Today’s automotive SoCs are compelling due to technology improvements, different integration technologies, increased heterogeneity, and many available embedded memories. On balance, despite testing techniques that have been refined through years, traditional structural test methods, like scan and BIST, can cover a vast but not complete spectrum of all the possible defects. It appears that the divide-and-conquer approach founded on structural techniques may not be enough to reach every single element or to effectively stimulate the faulty behaviors that may show up during the lifetime of the device. Burn-In is widely used to reduce Infant Mortality, accelerating the evolution of weak points into defects via externally or internally induced stress.In this work, we focus on internal stress and present a generation strategy intended to automatically produce functional stress procedures for the Burn-In phase that exacerbate possible weak points which are likely to escape activation by structural tests, such that they more easily outbreak during the successive final test procedures. The proposed generation strategy primarily addresses the interconnections to embedded memories, which look challenging to stress by structural methods, including Logic and Memory BIST, and critical due to the integration of different technologies (i.e., logic gates and memory layout). In the considered test case, the proposed approach increases the average toggle activity by orders of magnitude with respect to Memory BIST. Furthermore, it provides a uniform distributed toggling activity.Results collected on an automotive SoC show how the stress provided by functional programs compares with the stress level provided by structural test methods measured in terms of toggling activity. The SpeedUp produced by the proposed procedure is 3.14X wrt to the MBIST executing the March C-algorithm.

Testing and validation check a hardware device or a software application against the desired design requirements. They are a vital part of all steps of system engineering and typically account for a significant percentage of the overall development cost. This paper presents a novel technique to provide a quick preliminary evaluation of functional test procedures of various natures, ranging from Software-Based Self-Test to Burn-In Functional Stress and System-level tests. We define a new metric called “connectivity”, which is fast to compute and can be used to guide functional program development. The method does not require logic or fault simulations, and it is based on the analysis of the execution trace generated by the functional program. To summarize our process, we first obtain the trace directly from the chip, running the software through a debugger. Then, we create a graph representation of the program data flow. Finally, we analyze the graph to identify instructions that negatively impact the final coverage. We perform experiments on an automotive device manufactured by STMicroelectronics, and we demonstrate the effectiveness of the approach in terms of computation time and beneficial effects on the fault coverage.

Embedded nano-electronic systems are becoming more prevalent in people's daily lives. As a result, chip and embedded system manufacturing has become increasingly complicated and huge in recent years. Considering safety-critical sectors, such as automotive, it is evident how managing system anomalies and defects becomes vital. Thus, it is necessary to develop and investigate innovative methodologies that can guarantee high reliability despite modern Systems-on-Chip's complexity in critical safety fields. Significant attempts were made to market incredibly reliable microelectronic components. In order to ensure the reliability of the devices, the Automotive field has also started focusing on collecting large amounts of data from car fleets. The data are collected in-field during the life cycle of the devices and create effective feedback for designers and manufacturers. This paper proposes a methodology to store and collect data from key-on and key-off tests performed by Logic BIST for an industrial case study produced by STMicroelectronics.

With the explosion of off-the-shelf SoCs in terms of size and the advent of novel techniques related to failure modes, commercial ATPG and fault simulation engines can often be insufficient to measure the coverage of very specific metrics. In these cases, many researchers firstly store the simulation trace during the analysis phase. Then, they collect the desired statistics during a post-processing step. In this framework, the so-called Value Change Dump (VCD) is a very commonly used file format to record simulation traces. The target of this paper is twofold. From the one hand, we illustrate some Burn-In (BI) related metrics which cannot be evaluated by current commercial fault simulators and ATPG engines. These metrics are indeed based on a post-processing analysis of memory dumps in VCD format. From the other hand, we mitigate the evaluation time and the memory required to analyze huge VCD files by exploiting optimization techniques coming from modern programming features and smart parallelization. Adopting this strategy, we can analyze simulation dumps of more than 250 GBytes in less than one hour, showing improvements of two orders of magnitude over previous tools, with a consequent higher scalability and testability power.

System-level test (SLT) is gaining in importance in modern test flows. This paper summarizes recent industrial findings from three companies and discusses some of the still open questions. The first two reports focus on the optimization potentials due to defect coverage overlaps between SLT and other test insertions. Results observed on approximately 20 million manufactured 28nm and 40nm automotive system-on-chip (SoC) designs are reported. Costs and benefits of SLT are discussed and the potentials of a test results analytics platform are identified. The third report explores the role of marginalities among SLT fails. The post-silicon investigation of a CPU block in a 7nm 5G mobile SoC product aims at achieving a better understanding, whose fails are due to random variations versus systematic factors.

The introduction of System Level Test (SLT) about a decade ago aimed to a better sustainability for the achievement of the quality objectives required by high performances GPUs and CPUs. The paper intends giving some quantitative information to support this simplified statement. To do this we will report the results of a study conducted by the industrial application of SLT on a product targeted to a high-quality market segment, such as automotive. The discussion will describe the different SLT solutions developed for this new field of application and how it was possible to isolate SLT-only fails and relative functional root causes and cross-correlate traditional ATE test versus SLT screening capability through manufacturing operations.

Automotive systems must reach a high reliability in their electronic components. This kind of devices must undergo several tests and stress steps discovering all possible defects that could manifest during lifetime. Burn-In (BI) is a manufacturing test phase used for screening the early life latent faults that can naturally affect a population of devices. System Level Test (SLT) is increasingly adopted as one of the final steps in the testing process of complex Systems on Chip (SoCs) mimicking the operational conditions. This paper aims at describing the motivations for and the effectiveness stemming from combining SLT with BI. The key idea leverages on the development of a new step inside the test process, which reproduces the system using SLT and places the system in the worst cases by means of the BI. Moreover, the paper analyses the required tester architecture to merge SLT and BI. Finally, an industrial case by STMicroelectronics is used to demonstrate the possible cost reduction.

Environmental and electrical stress phases are commonly applied to automotive devices during manufacturing test. The combination of thermal and electrical stress is used to give rise to early life latent failures that can be naturally found in a population of devices by accelerating aging processes through Burn-In test phases. This paper provides a methodology to evaluate and compare the stress procedures to be run during Burn-In; the proposed method takes into account several factors such as circuit activity, chip surface temperature and current consumption required by the stress procedure, and also considers Burn-In flow and tester limitations. A specific metric called Stress Coverage is suggested summing up all the stress contributions. Experimental results are gathered on an automotive device, showing the comparison between scan-based and functional stress run by a massively parallelized test equipment; reported figures and tables quantify the differences between the two approaches in terms of stress.

The testing of IC at package level may require complex flows. In such cases, when the shop floor is fed with lots of multiple product lines, the manufacturing execution can suffer of very low efficiency, throughput limitation and longer cycle time than expected. The present work proposes a Mixed Integer Linear Programming model to evaluate the operational efficiency of the shop floor under different loading conditions and various shop floor characteristics. In particular, our computational campaign uses realistic data to evaluate the impact of increased parallelism and the effect of different parallelism distribution on the operational efficiency.

Summary form only given. The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology Roadmap for Semiconductors) projects very high bit failure rates of the order of 10-2for SRAM and of 10-3for latches for 16nm high performance technology. Hence, solving reliability challenges for future technologies requires new efficient and cost effective approaches not only to detect and recover from in-filed failures, but also to extend the device lifetime for targeted applications.

Current, voltage and time (frequency) are the base parameters describing an electronic system. In the 1700's, Benjamin Franklin was one of the first experimenting with current tests, followed by many others shaping the current domain. In 1963 Frank Wanlass (Fairchild Semiconductor) planted the first seeds of using current testing as part of a structural approach to validate integrated circuits when publishing the concept of complementary-MOS (CMOS) logic circuitry. It occurred to him that a CMOS circuit would use very little power and that in standby; it would draw practically nothing — just the leakage current. It was therefore a fact that CMOS circuits with increased standby power consumption were defective. In 1981 Mark W. Levi demonstrated the concept of IDDQ testing (validating circuits by measuring and observing their quiescent supply current) in his ITC'1981 paper “CMOS is most Testable”. This paper kicked off a lot of research on IDDQ fault modeling, IDDQ defect detection capabilities, IDDQ and reliability, IDDQ efficiency. Much of that research happened in the late eighties — early nineties by “Chuck and Jerry”, exploring the benefits, followed by studies done by HP, IBM, TI, Philips, Alcatel, Ford Micro, … Since then IDDQ testing became synonym to current testing. Extensive research revealed the IDDQ capabilities. Despite its demonstrated defect detection capabilities and screening efficiency, it was not an easy way for IDDQ to make it to the production test floor. The initial lack of commercial available ATPG tools and suitable measurement solutions were the hurdles to take.

This paper describes an optimized embedded memory diagnosis flow that exploits many levels of knowledge to produce accurate failure hypothesis. The proposed post-processing analysis flow is composed of many steps investigating failure shapes as well as cell fail syndromes, and includes advanced techniques to tackle incomplete data possibly due to tester noise and/or by faults showing intermittent effects. The effectiveness of the technique is demonstrated on an automotive-oriented System-on-Chip (SoC) manufactured in a 90nm technology by STMicroelectronics, which includes embedded SRAM memory cores tested using a programmable BIST. Scrambled BITMAPS gives a visual feedback leading to quick physical defect identification. Such research is relevant to aid on the manufacturing, material and process enhancements raising silicon yield.

Adaptive testing is a generic term for a number of techniques which aim at improving the test quality and/or reducing the test application costs. In adaptive tests, the test content or pass/fail limits are not fixed as in conventional tests, but dependent on other test results of the currently or previously tested chips. Part-average testing, outlier detection, and neighborhood screening are just a few examples of adaptive testing. With this Embedded Tutorial, we are offering an introduction to this topic, which is hot in the test community, to the wider DATE audience.

Summary form only given: Safety is a concept which nowadays is pervading a large spectrum of applications fields. It was pioneered by military and aerospace and is now exploited in a wide spectrum of systems to prevent any form of injury to people to properties and to the environment. In other words, the purpose of safety is to prevent that any type of error generate unacceptable risk conditions. This talk will explore two specific aspects linked to safety. First, an analysis of error sources (limited to hardware and environmentally-dependant errors) will be taken. Secondly, a discussion on the detection and the diagnosis techniques of error root causes will be proposed, to follow-up the question asked by the keynote title. How and when is it possible to exploit differently the error detection and diagnosis features present in SoCs? Could they be re-used during off-line operations? Can we log and access the data they generate on-line? Is this a good chance to learn better about error root causes and activating better (=in a tailored manner) prevention mechanisms? Which are the key enablers to succeed?

An effective silicon debug and diagnosis process has to be supported by on-chip hardware structures, stimulation equipments and software tools for analysis. In this paper, the characteristics of a software tool for memory failure analysis are presented; this tool takes into account the memory topology and the executed memory test, and returns both syndrome and shape-based failure statistics. Furthermore, it allows the cumulative analysis over many memory cuts inside a die, a wafer or a lot. The results obtained for embedded SRAMs tested using March test algorithms are presented, demonstrating the capability of the tool in underlining manufacturing process weaknesses and systematic constructive marginalities.

This paper reports and analyzes the results of alpha radiation testing campaigns on an embedded microprocessor manufactured with different standard cell libraries, each one enforcing Design for Manufacturing rules at a specific level. A set of analog simulations has been performed on flip-flops built with different physical layouts to reproduce and evaluate the effects of ionizing particles. The results of simulation experiments are presented and discussed, highlighting the configurations which are more likely to improve the system reliability, and then compared with radiation experiments data. Finally, we give a physical interpretation of the observed variations on radiation sensitivity.

Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also for Reliability Characterization. This paper first discusses the characteristics of the stimuli to be used during Reliability Characterization experiments, and outlines the importance of adopting a functional approach. Secondly, the paper describes a novel approach to automatically generate suitable stress patterns to be used during the Reliability characterization process of Systems-on-chip. The generation process uses an evolutionary algorithm driven by suitable state toggling-related metrics purposely defined in the paper. Costs and benefits of the proposed approach are highlighted, supported by the results gathered on a test vehicle released on a 90 nm technology.

In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor VTHdegradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure used to make the SoC/System aware of the NBTI effects. This scheme is conceptually validated by using multi-level simulation and models. The discussion of possible exploitation models completes the paper.

This paper presents the results of Alpha Single Event Upsets tests of an embedded 8051 microprocessor. Cross sections for the different memory resources (i.e., internal registers, code RAM, and user memory) are reported as well as the error rate for different codes implemented as test benchmarks. Test results are then discussed to find the contribution of each available resource to the overall device error rate.

This paper proposes an efficient low-cost strategy for collecting data during radiation experiments on systems-on-chips (SoCs), exploiting the available on-chip design for testability (DfT) structures devised for manufacturing test.The approach combines hardware test and diagnostic features with suitable software tools, which enable accurate measurements and quick transient effects data collection. Specific flows for radiation testing of different kinds of embedded cores are described. Results are shown for a radiation experiment conducted on an embedded SRAM core included in a 90 nm test-vehicle.

Nanometric circuits and systems are increasingly susceptible to delay defects. This paper describes a strategy for the diagnosis of transition-delay faults in full-scan systems-on-a-chip (SOCs). The proposed methodology takes advantage of a suitably generated software-based self-test test set and of the scan-chains included in the final SOC design. Effectiveness and feasibility of the proposed approach were evaluated on a nanometric SOC test vehicle including an 8-bit microcontroller, some memory blocks and an arithmetic core, manufactured by STMicroelectronics. Results show that the proposed technique can achieve high diagnostic resolution while maintaining a reasonable application time.

This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main focus of our work is to obtain a modeling of the degradation of selected parameters measurable through at-speed testing. The paper reviews the current approach for reliability characterization and shows the achieved enhancement on efficiency and effectiveness. Results shown are related to experiments run on a vehicle released on a 90 nm technology.

This paper discusses the fabrication challenges introduced by products targeted to the automotive market segment. Different methods to enhance intrinsic design robustness, along with the design flow will be discussed. Experimental results from simulations and daftafom the field will be presented to support the proposed solutions.

Electronics is relentlessly gaining new space in automotive. Different application types are converging into the car to increase comfort, performances, safety and entertainment. Many of these applications come from the so-called "consumer" domain which is traditionally undergoing to less severe quality constraints with respect to "automotive grade" products. Automotive products are often heavily tested, with multiple passes, and by monitoring quality indicators used as acceptance tests. Cost of test per each finished good is inevitably growing. On the other hand, average price of automotive products is constantly decreasing. Adding always more does test not necessarily means also improving product quality. Or at least, there might be smarter way to get better results.

Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in an IEEE 1500-compliant environment, and on a novel diagnostic algorithm for determining the fault model associated to the retrieved syndromes. An experimental implementation showing the feasibility of the approach is presented

The ITRS roadmap predicts the need for very high testing parallelism to full wafer testing by year 2010. This goal should be achieved with multi-site efficiency well above 90%. This hypothesis put tough requirements on different components of the current concept of test cell. What do we need to achieve these targets? Will the existing and widely adopted contacting technology adequate for that? Will we still be using testers with per pin/site instrumentations? Will the PC be mostly a "passive" piece of hardware? Will we still consider the PC a "consumable"? Which is the economic model behind these new test paradigms? These issues require more discussion. They also require the evaluation of new technologies and why not, to approach differently the partitioning of test resources within the test cell (ATE, probe card, probe station and DUT).

Modern systems-on-chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires taking fast decisions in the selection of structures and strategies at different stages of the design flow: early computation of area overhead, power consumption and test application time are indispensable in order to develop effective and efficient test for the overall chip, while taking into account physical constraints imposed by the available test equipment. Furthermore, once the test strategy has been selected and patterns generated for each module, additional nonnegligible effort is required to integrate the test program in an ATE-readable format. In this paper, we tackle these problems by means of a new software platform, leveraging descriptions of both the core-level test structure and the system-level requirements. Experimental results related to a realistic case of study underline the effectiveness of the tool and its potentialities in the IEEE 1500 environments

Complex SOC's developed in VDSM technologies require adequate solutions to diagnose and analyze yield losses. This paper focuses on the diagnosis of logic circuits embedded in SOCs. The core instrument leveraged is ATPG used during test vectors generation and analysis of failures. This work emphasizes the results obtained in systematically applying ATPG diagnosis on failures detected in the manufacturing test floor. Details on diagnosis flow and ATE data collection are given. Experimental results are provided.

This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost of test development, easing the reuse of the available architectures for test and diagnosis of different memory types and minimizing the cost of the external ATE.

Summary form only given. Many ways to outsource test activities has been explored recently. Often subcontractors have been employed to design portion of devices or entire circuits. Often it is also discovered that transferring DFT and test methodologies outside the originating company is critical. The efficiency of test development, and also the quality of product test can be affected. Reaching the target coverage is not the only problem. Defining how to exchange test data and the handoff step in the flow is another crucial issue. Similar problems arise also when outsourcing concerns the ATE test program development. In such cases the risk is loosing the possibility to gain important expertise and skills, for example, concerning critical technology-dependant features of the device. In conclusion, the major concerns are for the diagnostic capabilities that test and DFT should provide. In this perspective, the impact of test outsourcing could really be significant, especially on the test-manufacturing environment, and on the effectiveness of the test data coming from it.

A novel approach is presented for digital generation of an analog waveform suitable for BIST of high-resolution analog-to-digital converters (ADCs). The staircase-like exponential waveform is shown to have properties of a perfectly linear ramp when used as the stimulus for a 3rd order polynomial fitting algorithm that measures offset, gain, 2nd and 3rd harmonic distortion. The technique is particularly suitable for testing high resolution (>12 bits) sigma-delta ADCs in a noisy environment, which can then be used to test digital-to-analog converters (DACs). Experimental results for a 44 kHz 16-bit ADC show that the technique measures distortion with better than 0.01% accuracy in the presence of random and 50 or 60 Hz noise.

This paper deals with the diagnosis of faulty embedded RAMs and outlines the solution which is currently under evaluation within STMicroelectronics. The proposed solution exploits a BIST module implementing a March algorithm, defines a wrapper allowing its interface with a TAP controller, and describes a diagnostic procedure running in the external ATE software environment. The approach allows one to test multiple modules in the same chip through a single TAP interface and is compliant with the proposed P1500 standard for Embedded Core Test. Some preliminary experimental results gathered using a sample circuit are reported, showing the effectiveness of the proposed solution in terms of area and time requirements.