Several proposals for computer data processing and memory systems that exploit the inherent parallelism in programs expressed in data flow form have been advanced recently.These systems have packet communication architecture --each system consists of many units that interact only through the transmission of information packets through channels that link pairs of units.A simulation facility for evaluating the prograranability and potential performance of these proposed data processing and memory systems has been designed.The facility uses microprocessor modules to emulate the behavior of system units or groups of units.By conducting a simulation in accurate scale time a precise extrapolation of performance of a proposed system may be obtained.The user of the facility will specify the system to be simulated in an architecture description language.A host computer translates the system description modules into microprocessor programs and controls the loading and monitors the operation of the microprocessors.Application of the facility is illustrated by considerat:ion of a simple data flow processor.

A processor is described which can achieve highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor is a step toward a practical data-flow processor for a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnecion that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.