Demo Data from VLDB 2026 / reviewers in the wild / expert
Jin S. Zhang
dblp:67/1550
· DBLP profile ↗
7ranked-venue papers
3as first author
0since 2021 · last 2014
0000-0002-1936-7780ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 3 first-authorArtificial intelligence and machine learning · 1Graphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.1 | 3 | 2006 | Linear cofactor relationships in Boolean functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 Using simulation and satisfiability to compute flexibilities in Boolean networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability · DAC 2006 |
Electronic design automation › hardware verification and test
hardware verification |
0.1 | 2 | 2006 | Using simulation and satisfiability to compute flexibilities in Boolean networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability · DAC 2006 |
Electronic design automation › logic synthesis
boolean function analysis |
0.1 | 1 | 2006 | Linear cofactor relationships in Boolean functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation
boolean satisfiability |
0.1 | 1 | 2006 | Using simulation and satisfiability to compute flexibilities in Boolean networks · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation › hardware verification and test
formal verification |
0.1 | 1 | 2006 | Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability · DAC 2006 |
Electronic design automation › logic synthesis › boolean function analysis
symmetry detection |
0.1 | 1 | 2006 | Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability · DAC 2006 |
Electronic design automation › logic synthesis
boolean matching |
0.0 | 1 | 2006 | Linear cofactor relationships in Boolean functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation › logic synthesis › decision diagrams
decision diagram optimization |
0.0 | 1 | 2006 | Linear cofactor relationships in Boolean functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.1structural analysis · 0.1cofactor detection algorithm · 0.1boolean satisfiability · 0.1binary decision diagram · 0.1SAT solving · 0.1BDD · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Improved observer-based Hoo control for fuzzy interconnected systemsabstractIn this paper, based on Lyapunov-Krasovskii functional approach and the decentralized control theory of interconnected systems, we consider the observer-based control design for a class of fuzzy descriptor interconnected systems. Firstly, the stability conditions of the T-S fuzzy model with a prescribed performance level are provided in theorem 1, but there is no efficient algorithm solving the inequalities. Theorem 2 proposes a single-step method, reducing the conservatism of the conditions. This method overcomes the drawback of the two-step approach in other methods. The stability conditions in theorem 1 are the sufficient and necessary conditions of the ones in theorem 2. The parameters of reliable H∞controllers can be found via LMI toolbox in MATLAB software. Finally a numerical example is given to show the validity of the proposed method. Xin R. Liu, Xin M. Hou, Kun Y. Guo, Zong R. Li, Jin S. Zhang |
FUZZ-IEEE | 5 |
| 2006 | Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiabilityabstractClassical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-based method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completely-specified Boolean functions. This is in contrast to previous incomplete circuit-based methods and complete BDD-based methods. Experimental results demonstrate that the proposed method works for large Boolean functions, for which BDDs cannot be constructed. Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske |
DAC | 1 |
| 2006 | Using simulation and satisfiability to compute flexibilities in Boolean networksabstractSimulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the network structure while preserving its functionality. In the first two applications, simulation quickly enumerates most of the solutions while SAT detects the remaining solutions. In the last application, simulation efficiently filters out most of the infeasible solutions while SAT checks the remaining candidates. The experimental results confirm that the combination of simulation and SAT offers a computation engine that outperforms binary decision diagrams, which are traditionally used in such applications. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2006 | Linear cofactor relationships in Boolean functionsabstractThis paper describes linear cofactor relationships (LCRs), which are defined as the exclusive sums of cofactors with respect to a pair of variables in Boolean functions. These relationships subsume classical symmetries and single-variable symmetries. The paper proposes an efficient algorithm to detect LCRs and discusses their potential applications in Boolean matching, minimization of decision diagrams, synthesis of regular layout-friendly logic circuits, and detection of support-reducing bound sets Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2005 | Substrate noise modeling in early floorplanning of MS-SOCsabstractWe propose a frequency-dependent sensitivity model for analog blocks and a noise injection model for digital blocks in application to early design planning of Mixed-Signal System-on-Chips (MS-SOCs). We assume no precise layout information about IP cores is available. We also propose an empirical formula for separation-dependent coupling between large-area noisy ports and small-area sensitive ports for lightly-doped substrates that are preferred for mixed-signal circuits. The interaction between digital and analog blocks is incorporated into our floorplanner, which reduces the overall noise and the number of analog blocks with noise limit violations. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging. Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang |
ASP-DAC | 4 |
| 2005 | Detecting support-reducing bound sets using two-cofactor symmetriesabstractDetecting support-reducing bound sets is an important step in Boolean decomposition. It affects both the quality and the runtime of several applications in technology mapping and re-synthesis. This paper presents an efficient heuristic method for detecting support-reducing bound sets using two-cofactor symmetries. Experiments on the MCNC and ITC benchmarks show an average 40x speedup over the published exhaustive method for bound set construction. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch |
ASP-DAC | 1 |
| 1995 | Parallel feedforward equalization-a new nonlinear adaptive algorithmabstractAdaptive equalization can be used to improve digital data transmission on wireless links with time-varying multipath distortion. It was proved by Zhou, Proakis and Ling (see IEEE Transactions on Communications, vol.38, p.8-24, no.1, 1990) that feedforward schemes are universally capable of approximating any measurable function to any desired degree of accuracy. We propose a new realization of such feedforward scheme to the channel equalization problem, parallel feedforward equalization (PFE). An important feature of the new approach is the decomposition of any equalization into linear and nonlinear components. The new approach chooses F/sub j/(/spl middot/) (j=1, ...) from a family of nonlinear functions to approximate the nonlinear component decomposed from the desired mapping f(/spl middot/). The other new idea proposed in this paper is a measure called nonlinearity distribution which characterizes the nonlinearity in multipath fading channels. The architecture of the new equalization consists of parallel feedforward nonlinear filters, each of them has a specifically tailored nonlinear function F/sub j/(/spl middot/). Jian Zhan, Jin S. Zhang, Fu Li 0004, Zhigang Fan 0001 |
ICASSP | 2 |