The increasing bandwidth demands of the emerging new generation of computer communication networks have led to the utilization of optical fiber as a transmission medium. A new receiver conflict avoidance algorithm for wavelength-division multiplexing (WDM) broadcast-and-select star networks is introduced. The proposed algorithm is based on the use of learning automata in order to reduce the number of receiver conflicts and, consequently, improve the performance of the network. According to the proposed scheme, each node of the network is provided with a learning automaton; the learning automaton decides which of the packets waiting for transmission will be transmitted at the beginning of the next time slot. The asymptotic behavior of the system, which consists of the automata and the network, is analyzed and it is proved that the probability of choosing each packet asymptotically tends to be proportional to the probability that no receiver conflict will appear at the destination node of this packet. Furthermore, extensive simulation results are presented, which indicate that significant performance improvement is achieved when the proposed algorithm is applied on the basic DT-WDMA protocol.

A receiver collision avoidance algorithm for WDM broadcast-and-select star networks is introduced. It is based on the use of learning automata to reduce the number of receiver collisions and, consequently, to improve the performance of the network. Each station has a learning automaton that decides which of the packets waiting for transmission will be transmitted at the beginning of the next time slot. The learning automaton used is a multifeedback automaton, specially designed for the receiver collision avoidance problem of WDM broadcast-and-select star networks. The asymptotic behavior of the system, which consists of the automata and the network, is analyzed. The probability of choosing each packet asymptotically tends to be proportional to the probability that no receiver collision will appear at the destination node of this packet. Extensive simulation results indicate that a significant performance improvement can be achieved when the algorithm is applied on the basic DT-WDMA protocol.>

The development of problem-oriented hardware has become a possibility as a result of current technological advances. New machine architectures can now be defined, reflecting the high performance requirements which are set by specific application areas. Large-scale discrete time simulation is a problem area which demands high-speed processing, especially within the realm of real-time applications. The natural parallelism which characterizes many real-life dynamic systems and remains unexploited in the environment of uniprocessor machines, points decisively towards multiprocessor structures. Although the process-oriented simulation languages have proved very effective in accommodating this kind of parallelism in the corresponding simulation programs, their execution in the uniprocessor machines reverts the situation back to the unhappy reality of serial execution of otherwise independent tasks. SIMULA-67 is a process-oriented language specifically designed for advanced and complex software simulation products. The process structure of SIMULA allows for the definition of concurrent tasks within a SIMULA program which can be executed in parallel within the environment of a multiprocessor system. The analysis and the basic software architectural scheme for a parallel SIMULA machine (PSM) have already been reported by the authors in a previous paper. In the present paper a hardware organization of a PSM is presented. A system architecture is explored which is conceived so as to implement efficiently the execution algorithm (process co-ordination and synchronization algorithm) which has been outlined by the authors in previous papers. The architecture is based upon the master/slave system topology. It incorporates a central controller microprocessor and a number of satellite microprocessors. The interconnection circuitry between the microprocessor and a number of satellite microprocessors. The interconnection circuitry between the microprocessor modules involves a time-sharing system bus and various programmable interrupt control units. Common and private memory modules reside in the system, and DMA transfers are employed to alleviate the controller's workload. The time operational features of the parallel SIMULA machine are also described.

In a recent note1J. S. Hill attempts a criticism of the model for the Ek/D/1 buffer system which we have presented in [1]. His starting point is a discrepancy that he has observed between the results which have been published by Dor [2] for a buffer system with Poisson input and constant removal rate, and the results which J. S. Hill obtained when he applied our model [1, eq. (11)] for k = 1.

For the class of primitive trinomials xP+ xk+ 1 with (k, 2P-1) = 1, shift register constructions are presented which are designed to produce in parallel consecutive patterns, of k-consecutive bits each, of the corresponding m-sequence. The resultant class of register structures preserves the function of equivalent feedback shift registers (FSR's) with composite feedback logic while allowing a saving in the physical implementation which amounts to the complete elimination of modulo-2 adders. This accounts for the high-speed performance of the toggle-registers presented, and makes them suitable for a broad range of applications.

A criterion Is derived for the "q-equipartmon" of the period of m-sequences based on pnmmve trmomlals (PT's), 1 + D q + D" It is shown that the class of PT's with q = 2 t, where t is an integer, can be implemented efficiently so as to produce m parallel q phase-shifted versions of the same m-sequence with relative delays analytically evaluated.These implementations lead to the construction ofeffioent algontlmas for the generation of q-bit pseudorandom number sequences equivalent m correlation performance to the Tausworthe-type generators.The algonthrns are of the GFSR type introduced by Lewis and Payne.The advantage of utthzmg the specific class of PT's is that the mmahzauon procedure is not reqmred.The corresponding linear recurrences threctly yield coding for the generators which delwer q-bit number sequences uncorrelated over a length approximately equal to ( 2It is important that three members of this class, of degreesp = 127, 175, 521, respectively, are Merserm¢ prime KEY WORDS AND PHRASES' m-sequences, pseudorandom number generators, feedback shift registers, pmmtive polynomials, Tausworthe generators, Tootdl, Lewis and Payne, key generators, equipartition of m-sequences, GFSR, linear recurrences CR CATEGORIES 3.15, 5 5, 6.30, 8 1

We propose a systematic way for analyzing split-up feedback shift register structures which generate parallel p-n sequences. The analysis aims towards determining the relative phase shifts among the various realizations of the same p-n sequence. The main design criterion is derived when such systems are used as pseudorandom number generators. The results of this analysis are incorporated in the procedure for constructing pseudorandom number sequences. A case study is presented to demonstrate the construction procedure and in the light of our analysis a critical assessment of a class of generators proposed by W. J. Hurd, is given. Two polynomials of degree n = 20 contained in the table reported by W. J. Hurd have been checked and proved to be nonprimitive. The purpose of this study is to ensure "safe" designs when pseudorandom number generating algorithms are constructed, based on high-degree recursions with many nonzero terms.

In this paper a procedure for forming high-accuracy Gaussian distributed pseudorandom numbers is presented, and a digital system that mechanizes the procedure is suggested. The high accuracy that is obtainable while maintaining high output rates, makes the proposed method comparable to the established software generation methods so far as speed and accuracy are concerned. The approach that is suggested is one that is central limit theorem oriented. Error compensation is provided so that accuracies can be better than 3 percent to within ±4 standard deviations from the center of the distribution, and better than 5 percent at ±6 standard deviations. A formula describing the output of the system is derived and tabulated results are presented. The system can find application as a peripheral device of a general-purpose computer in simulation studies as well as in all fields where high-accuracy Gaussian noise generation is required.

A method for analytically studying the two feedback shift-register pseudorandom sources is presented. It is proved, that contrary to the experimental results that have been reported by various authors, their autocorrelation function is a many-valued function. As a result, some care should be exercised in using these sources, and simulation results that have been obtained with these generators might be appropriately reconsidered.

In this paper the principles which are involved in designing an equipment for producing sequences of pseudorandom pulses, non-Poisson-distributed, are discussed. Design criteria are given and applications are discussed.

The problem of the length of a buffer store required for an Erlang input rate where words are removed at regular intervals is discussed. Analytical expressions relating buffer length to the loss resulting from overflow are derived. Graphical results are presented for a range of Erlang distributions.

This paper is a case study of a general method for designing generators of repeatable non-Poisson sequences of pseudorandom pulses. A class of normal distributions and some classes of skew distributions are derived. Block diagrams and design guides are given. The study is based both on analytical and simulation approaches. Applications of the proposed system may be found in the field of hardware simulation techniques and in more efficient arrangements of general purpose machines where they are used in simulation studies.