In deep submicron nodes, the final design patterning quality depends profoundly on the optical proximity correction (OPC) quality. The required pattern fidelity and CD uniformity can never be achieved without good OPC. However, OPC runtime-resource factor has been exponentially increasing every technology node reaching alarming levels, where the OPC cost in terms of resources and turn-around-time is becoming very expensive. In this paper, we present a novel approach for speeding up the OPC convergence process using our model-based initial bias methodology. Our proposed methodology is based on building generic compact bias-models that can predict the final OPC shapes with a good accuracy using the optical simulation parameters. As a result, the OPC initial condition is much closer to the final solution and more than half of the OPC iterations can be saved as a result. In this paper, we present the details of our methodology and our compact initial-bias model we are proposing. We also present our testing results on a 10 nm metal level, where almost 50% of the OPC iterations could be saved when we apply our methodology.

SRAM has become the dominant block in modern ICs and constitutes more than 50% of the die area. The increase of process variations with continued CMOS technology scaling is considered one of the major challenges for SRAM designers. This process variations increase causes the SRAM cells to functionally fail and reduces the chip functional yield considering the static noise margin stability failures (i.e., cell flips when accessed), write failures (i.e., cell is not written within the write window), and read access failures (i.e., incorrect read operation). In this paper, novel negative capacitance circuits are developed, for the first time, to statistically improve the SRAM read access yield under process variations by reducing the bitlines parasitic capacitance. Post layout simulation results, referring to an industrial hardware-calibrated TSMC 65-nm CMOS technology, show that the adoption of the negative capacitance circuit to a 512 SRAM cells column is capable of improving the read access yield from 61.9% to 100%.

In this paper, we present a novel methodology for identifying lithography hot-spots and automatically transforming them into the lithography-friendly design space. This fast model-based technique is applied at the mask tape-out stage by slightly shifting and resizing the designs. It implicitly does a similar functionality as that of the Process Window OPC (PWOPC) but more efficiently. Being a relatively fast technique it also offers the means of providing the designer with all the design systematic deviations from the actual (on-wafer) parameters by including it in the parameter-extraction flow. We applied this methodology successfully to 28-nm Metal levels and showed that it efficiently (better quality and faster) improves the lithography-related yield and reliability issues.

In this paper, a method is proposed to accurately estimate the power yield, considering process-induced temperature and supply voltage variations. Process variations impose statistical behavior on the temperature and leakage current. This, in turn, impacts the IR drops due to the variations in the current, drawn off the power grid. By considering the process-induced statistical profile of the temperature and Vdd, the power yield is estimated for a chip. This helps check the robustness of the circuits early in the design process. The experimental results on the ISCAS89 benchmarks indicate a significant yield loss, if the statistical measures of the temperature and voltage drop are ignored. Monte Carlo simulations verify the accuracy of the developed methodology.

An analog adaptive body bias (A-ABB) circuit is proposed in this paper. The A-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The A-ABB consists of threshold voltage estimation circuits and analog control of the body bias performed by on-chip amplifier circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are demonstrated. This study shows that the proposed A-ABB reduces the standard deviations of the frequency, the dynamic power and the leakage power by factors of 6.6 X, 8.8 X, and 3.3 X, respectively, when both D2D and WID variations are considered. In addition, in this presented case study, initial total yields of 16.8% and 5.2% are improved to 99.9% and 84.1%, respectively. The advantage of the proposed A-ABB is its lower area overhead allowing it to be used at lower granularity level than that of the previously published ABB circuits.

The Latin hypercube sampling (LHS) has been used as a variance-reduction estimation tool for an efficient sampling-based variability analysis of analog circuits. For a certain estimation confidence interval, a lower number of LHS samples is needed than that of Monte Carlo due to the estimation variance reduction. In this paper, an analysis of variance decomposition of the indicator function, the yield function, reveals strong contribution of interactive terms in the variance of the yield function, leading to limited performance gain of the traditional LHS sampling. In order to improve its efficiency, two correlation-controlled LHS methods are developed to reduce the required number of LHS samples for analog circuit yield estimation.

IR-drop management in the power supply network of a chip is one of the critical design challenges in nanometer VLSI circuits. Techniques developed for application-specific integrated circuits cannot be directly applied for IR drop management in field-programmable gate arrays (FPGAs) because of the programmable nature of FPGAs. This paper proposes a novel clustering technique for improving the supply voltage profile in power grid of FPGAs. The proposed clustering technique not only improves the minimum voltage at any node in the circuit, but also reduces the variance in supply voltage across the nodes in the power grid. Results indicate that a reduction of up to 36% in IR-drop and 27% in spatialVddvariation can be achieved using the proposed clustering technique.

Sub-threshold SRAM cells are attractive because of their low leakage power and low access energy. However, the susceptibility of sub-threshold SRAM cells to soft errors is high due to their low supply voltage, high density, and shrinking geometry. Moreover, the increase in statistical variations in advanced nanometer CMOS technologies poses a major challenge for sub-threshold circuits designers. In this paper, analytical models for the sub-threshold SRAM critical charge variations, which account for both die-to-die (D2D) and within-die (WID) variations, are proposed. The derived models are then compared with Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper also provides novel design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. In addition, it demonstrates that the relative critical charge variability is minimum at a certain temperature value. Then, the circuit designer can employ these results with temperature control techniques to minimize the critical charge variability in the early design cycles, especially, for applications with strict soft error rate (SER) constraints. In Zaddition, the proposed models show that the device sub-threshold swing coefficient can be optimized to minimize the relative critical charge variability.

A direct adaptive body bias (D-ABB) circuit is proposed in this paper. The D-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations, and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The D-ABB circuit consists of threshold voltage estimation circuits and direct control of the body bias performed by on-chip direct controller circuits. Circuit level simulation results of a circuit block case study, extracted from a real microprocessor critical path, referring to an industrial hardware-calibrated 65-nm CMOS technology transistor model, are presented. These results show that the proposed D-ABB reduces the standard deviations of the frequency, the dynamic power, and the leakage power by factors of 5.5×, 6.4×, and 4.5×, respectively, when both D2D and WID variations are considered. In addition, in the presented case study, initial total yields of 16.8% and 13% are improved to 100% and 91.4%, respectively. The proposed D-ABB circuit exhibits lower area overhead compared to the other ABB circuits reported in the literature.

Nanometer SRAM cells are more susceptible to the particle strike soft errors and the increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, an analytical model for the critical charge variations accounting for both die-to-die (D2D) and within-die (WID) variations, over a wide range of bias conditions, is proposed. The derived model is verified and compared to Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper shows the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. It demonstrates that the adoption of the coupling capacitor reduces the critical charge variability. The derived analytical model accounts for the impact of the supply voltage, from 0.1 to 1.2 V, on the critical charge and its variability.

The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in digital circuits. However, these techniques, the Quasi-MC method and the order-statistics base estimator, are prone to bias or negligible improvement upon the crude-MC method when an early-stage timing analysis with few (10s) simulation iterations can be afforded. In this paper, these issues are studied and a control variate-base technique is developed to accurately estimate the moments of circuits' critical delays with very few timing simulation iterations. A skew-normal distribution is then used to form a closed-form cumulative distribution function of timing yield. Analysis of the benchmark circuits shows 3-10X reduction of the confidence interval ranges of the estimated yield compared to the crude-MC translating to 9-100X reduction in the number of samples for the same analysis accuracy.

The Monte Carlo (MC) simulation is a well-known solution to the statistical analysis of analog circuits in the presence of device mismatch. Despite MC's superior accuracy compared with that of the sensitivity-based techniques, an accurate analysis that involves traditional MC-based techniques requires large number of circuit simulations. In this paper, a correlation controlled sampling technique is developed to enhance the quality of the variance estimations. The superiority of the developed technique is verified by variability analysis of the input-referred offset voltage of a comparator, the frequency mismatch of a ring oscillator, and the AC parameters of an operational transconductance amplifier.

This paper briefly describes the PhD research work on Robust FPGA Design Under Variations. The work proposes design techniques in three primary areas, viz., power yield enhancement, timing yield enhancement and IR-drop reduction. An architecture and CAD enhancement technique is proposed for improving the timing yield of FPGAs under process variations. Two different techniques are proposed for improving the power yield of FPGAs under process variations. The first technique reduces spatial correlation among leaking blocks to reduce leakage variability, whereas the second technique sizes the transistors of the buffers in the interconnects to reduce leakage variability. For IR-drop reduction, two different CAD techniques are proposed. The first design methodology is an IR-drop aware place and route technique which reduces local switching activities in a region to reduce IR-drops. The second approach is an IR-drop aware clustering methodology. This methodology reduces the clustering of high switching activity nets in a logic cluster to improve the supply voltage profile.

Parametric yield loss has become a significant issue in the design of nanometer integrated circuits (IC). In this paper, the impact of supply (Vdd) and threshold voltage (Vth) variations on the yield loss for the current and future CMOS technologies is investigated. The results demonstrate that, despite the temporary improvement due to the use of high-k dielectric materials and metal gates (HiK+MG), parametric yield and design robustness will remain amongst the major challenges in the future technology generations. Subsequently, design centers in the Vth-Vddplane are suggested for having more robust and reliable circuits for the nodes. Monte-Carlo simulations using SPECTRE and HSPICE verify the provided results in this work for 90nm to 16nm nodes.

In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for delay, energy, and energy-delay product (EDP) overheads to achieve this power yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has the lowest overheads while the modified clocked CMOS master slave flip-flop (M-C2MOS-MSFF) exhibits the largest overheads, and correspondingly, it is not recommended for sub-threshold operation.

Dynamic logic circuits are considered the best choice for high performance applications due to their relatively high speed. These high performance applications have strict timing constraints. Moreover, process variations create a large variability in the dynamic circuit delay in scaled technologies impacting the timing yield. In this paper, the negative capacitance is adopted, for the first time, for statistical timing yield improvement under process variations. Simulation results show that the adoption of the negative capacitance at the output of a 16-input dynamic NOR gate improves the timing yield by reducing the dynamic circuit delay. In addition, the negative capacitance adoption results in power saving of 10% and reduces the delay variability by 57.6%.

The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. However, a precise analysis that involves a traditional MC-based technique requires many simulation iterations, especially for the extreme quantile points. In this paper, advanced sampling and variance reduction techniques, along with applications for efficient digital circuit timing yield analysis, are studied. Three techniques are proposed: 1) an enhanced quasi-MC-based sampling which generates optimally low-discrepancy samples suitable for yield estimation of digital circuits; 2) an order-statistics based control variate technique that improves the quality of the yield estimations, when a moderate number of samples is needed; and 3) a classical control-variate technique utilized for a variance-reduced critical delay's statistical moment estimation. This solution is shown to be effective even for a very low number of samples.

This paper presents novel computer-aided design (CAD) techniques for mitigating IR-drops in field-programmable gate arrays (FPGAs). The proposed placement and routing relies on reducing the switching activities in local regions in the FPGA fabric to improve the profile of the supply voltage distribution. The proposed techniques reduce IR-drops and the variance of the supply voltage distribution across all the nodes in the power grid network. The proposed CAD techniques are efficient as they do not require solving the power grid model at every placement and routing iteration. A reduction of up to 53% in maximum IR-drop and up to 66% reduction in standard deviation of is obtained from the design techniques proposed in this paper with an average impact of 3% on circuit delay.

Embedded SRAM dominates modern SoCs, and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, the large increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. In the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operations and meet yield targets. In this paper, we propose a new architecture that significantly reduces the array switching power for SRAM. The proposed architecture combines built-in self-test and digitally controlled delay elements to reduce the wordline pulsewidth for memories while ensuring correct read operations, hence reducing the switching power. Monte Carlo simulations using a 1-Mb SRAM macro in an industrial 45-nm technology are used to verify the power saving for the proposed architecture. For a 48-Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it an attractive solution for 45-nm-and-below technologies.

Yield loss due to timing failures results in diminished returns for field-programmable gate arrays (FPGAs), and is aggravated under increased process variations in scaled technologies. The uncertainty in the critical delay of a circuit under process variations exists because the delay of each logic element in the circuit is no longer deterministic. Traditionally, FPGAs have been designed to manage process variations through speed binning, which works well for inter-die variations, but not for intra-die variations resulting in reduced timing yield for FPGAs. FPGAs present a unique challenge because of their programmability and unknown end user application. In this paper, a novel architecture and computer-aided design co-design technique is proposed to improve the timing yield. Experimental results indicate that the use of proposed design technique can achieve timing yield improvement of up to 68%.

Simultaneous multithreading (SMT) processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is significantly increased, straining the power budget of the processor. This increases not only the dynamic power consumption, but also the leakage power consumption due to the increased temperature. In this paper, a comparison of the static and dynamic sleep signal generation techniques for SMT processors is presented. This is conducted under various workloads to assess their effectiveness in leakage power management. Results show that the dynamic approach exhibits a threefold increase in leakage savings, compared with that of the static approach for certain functional units.

In this paper, an adaptive sampling method is proposed for the statistical SRAM cell analysis. The method is composed of two components. One part is the adaptive sampler that manipulates an alternative sampling distribution iteratively to minimize the estimated yield error. The drifts of the sampling distribution are re-configured in each iteration toward further minimization of the estimation variance by using the data obtained from the previous circuit simulations and applying a high-order Householder's method. Secondly, an analytical framework is developed and integrated with the adaptive sampler to further boost the efficiency of the method. This is achieved by the optimal initialization of the alternative multi-variate Gaussian distribution via setting its drift vector and covariance matrix. The required number of simulation iterations to obtain the yield with a certain accuracy is several orders of magnitude lower than that of the crude-Monte Carlo method with the same confidence interval.

This work describes a novel approach for total power estimation in field-programmable gate arrays (FPGAs) while considering spatial correlation among the different signals in the design. The signal probabilities under spatial correlations are used to properly model the dynamic power dissipation and the state-dependency of the leakage power dissipation in the logic and routing resources of FPGAs. Moreover, the proposed model accounts for power due to glitches. The accuracy of the developed power estimation technique is compared with that of HSpice simulations and other FPGA power estimation techniques that assume spatial independence. It is found that the spatial independence assumption can overestimate power dissipation in FPGAs by an average of 19%.

The increase of process variations in advanced CMOS technologies is considered one of the biggest challenges for SRAM designers. This is aggravated by the strong demand for lower cost and power consumption, higher performance and density which complicates SRAM design process. In this paper, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow enables early SRAM yield predication and performance/power optimization in the design time, which is important for SRAM in nanometer technologies. The methodology is verified using measured silicon yield data from a 1 Mb memory fabricated in an industrial 45nm technology.

The Monte-Carlo (MC) technique is a well-known solution for statistical analysis. In contrast to probabilistic (non-Monte Carlo) statistical static timing analysis (SSTA) techniques, which are typically derived from simple statistical or timing models, the MC-based SSTA technique encompasses complicated timing and process variation models. However, a precise analysis that involves a traditional MC-based technique requires many timing simulation runs (1000s). In this paper, the behavior of the critical delay of digital circuits is investigated by using a Legendre polynomial-based ANOVA decomposition. The analysis verifies that the variance of the critical delay is mainly due to the pairwise interactions among the principal components (PCs) of the process parameters. Based on this fact, recent progress on the MC-based SSTA, through Latin hypercube sampling (LHS), is also studied. It is shown that this technique is prone to inefficient critical delay variance and quantile estimating. Inspired by the decomposition observations, an efficient algorithm is proposed which produces optimally low L2-discrepancy quasi-MC (QMC) samples which significantly improve the precision of critical delay statistical estimations, compared with that of the MC, LHS, and traditional QMC techniques.

Technology scaling introduces major challenges in yield and performance with the employment of standard single-gate MOSFETs, traditional metal interconnects, and the classical 2-dimensional integration technology. Therefore, there is a need for innovative technologies aimed at enhancing the integration density, performance, and reliability of nanoscale chips. Promising technologies to resolve the degrading performance of devices and interconnects include: (1) 3-dimensional chip stacking with vertical interconnections through chips, (2) on-chip carbon nanotubes as a replacement for metal interconnects , and (3) scalable devices such as double gate FinFETs with lower leakage current characteristics as compared to the standard single-gate transistors. This paper introduces those three promising technologies and highlights the associated opportunities and challenges.

Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks for digital subthreshold logic circuits. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this paper, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. By using the technique, a process/device designer can optimize a transistor for subthreshold operation in terms of the total leakage current and intrinsic delay bounds. Sample devices are optimized for 90 nm and 65 nm technologies, and Monte Carlo simulations verify the accuracy of the technique.

A new low power multiplication algorithm for reducing the switching activity through operand decomposition for Radix-8 Booth multiplier is proposed. The proposed algorithm incorporates our proposed Redundant Binary Signed Digit (RBSD) Modified Booth-3 (Radix-8) encoding scheme to generate RBSD partial product rows and low power RB Adder unit designed for accumulation and thereby circumventing the need to generate hard multiples and sign extension. Experimental results show a reduction of 21% in dynamic power consumption and at least 44% reduction in Energy Delay Product (EDP) with a penalty of 4% in area.

The increase of statistical variations in advanced nanometer CMOS technologies poses a major challenge for digital circuit design. In this paper, we study the impact of random variations on the delay variability of a gate and derive simple and scalable statistical models to effectively evaluate delay variations in the presence of within-die variations. The derived models are verified and compared to Monte Carlo SPICE simulations using industrial 90-nm technology. This paper provides new design insight and highlights the importance of accounting for the effect of input slew on delay variations, particularly at lower supply voltages. We also show that, for a given supply voltage, there is an optimum input slew that minimizes the relative delay variation of the gate. We present conditions to achieve this minimum. The derived analytical models account for the impact of supply voltage and output loading and can be used in early design cycle. These results are particularly important for variation-tolerant design in nanometer technologies, particularly in low-power and low-voltage operation.

Variations in supply (Vdd) and threshold voltages (Vth) significantly impact parametric yield. These variations also affectVddandVthscaling, two power reduction techniques that effectively reduce dynamic and static power consumption. This paper presents a statistical methodology for maximizing yield and optimizing supply and threshold voltage scaling under theVddandVthvariations. A design-specific feasible region is constrained by a minimum performance and maximum temperature in theVth-Vddplane. A tolerance box is placed in the feasible region so that its center provides the nominal values forVddandVthsuch that the design has a maximum immunity to the variations and maximizes the yield for the given constraints. It is demonstrated that the location of the tolerance box and, therefore, the values ofVddandVthdepend on the design metrics, circuit switching activity, transistor sizing, and the given constraints. Monte Carlo simulations indicate a 25% increase in the yield for 90-nm CMOS technology. In addition, the methodology can be adopted as a variability-aware guideline in a design specific power and performance optimization and is applicable to both continuous and discrete voltage scaling. SPECTRE simulations verify the developed method.

In this paper, a leakage power reduction technique for field-programmable gate arrays (FPGAs) is proposed based on the state dependency property of leakage power. A pin reordering algorithm is proposed, where the subthreshold and gate leakage power components are taken into consideration to find the lowest leakage state for the FPGA pass-transistor multiplexers in the logic and routing resources without incurring any physical or performance penalties. The newly developed methodology is applied to several FPGA benchmarks, and an average leakage savings of 50.3% is achieved in a 90-nm CMOS process. Moreover, a modified version of the methodology is implemented to improve the performance of the final design, and again, considerable leakage power savings are achieved. Furthermore, the methodology is extended to find the lowest leakage states for several future predictive Berkeley CMOS technologies.

As CMOS technology is scaled down toward the nanoscale regime, drastically growing leakage currents and variations in device characteristics are becoming two important design challenges. Traditionally, the device-design methodology is based on finding the device parameters which minimize the leakage current while providing a minimum saturation current for the transistor. This methodology may change when variations are accounted for design. In this paper, a novel device optimization methodology is presented that incorporates variability awareness into the device-design flow such that the designed device satisfies desired bounds on total leakage, saturation current, and intrinsic delay under parameter variabilities. The technique locates the maximum-yield rectangular cube in the 5-D feasible space composed of oxide-thickness, gate-length, and channel-doping profile parameters. The center of this cube is considered as the maximum-yield design point with the highest immunity against variations. By using the methodology, four high-performance (HP) and low-power devices in 90-nm technology and one HP device in 65 nm have been designed. Monte Carlo simulations have been done to investigate the devices' performance and power metric variations and to verify their yield maximality.

The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultra-deep submicrometer designs. To correctly predict performance/ leakage/reliability measures and address any yield losses during the early stages of design phases, it is desirable to have a reliable thermal estimation of the chip. However, the leakage power sources vary greatly due to process variations and temperature, which result in significant variations in the hotspot and thermal profile formation in very large scale integration chips. Traditionally, no leakage variations have been considered during full-chip thermal analysis. In this paper, the dependence behavior among the process variability, leakage power consumption, and thermal profile construction are established to effectively extract a reliable statistical thermal profile over a die at the microarchitectural level. Knowledge of this is the key to the design and analysis of circuits. The probability density functions of temperatures are extracted while considering the leakage variations due to the gate-length and oxide-thickness variations and while accounting for the coupling between the temperature and the total leakage. Two applications of the developed analyzer are investigated, namely, the evaluation of the hotspots' relocations and the total full-chip power estimation. Finally, the accuracy and efficiency of the developed analyzer are validated by comparisons with Monte Carlo simulations.

Power gating techniques are rapidly gaining popularity assisting the management of leakage power consumption for deep submicrometer microprocessors' functional units. Power gating is based on an input sleep signal to set the functional unit into a low leakage mode. However, power gating techniques in general inherently lack information about the utilization profile of the functional units they manage. This limitation is usually handled either statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles or dynamically by changing the number of cycles before the sleep signal is generated depending on the previous history of operation. In this paper, a comparative study between the static and dynamic approaches regarding the power-performance tradeoff will be presented. It will be shown that the dynamic sleep signal generator is capable of tracking the operation of the functional units while achieving accuracies up to 90% compared to an average of 40%-60% for the static sleep signal generator (SSSG). Additionally it saves up to 80% more leakage versus the SSSG. This study is very important in assisting circuit designers choose between both techniques depending on the power gated circuit.

A timing-driven MTCMOS (T-MTCMOS) CAD methodology is proposed for subthreshold leakage power reduction in nanometer FPGAs. The methodology uses the circuit timing information to tune the performance penalty due to sleep transistors according to the path delays, achieving an average leakage reduction of 44.36 % when applied to FPGA benchmarks using a CMOS 0.13mum process. Moreover, the methodology is applied to several FPGA architectures and CMOS technologies.

Process variations are becoming of increasing importance in nanometer CMOS regime. This paper reviews the challenges associated with variability and variation-tolerant design in nanometer CMOS. It highlights how design decisions, circuit techniques, and architecture decisions are modified to address the difficulties posed by the large increase in process variations.

Field-programmable gate arrays are attractive candidates for wireless applications due to their reconfiguration capability and high performance development. However, sub-threshold leakage power in modern FPGAs has become a critical obstacle for these devices in entering to this application domain. Subthreshold leakage current of programmable interconnections is responsible for most of the static power dissipation. This work proposes and evaluates ten routing designs based on the dual-threshold technique to reduce leakage power. Alternating between buffers and pass transistors, we analyze the percentage constitution of low-Vthand high-Vthtransistors as a function of the leakage reduction and delay increment tradeoff. By routing a suite of MCNC benchmark circuits, we show that an average savings of about 28.83% (as high as 48.46%) in total interconnect leakage can be obtained with 8.73% worst case average delay penalty.

Managing leakage power in field programmable gate arrays (FPGAs) has become critical for the FPGA industry to remain competitive in the semiconductor market and enter the mobile applications domain. This paper proposes and evaluates several dual-Vt-based designs of FPGA architecture for reducing the leakage power. A dual-Vt FPGA computer-aided design (CAD) framework has been proposed, which is used to develop and evaluate different dual-Vt FPGA architectures. The logic elements and the routing resources are considered as candidates for dual-Vt assignment. The authors estimate the number of the logic elements that can be assigned as high-Vt in the ideal case by using a dual-Vt assignment algorithm in the CAD framework. Based upon this estimate, the authors develop and evaluate two kinds of architectures, homogenous and heterogenous. The results indicate that an average leakage-power savings of up to 50% can be obtained from these architectures. This CAD framework can also be used for developing and evaluating different dual-Vt FPGA architectures other than the ones proposed in this paper

In this paper we present a state dependent analytical leakage power model for FPGAs. The model accounts for subthreshold leakage and gate leakage in FPGAs, since these are the two dominant components of total leakage power. The power model takes into account the dependency of gate and subthreshold leakage on the probability of the state of circuit inputs. The leakage power model has two main components, one which computes the probability of a state for a particular FPGA circuit element, and the other which computes the leakage of the FPGA circuit element for a given input using analytical equations. This FPGA power model is particularly important for rapidly analyzing various FPGA architectures across different technology nodes

In this paper, a novel device optimization methodology is presented that is constrained by the total leakage and the ON current of the device. The devised technique locates a maximum yield rectangular cube in a three-dimensional feasible space composed by oxide thickness, halo peak doping, and halo characteristic length parameters. The center of this cube is considered as the maximum yield design point with the highest immunity against variations. Monte-Carlo simulations show that the optimized Bulk-MOS device for 45 nm gate length satisfies the on current and leakage constraints under a variability of up to 30% in the three parameters.

Leakage power is projected to comprise approximately 50% of the processor's power for sub 65 nm technologies. Much of this power is consumed in the processor's functional units. Accordingly, leakage control techniques are employed to reduce leakage in these functional units. Many of these techniques are dynamic and are based on an input sleep signal to initiate a low leakage mode. However, since most of these leakage control techniques are based on circuit level schemes, such techniques inherently lack information about the operational profile of the functional units they manage. This limitation is usually handled statically by using a fixed length counter that generates the sleep signal when the functional unit is idle for a specified number of cycles. In this paper, the limitations of the static sleep signal generation approach are identified, and the use of a dynamic alternative that is capable of adopting the counter length to the running application is proposed. In order to assess the accuracy of the proposed dynamic sleep signal generator, the length of the sleep period following the sleep signal generation is used as a metric to identify the usefulness of utilizing the dynamic approach. Experimental results for the dynamic alternative shows up to 98% accuracy in predicting the length of the standby period compared to an average of 40-60% in the static case, which translates into increased leakage savings. This is achieved while consuming 360 muW of overhead power at 1 GHz

In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a connection-based packing technique by which the proximity of the logic blocks is accounted for, and the second algorithm is a logic-based packing approach by which the weighted Hamming distance between the block activities is considered. After both algorithms are analyzed, they are applied to a number of FGPA benchmarks for verification. Once the activity profiles are realized, sleep transistors are carefully positioned to contain the clustered blocks that share similar activity profiles. Finally, the percentage of the leakage power savings for each of the two algorithms is evaluated.

We highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a number of random variables while accounting for spatial correlations. Our methodology sorts the probability density functions (PDFs) of the critical paths of a circuit based on a confidence-point. We show the mathematical accuracy of our method and also implement a typical program to test it on various benchmarks. We find that the worst-case analysis overestimates path delays by more than 50% and that a path's probabilistic rank with respect to delay is very different from its deterministic rank.

FPGAs are witnessing a big increase in their applications, especially with the introduction of state-of-the-art FPGAs using nanometer technologies. This has been accompanied with a big increase in power dissipation in FPGAs, which forms a road block to the integration of FPGAs in several hand-held applications. Motivated by the increase in the percentage of leakage power dissipation to the total power dissipation in modern technologies, this work presents a complete CAD flow to mitigate leakage power dissipation in FPGAs. The algorithm is based on a FPGA architecture that employs multi-threshold CMOS technology. The flow is based on the VPR flow and it aims to pack and place logic blocks that exhibit similar idleness close to each other so that they can be turned off during their idle time. The flow is tested with a CMOS 0.13 m dual-vth technology and achieved an average power saving of 22%.

Leakage power has been overshadowed by dynamic power minimization techniques in FPGAs, and is a growing concern in programmable logic. This paper proposes a dual threshold voltage implementation of the FPGA architecture for leakage power reduction. A CAD flow is developed for assigning high threshold voltage to the logic elements within the logic blocks of the FPGA for leakage power reduction. The CAD flow ensures that all the logic blocks remain identical with respect to the number of high and low threshold voltage logic elements that each logic block contains. This CAD flow leads to a dual threshold voltage implementation for the FPGA architecture. Results indicate that over 95% of the logic elements in the FPGA can be assigned high threshold voltage. On an average leakage savings of 60% and up to 70% for some benchmarks can be achieved. The proposed CAD flow forms a basis on which other dual threshold voltage implementations of FPGA can be evaluated. We investigate the design trade-offs between the ratio of the number of high and number of low-Vt logic elements in a cluster and the leakage savings. We also investigate the impact of cluster size on leakage savings for the dual threshold voltage implementation.

As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPGAs CAD flow to mitigate leakage power dissipation through the use of multi-threshold CMOS technologies to pack and place logic blocks that exhibit similar idleness close to each other so they can be turned off during their idle time. The modifications are integrated into the VPR flow and tested on several FPGA benchmarks using a CMOS 0.13μm dual-Vth technology, resulting in an average leakage power savings of at least 20%

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.

As VLSI technologies scale down, the average die size is expected to remain constant or to slightly increase with each generation. This results in an average increase in the global interconnect lengths. To mitigate their impact, buffer insertion has become the most widely used technique. However, unconstrained buffering is expected to require several hundreds of thousands of global interconnect buffers. This increased number of buffers is destined to adversely impact the chip power consumption. In this paper, an optimal power maze routing and buffer insertion/sizing problem for a two-pin net is formulated, as a shortest paths ranking problem. The pseudopolynomial time bound of the new formulation fits well within the context of the increased number of buffers. In fact, power savings as high as 25% for the 130-nm technology with a 10% sacrifice in delay is achieved. Furthermore, with the advent of dual threshold technologies, power sensitive applications can substantially benefit from adopting dual threshold buffers. Accordingly, the proposed problem formulation is extended to incorporate the selection of the buffer threshold voltage, where a twofold increase in power savings is observed. During the assessment of the impact of technology scaling using a set of MCNC Benchmarks, an average power saving as high as 35% with a 10% sacrifice in delay is observed. In addition, there is a 10% variation in the power savings when accounting for the process variations.

An automated optimization-based design strategy is proposed for single-level MOS Current Mode Logic (MCML) gates to overcome the complexities of the gate design procedure. The proposed design methodology determines the values of the design variables that achieve the minimum power dissipation point while attaining the required performance. The proposed design methodology has the advantage of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on the MCML gate performance is presented. The proposed strategy is used to design two popular circuits, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the gate parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as the technology scales down is investigated.

Reducing power dissipation is one of the most important issues in very large scale integration design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multithreshold technology has emerged as a promising technique to reduce leakage power. This paper presents several heuristic techniques for efficient gate clustering in multithreshold CMOS circuits by modeling the problem via bin-packing (BP) and set-partitioning (SP) techniques. The SP technique takes the circuit's routing complexity into consideration which is critical for deep submicron (DSM) implementations. By applying the techniques to six benchmarks to verify functionality, results obtained indicate that our proposed techniques can achieve on average 84% savings for leakage power and 12% savings for dynamic power. Furthermore, four hybrid clustering techniques that combine the BP and SP techniques to produce a more efficient solution are also devised. Ground bounce was also taken as a design parameter in the optimization problem. While accounting for noise, the proposed hybrid solution achieves on average 9% savings for dynamic power and 72% savings for leakage power dissipation at sufficient speeds and adequate noise margins.

Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic.

A new high-speed domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.