The cache memory has been a predominant component in modern chips, easily taking up more than 50% of the silicon area. It is then desirable to make the cache memory flexible for different needs. Therefore, many modern processor chips allow users to configure a part of the cache memory as the scratch-pad memory (SPM), a high-speed internal memory for rapid data access. However, such approach uses only the data RAM of the cache memory while leaving the tag RAM unused and thus wasting its capacity. This paper presents a cache organization, called Tag-SPM architecture, which allows the tag RAM to be used as the SPM and thus increases its capacity. It is accomplished with small Tag/Data-SPM controllers and four additional multiplexers in the cache organization. The proposed Tag-SPM architecture has been implemented with an academic ARM-based microprocessor with 4-/4-kB four-way set-associative instruction/data caches at the register transfer level level. Experiments show that the proposed architecture boosts the SPM capacity by 12.5% and requires only 0.08% area (434 gates) overhead without impairing the cache's circuit speed in TSMC's 90-nm standard cell implementation. Furthermore, the power overhead is negligible. When the Tag-SPM architecture is applied to typical cache systems, such as in ARM's Cortex-A5 and Cortex-A53 processors, additional 12.5% SPM space per way can also be gained in both cases. The analyses show that our Tag-SPM architecture is a highly cost-effective way to boost the SPM space.

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real-time program trace compressor, named trace-capable cache (TC-cache). It is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource and power consumption. The TC-cache can be configured to work simultaneously as the instruction cache and the trace compressor, named the online mode, or exclusively as the trace compressor, named the bypass mode. The RTL implementation of a 4 KB trace-capable instruction cache, a 4 KB data cache, and an academic ARM processor core has been accomplished. The experiments show that the TC-cache achieves average compression ratio of 90 percent with a very small hardware overhead of 3,652 gates (1.1 percent). It takes only 0.2 percent additional system power for the online mode operation. In addition, the trace support circuit does not impair the global critical path. Therefore, the proposed approach is a highly feasible on-chip debugging/monitoring solution for SoCs, even for cost-sensitive ones such as consumer electronics. Furthermore, the same concept can be applied to the data cache to compress the data address trace as well.

This paper proposes a multiresolution AHB on-chip bus tracer named SYS-HMRBT (aHb multiresolution bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. In addition, it allows users to switch the trace resolution dynamically so that appropriate resolution levels can be applied to different segments of the trace. On the other hand, SYS-HMRBT supports tracing after/before an event triggering, named post-triggering trace/pre-triggering trace, respectively. SYS-HMRBT runs at 500 MHz and costs 42 K gates in TSMC 0.13-m technology, indicating that it is capable of real time tracing and is very small in modern SoCs. Experiments show that the bus tracer achieves very good compression ratios of 79%-96%, depending on the selected resolution mode. As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and monitoring of the system behaviors. The SoC has been successfully verified both in field-programmable gate array and a test chip.

This paper presents an embedded debugging/ performance monitoring engine (EDPME), which is capable of collect run time characteristics, detect AHB on-chip bus protocol error/inefficiency, and capture on-chip AHB bus traces at various abstraction levels with compression ratio up to 98% for a low cost tile-based 3D graphics SoC development.

Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The compression algorithm must be simple for hardware implementation; a common method is to store only the difference between the previous value and the current one. Such differential compression has trouble with the circular buffer that is needed for recording continuous traces. Previous solutions are complex and waste memory. By a transformation that expresses differential compression in reverse form, we derive a new solution that is simpler than previous methods and does not waste memory. Our algorithm is based on an innovative reverse-encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a real-time on-chip advanced high-performance bus tracer and has been embedded in a 3-D graphics system-on-a-chip as an application example. The bus tracer costs only 44 K gates and runs at 500 MHz in TSMC 0.13-¿m technology. Experiments have shown that our bus tracer achieves 100% circular-buffer utilization and captures 4.86 times trace depths as compared with a conventional industrial approach.

This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.

The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challenging problem since the initial state of the trace being compressed might be corrupted when wrapping around occurs and thus, makes it difficult to reconstruct the trace from the incomplete information stored in the circular buffer. This paper proposes an efficient compression algorithm which is capable of compressing both pre-T and post-T traces. The algorithm is based on an innovative reverse encoding scheme by reversing the order of the datum being encoded and the datum being referred. This algorithm has been successfully implemented in a realtime on-chip AHB bus tracer and has been embedded in a 3D graphics SoC as an application example. The bus tracer costs only 44K gates and runs at 500MHz on 0.13um technology. Experiments have shown that this bus tracer achieves 100% circular buffer utilization and captures 1.2x and 4.86x trace depths than state-of-the-art related work and conventional industrial approaches, respectively.

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time program trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.

This demonstration shows how we can enable the SoC debugging and performance evaluation with the reverse-encoding-based on-chip AHB bus tracer. By embedding this bus tracer to a SoC, designers can observe and debug the SoC internal states easily. The bus tracer supports both Pre-Triggering (Pre-T) trace and Post- Triggering (Post-T) trace at high compression ratio. For Post-T trace, designs can monitor signals for a known period at different abstraction level. It is very helpful for designs to realize the top view and detail view of the system for performance evaluation and debugging. Pre-T trace captures signals before an event occurs. It is very helpful for system error diagnosis since the errors are unexpected.

The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique. In this paper, a parameterized embedded in-circuit emulator and its retargetable debugging software are proposed. The parameterized embedded in-circuit emulator can be integrated into different style processors such as microcontroller, microprocessor, and DSP processor. The GUI interface debugging software can help user to debug easily. As a result of it, the duration of microprocessor debugging design procedure time is reduced.

The forward/backward trace refers to the trace captured after/before a target point is reached, respectively. Real time compression of the backward trace in a circular buffer is a challenging problem since the initial state of the trace currently under compression might be overwritten when wrapping around occurs. This paper presents a real time multi-resolution AHB on-chip bus tracer which is capable of capturing and compressing both forward and backward traces in a circular buffer. The backward trace is accomplished with a ping-pong organization of dual forward trace compression engines. While one module is compressing the trace, the other is clearing up its internal data structure. The roles of the two engines are exchanged periodically. The Bus Tracer, costs 60K gates and runs up to 500MHz in TSMC 0.13μm technology. The experiments show that our approach achieves 2.32 to 3.98 times in effective trace depth than traditional circular buffer approaches.

The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with other IP components, they suffer from the complicated bus protocol and IP conflict problems. This paper proposes a automatic method to verify the microprocessor external interrupt behaviors on the OCB. The verification approach is based on the Processor External Interrupt Verification Tool (PEVT) whose simulation environment is direct-connected memory. In this paper, we implement the PEVT-SoC and successfully verify two SoC platforms, one academic microprocessor and one public domain microprocessor. An interesting bug appears that is impossible to be discovered in the memory bus and not easy to be identified on the OCB. The result shows that the PEVT-SoC effectively shortens the verification time regardless of the system complexity and can be easily migrated to different platforms/microprocessors. With little human effort, even an inexperience designer can generate extensive verification cases in a systematic way.

Bus-based system-on-chip (SoC) design becomes the major integration methods for shorting design cycle and time-to-market, thus how to verify IP functionality on bus protocol is a challenge. Traditional simulation-based bus protocol monitors can check bus signals obey bus protocol or not, but they often lack of efficient debugging mechanisms .We propose a rule-based bus protocol checker, it contains 73 related bus protocol rules to check bus signal behavior, and two corresponding debugging mechanism to shorten debugging times. Error reference table can summarize design under tests (DUTs) have been violated; Windowed trace buffer can capture multiple errors’ history data that helps designer debug efficiently.

Interrupt behaviors, particularly the external ones, are difficult to verify in a microprocessor. Because the external interrupt arrival time and the microprocessor response time must be precise, verification requires sophisticated hardware and software design. This paper proposes a computer-aided design tool, called processor exception verification tool (PEVT), to verify the external interrupt behaviors of microprocessors, including individual, multiple, and nested interrupts. An architecture description language extension, called Exception Description Language (EXPDL), is developed for the designer to capture the external interrupt behaviors for the microprocessor under verification. PEVT is responsible for generating the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of the ARM7 microprocessor core and a public domain scalable processor architecture (SPARC) microprocessor core. The ARM7 has had a system-on-a-chip test chip and software porting including multimedia applications (MP3/JPEG/ ...) and a real time operating system muC-OSII. PEVT successfully identified several sophisticated remaining bugs with 527 lines of EXPDL description and took only 4 204 961 cycles of register transfer language simulation with execution time of 4.5 h in a SUN Blade2000 workstation. The experiment shows that PEVT could generate highly focused verification cases, less than 98 cycles per case on the average, which identify potential bugs with much less simulation cycles at the early verification stage, compared with traditional manual-based approaches.

This paper purpose an embedded AMBA signal tracer for microprocessor-based SoC's. This tracer provides five trace resolution modes that can perform a cycle-accurate or a transaction-based trace collection in an unlimited time. Also this tracer is implemented in a Soft-IP style. It provides four parameters for tracing configuration. The experimental results show that the bus tracer can reach a good compression ratio of 96%.

A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock frequency comparing to ARM7, even the performance is 67% better in narrow width memory at the same clock frequency. The ARM7 software is also compatible.

The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycle-accurate tracing is large and the trace cycle is shallow unless using a proper compression mechanism. In this paper, we propose an embedded multi-resolution AMBA trace analyzer that provides the trade-off between the trace granularity and the trace depth. It consists of two major trace approaches: (1) the signal monitor/tracing which provides the levels of abstraction, and (2) the trace reduction. In the first approach, it allows designers to zoom-in/out to preferred level of abstraction to serve different debugging purposes. In the second approach, the trace analyzer compresses the traced data according to signal characteristics and the cost of on-chip storage is reduced. The trace data will be decompressed on the host for further observation and debugging. The experimental results show that the proposed approach can reach a good compression ratio of 96% and the trace depth is more than two thousand cycles at the higher abstraction level.

Interrupt behaviors, especially the external ones, are difficult to verify in a microprocessor design project in that they involve both interacting hardware and software. This paper proposes a CAD tool, called PEVT, to verify the external interrupt behaviors of microprocessors. An architecture description language extension, called EXPDL, is developed for the designer to capture the external interrupt behaviors for the microprocessor. PEVT is responsible to generate the verification cases, consisting of both the hardware and software modules, which are then used to trigger the expected behaviors. A monitor is also generated from the EXPDL description to verify these cases. PEVT has been applied to the verification of an academic implementation of ARM7 microprocessor core, which has had a SoC test chip and software porting including MP3 decoder and uC-OSII. PEVT successfully identified several sophisticated remaining bugs with only less than 88,000 cycles of RTL simulation with execution time of 424 seconds in a SUN Blade2000 workstation. The experiment shows that PEVT could generate highly focused verification cases, less than 21 cycles per case on the average, which identify potential bugs with much less simulation cycles, compared with traditional regression tests which consume huge amount of simulation cycles.

Address trace compression represents that the address data, which were generated from instruction fetch stage of microprocessor, can be retrieved for later observation and analysis. In this paper, we present how to design and implement this real-time address trace compressor (RTATC), which can be used to collect the address trace information of FPGA Prototyping system based on embedded microprocessors. Address trace compressor is able to monitor address bus of microprocessor, and to get operation workload under the analysis of profiling software. Address trace compressor is also allowed to perform accurate, successive trace collection in an unlimited length and can be used in different embedded microprocessors. At last, by the help of FPGA, this silicon intelligent property can own the abundant reconfigurable parameters, the removable modules and the reusable ability.

This paper presents the development of instruction analysis/scheduling CAD techniques to measure the distribution of functional-unit usage and the microoperation level parallelism (MLP), which together determine the proper functional-unit allocation for superscalar microprocessors, such as the x86 microprocessors. The proposed techniques fit in the early design exploration phase in which the trace or microarchitecture simulator has not been available. The techniques have been applied to analyze several popular Windows95 applications such as Word, Excel, Communicator, etc., for their MLP and distribution of functional-unit usage. The results are used to evaluate the resource allocation of several existing x86 superscalar microprocessors and suggest future extension.

Ethernet communication devices, such as adapter, hub, bridge and switch, all follow IEEE 802.3 standard protocol. We have designed and implemented an integrated 10/100 Mbps Ethernet MAC (Medium Access Control) mechanism. The MAC unit is used to handle receive/transmit processes of network packet stream. To meet the requirement of different communication devices, we design an automatic MAC unit generator. Users can select the desired number of MAC units through parametric environment setup. To verify the application of MAC unit, we provide a 10/100 Mbps layer-2 switch simulator and an automatic test pattern generator. The FPGA demo system reveals the validity of the MAC unit.

In this paper, we o introduce the Reusable Embedded In-Circuit Emulator (EICE) and Reusable EICE development system. The main function in EICE we design are testing and debugging. The architecture of EICE is reusable and based on IEEE 1149.1 boundary scan architecture. The EICE development system can help EICE to reduce developing time while developing a microcontroller/microprocessor. We implemented EICE by ASIC and FPGA way and the development system had been demonstrated in two microcontroller.

This paper presents a hardware/software co-synthesis approach to pipelined ISP (instruction set processor) design. The approach synthesizes the pipeline structure from a given instruction set architecture (behavioral) specification. In addition, it generates a set of reordering constraints that guides the compiler back-end (reorderer) to properly schedule instructions so that possible pipeline hazards are avoided and throughput is improved. Co-synthesis takes place while resolving pipeline hazards, which can be attributed to interin-struction dependencies (IIDs). An extended taxonomy of IIDs have been proposed for the systematic analysis of pipeline hazards. Hardware/software methods are developed to resolve IIDs. Algorithms based on taxonomy and resolutions are constructed and integrated into the pipeline synthesis process to explore hardware and software design space. Application benchmarks are used to evaluate possible designs and guide the design decision. The power of the co-synthesis tool PIPER is demonstrated through pipeline synthesis of one illustrative example and two ISPs, including an industrial one (TDY-43). In comparison with other related approaches, our approach achieves higher throughput and provides a systematic way to explore the hardware/software trade-off.

Article Free Access Share on A new approach to assembly software retargeting for microcontrollers Authors: Ing-Jer Huang Institute of Computer and Information Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, Republic of China Institute of Computer and Information Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, Republic of ChinaView Profile , Dao-Zhen Chen Institute of Computer and Information Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, Republic of China Institute of Computer and Information Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, Republic of ChinaView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 229–234https://doi.org/10.1145/368434.368615Published:28 January 2000Publication History 0citation107DownloadsMetricsTotal Citations0Total Downloads107Last 12 Months7Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper presents a synthesis tool ICEBERG for embedded in-circuit emulators (ICE's), that are part of the development environment for microcontroller (or microprocessor)-based systems (PIPER-II).The tool inserts and integrates the necessary in-circuit emulation circuitry into a given RTL core of a microcontroller, and thus turning the core into an embedded ICE.The ICE, based on the IEEE 1149.1 JTAG architecture, provides standard debugging mechanisms, including boundary scan paths, partial scan paths, single stepping, internal resource monitoring and modification, breakpoint detection, and mode switching between debugging and free running modes.ICEBERG has been successfully applied to synthesize the embedded ICE for an industrial microcontroller HT48 100 from its RTL core.

The understanding of instruction set usage in typical DOS/Windows applications plays a very important role in designing high performance /spl times/86 compatible microprocessors. This paper presents the tools to such analysis, the analysis results, and their implications on the design of a superscalar processor, based on a RISC core, for efficient /spl times/86 instruction execution. The analyzed results are used to optimize the execution of frequently executed instructions and micro operations.

This paper presents a case study of synthesis and analysis of the industrial embedded microcontroller HT48100, using the hardware/software co-synthesis tool (PIPER-II) for microcontrollers/microprocessors. The synthesis tool accepts as input the instruction set architecture (behavioral) specification, and produces as outputs the pipelined RTL designs with their simulators, and the reordering constraints which guide the assembler how to generate code for the synthesized designs. The study shows that the synthesis approach was able to help the original design team to evaluate their design quality, analyze the architectural properties and explore possible architectural improvements and their impacts in both hardware and software. Feasible future upgrade for the microcontroller family is identified by the study. Further cooperation with the design team has been undertaken to integrate the synthesis methodology into their design flow.

In instruction set serves as the interface between hardware and software in a computer system. In an application specific environment, the system performance can be improved by designing an instruction set that matches the characteristics of hardware and the application. We present a systematic approach to generate application-specific instruction sets so that software applications can be efficiently mapped to a given pipelined micro-architecture. The approach synthesizes instruction sets from application benchmarks, given a machine model, an objective function, and a set of design constraints. In addition, assembly code is generated to show how the benchmarks can be compiled with the synthesized instruction set. The problem of designing instruction sets is formulated as a modified scheduling problem. A binary tuple is proposed to model the semantics of instructions and integrate the instruction formation process into the scheduling process. A simulated annealing scheme is used to solve for the schedules. Experiments have shown that the approach is capable of synthesizing powerful instructions for modern pipelined microprocessors, and running with reasonable time and a modest amount of memory for large applications.>

We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitecture. In addition, the assembly code is generated to show how the application can be compiled with the synthesized instruction set. The design of instruction sets is formulated as a modified scheduling problem. A binary tuple is proposed to model the semantics of instructions and integrate the instruction formation process into the scheduling process. A simulated annealing scheme is used to solve for the schedules. Experiments have shown that the approach is capable of synthesizing powerful instructions for modern pipelined microprocessors. The synthesis algorithm ran with reasonable time and a modest amount of memory for large benchmarks. 1.

One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. We present a new solution to the problem in the domain of pipelined application-specific instruction set processors, based on hardware/software concurrent engineering approach. An extended taxonomy of inter-instruction dependencies is proposed for the analysis of pipeline hazards. Hardware/software resolution candidates are then associated with these dependencies. Algorithms using the taxonomy and the resolutions are developed to detect and resolve pipeline hazards, and to explore the hardware and software design space. Application benchmarks are used to evaluate the designs and guide the design decision. The power of these tools are demonstrated through the pipeline synthesis of two processors including industrial one. Compared with other approaches, our method achieves higher throughput, and provides a way to explore the hardware/software tradeoff. Our method can be combined with current approaches to achieve even higher performance since they are orthogonal.

Several architectural innovations intended to reduce access latency and improve overall throughput increase system bandwidth requirements. Bandwidth scales with clock speed, and can be regarded as an architectural resource to be applied to latency reduction. A properly designed bus provides low arbitration latency and delivers high sustained bandwidth. The paper evaluates the performance of 3.2 Gbyte/s peak bandwidth, low-latency arbitration bus connecting a GaAs superscalar CPU to a GaAs memory management unit. A microarchitectural performance model was written in the Verilog hardware description language. Bus transactions characteristic of the SPECint92 benchmarks and other workloads were generated as input. Sustained bandwidths of 1.68 Gbytes/s were achieved with arbitration costs of less than 0.5 cycles per data transfer.>