Taping out modern, complex SOCs presents a myriad of challenges in physical design. Doing so for demanding markets such as automotive, industrial, and IoT multiplies that complexity. In this talk we will take a broad look across the physical design space and discuss what works, what doesn't work, and where the major gaps are today and evolving challenges for future devices. We will look at experiences gained over the last 20 years for devices in high volume production and devices in active development across a myriad of technologies including bulk CMOS, low-power nodes, and FinFET.

Historically, Back End of Line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

This paper is in response to the question 'ASIC Design the nm era - dead or alive' from an ASIC library architecture and library flow point of view. The authors believe it is certainly significantly harder to design in the nm era but ASIC design is not dead. ASIC Design is much more challenging in the nanometer era. This paper will present some of the main effects that have become significant in terms of library architecture and library creation flow. Some full chip level effects will be discussed. Example solutions to some of these dramatic trends will also be presented. This is presented in a 'stories from the trenches' format - from the team that architects and delivers TI ASIC libraries. The majority of the data presented comes from development of TI ASIC 130, 90 and 65nm libraries.

Every year, the design and EDA communities are besieged by dire warnings about the impending doom of "design as we know it." Every year, another unpleasant physical effect from the evil depths of deep submicron physics surfaces, compromising our designs in new and vile ways. Every year, the same story: more nanometer woes. Rather than endorse a new winner in this year's race for the next worst thing from the nanometer arena, this panel gathers a set of world-class technology experts to debate what effects are hiding just around the next corner, waiting to pounce on the unwary tool or chip designer. Which among these is really the most important, when will it happen, and why.

Article Free Access Share on Hybrid dual-threshold design techniques for high-performance processors with low-power features Authors: Uming Ko Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Andrew Pua Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Anthony Hill Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Pranjal Srivastava Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 307–311https://doi.org/10.1145/263272.263362Published:01 August 1997Publication History 11citation116DownloadsMetricsTotal Citations11Total Downloads116Last 12 Months10Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper investigates delay, power and area of critical components in designing energy-efficient control logic. To improve performance and energy efficiency, a split-slave dual-path (SSDP) register is proposed which improves the energy efficiency of the prior art by 30%. For multiplexers (MUX) three MUXes are proposed and compared to existing solutions. The proposed MUXes improve performance by 50% or power by 22%. The impact of scaling supply voltage alone and scaling threshold voltage with supply voltage on delay and power is also examined.

Discrete simulation-based methods for switching density estimation can provide very accurate results, but some unresolved problems such as determining the required number of input patterns to guarantee a final accuracy impede the usefulness of this technique. In this paper, we present novel solutions for the following issues in switching density estimation: 1) derivation of simulation stopping criteria based on run-time information, and 2) a priori estimation of the number of input patterns required to guarantee a final specified accuracy. These problems are solved through the definition of a set of multinomial random variables and functions based on the parameters of these random variables. Experimental results indicate that the proposed techniques deliver a reliable stopping criteria as well as accurate a priori estimation of the number of required input patterns.

In combinational logic circuits, a single switching event on the primary inputs may give rise to multiple switchings at the internal nodes. This glitching effect is caused primarily by unequal delay paths and results in increased power consumption and decreased device reliability. In this paper, we present a new algorithm to estimate the maximum number of transitions at internal nodes in combinational CMOS VLSI circuits. Unlike exhaustive simulation, our algorithm is based on the technique of propagating uncertainty waveforms throughout the circuit and using these waveforms to count the maximum switching activity at every node. Our approach guarantees a tight upper bound on the number of transitions which is necessary to assess the minimum circuit reliability lifetime and maximum power dissipation.