Since 2004, Texas Instruments and Portland State University have collaborated to develop and deploy test data analytical methods for use in a variety of applications, including quality screening, burn-in minimization, high cost test replacement and/or removal, and operations monitoring. In this paper, key findings amassed during this time are summarized.

Outlier screening is a popular approach for testing automotive products. In practice, developing an outlier model can be subjective, making justification of the model challenging. In this paper we propose a new concept called Consistency which provides a data-driven objective way to assess an outlier model. We study the development of outlier models in view of this new model consistency concept and report experimental findings on an automotive product line.

In this work, we study the generalization of an outlier model from two perspectives, temporal and spatial. We show that model generalization with existing distribution-based outlier analysis methods can vary significantly. We then propose a “big data” outlier analysis approach together with a probability-based outlier evaluation for improving model generalization. Experiments are conducted based on two automotive product lines to explain the concepts and demonstrate the effectiveness of the proposed approach.

A large end-to-end database was created by joining an IC test factory database with a board contract manufacturer (CM) database using the unique electrical identity fused into the IC and read at IC and CM test steps. A new rank correlation method was used to measure statistical dependencies of IC failure rates in the CM factory on failure rates and attributes measured in the IC factory. IC factory dependency, including radial wafer symmetry, was seen in the CM data providing opportunity to improve CM failure rate at the cost of IC yield. A special kind of receiver operating characteristic (ROC) was constructed to quantify the IC factory yield cost of CM failure rate improvements for hypothetical IC factory screens additional to the screens which generated the database. A screen based on RAM fuse repair count was found to be better than one based on blocking of edge dies.

Variable bit retention time observed in a 65-nm dynamic random access memory (DRAM) case study will cause miscorrelation between retention times occurring in Test and Use. Conventional multivariate normal statistics cannot adequately model this miscorrelation. A more general copula-based modeling approach, widely used in financial and actuarial modeling, solves this problem. The DRAM case study shows by example how to use copula models in test applications. The method includes acquiring data using a test vehicle, fitting the data to a copula-based statistical model, and then using the model to compute producer- and customer-oriented figures of merit of a product, different from the test vehicle. Different array sizes, fault tolerance schemes, test coverage, end-use (datasheet), and test condition specifications of the product are modeled.

This paper introduces an adaptive test method to dynamically control test flow and test contents with continuous per die updates of test fail rates. The method employs Bayesian statistics to model a separate fail rate for each test. Test reordering and elimination is based on statistics of these predicted fail rates and is naturally monitored by a wafer based reset. Wafer sort test response data for two 65nm integrated circuit products is used to demonstrate this method. Test time reductions of about 30% are achieved with quality levels within industry expectations.

This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods are used to calculate the intra-die correlation. When intra-die correlation is found to be low the elevated vectors that lower correlation are extracted and input to IDDQ-based diagnostic tools. Monte-Carlo simulations are described to obtain confidence bounds of the correlation for good die test response.

This work presents a silicon evaluation of testing for small-delay defects using an approach called Longest Path Avoidance testing. The motivation for LPA testing is to improve outgoing product quality by identifying delay defects that escape critical path delay testing. Results from experiments run on high volume production 180nm ASIC are quantified in terms of test escapes and reliability escapes. Techniques for modeling the impact of small- delay testing are discussed.

This is the first of three papers on the statistical analysis of deep-submicron semiconductor test data for the ITC 2005 Lecture Series. The subject of this paper is variance reduction and the importance of variance reduction in outlier screening. Most of the test-data statistical analysis methods discussed are based on the concept of data driven model building. To obtain significant variance reduction, the common approach for these statistical models is to evaluate a die-by-die estimate of the test response, under the assumption that the die of interest is defect-free. Models of the wafer spatial patterns, single parameter and multi-parameter regressions demonstrate the variety and potential of the concept. Within such a framework, it is shown that significant reductions in the variance of parametric distributions can be obtained with a corresponding improvement in outlier detection

This paper is the second of a three paper series on statistical analysis of deep-submicron semiconductor test data. The subjects of this paper are the models and methods for computing healthy die estimates of the test response. Production data are used to demonstrate the ideas in this paper. The conceptual skeleton for the analysis is the computed difference between the measurement and a data-driven model of the healthy response. Uni-variate and multi-variate estimates are used to show the potential of the concept. Within the framework of estimating healthy response it is shown that significant reductions of distribution variance can be obtained with a corresponding improvement in outlier detection

This paper is the third in a lecture series on statistical analysis of semiconductor test data. Statistical test methods offer increased value in IC manufacturing and test over traditional maverick silicon screening methods by optimizing the trade-off between yield and reliability in deep sub-micron CMOS technologies. Effective use of the vast volume of data generated by test can lead to cost-effective screening of subtle defects, burn-in reduction or elimination and test cost reduction through adaptive test

A burn-in reduction screen is presented based on a subset of measurements from the wafer sort data. The subset of wafer sort data is identified by a principal component analysis (PCA) using die passing all the tests. This paper addresses the curse of dimensionality and shows the importance of reducing the dimensions in segregating the potential reliability fails for additional screening from the normal healthy population. The method presented is demonstrated using 90nm volume data and compared to 8 hour burn-in experiments

An I/sub DDQ/ Statistical Post-Processing/spl trade/ (SPP) outlier screen is presented based on the computation of statistically independent sources of variation in the I/sub DDQ/ measurements. I/sub DDQ/ measurements from die passing all other tests are modeled using sources of variation extracted by independent component analysis (ICA). Outliers are separated from the sample population based on residuals computed using these sources and a nearest neighbor spatial signature. An algorithm is presented for applying the proposed technique in production. The screen is demonstrated with 0.18/spl mu/m and 0.11/spl mu/m volume data and shown to effectively identify the outliers at the 0.1 /spl mu/m technology node.

ATE customers realize that testers that keep test data hermetically sealed in production mode are a barrier to profitability. This data is needed for process/yield improvement, adaptive control, product characterization, reliability improvement/burn-in elimination, test floor SPC, calibration, and test repeatability etc. Subcontractor and foundry manufacturing increases the complexity of getting the data. The views on this topic appear to fall into four camps: namely the traditionalist camp, the mainframe camp, the Wintel camp and the red hat camp.

Maintaining product quality at reasonable test cost in very deep sub-micron process has become a major challenge especially due to multiple manufacturing locations with varying defect and parametric distributions. Increasing vector counts and binary search routines are now necessary for subtle defect screening. In addition, parametric tests and at-spec testing is still often necessary to ensure customer quality. Systematic defects are becoming more common and threaten to dominate the yield Pareto. Adaptive test methods are introduced in This work that demonstrate the capability of increasing or decreasing the test coverage based on the predicted or measured defect and parametric behavior of the silicon being tested. Results promise an increase in product quality at the same time a reduction in test costs.

While much progress has been made screening common defects and outliers, less emphasis has been placed on testing for performance outliers and defects across the expected operating temperature range. The subject of this paper is an analysis of the minimum testing required to screen temperature dependent outliers at wafer sort and final test. The analysis is based on data obtained from 20 wafers of a 0.18 /spl mu/m skew lot and at the two temperatures 30/spl deg/C and 85/spl deg/C. The results demonstrate a need for defect screening at multiple temperatures and the advantage of die trace in multiple temperature testing.

This work attempts to improve the common understanding of multiple temperature testing by presenting previously unpublished data as well as deriving a simple model for bounding an IC's performance within the three dimensional space defined by VDD, frequency, and temperature. The model is used to design new temperature screens to improve the resolution between healthy and defective ICs. Temperature based test data is presented for Scan, LBIST, and TDF based MinVDD measurements as well as transistor characteristics needed to parameterize the model. The test vehicles used are 0.25 /spl mu/m and 0.18 /spl mu/m CMOS ASICs fabricated by LSI logic.

Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-Processing™ (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under Test (DUT) and takes two quiescent current measurements. The quiescent current measurements are taken at nominal and at subthreshold supply voltages. The scr een is demonstrated with 0.18µm and 0.13µm volume data. The screen's effectiveness is compared to stuck -at and other IDDQ screens.

In sub-micron processes, resistive path defects are increasingly contributing to the yield loss and the customer fail pareto. Data has been collected on a series of ASIC products and it has been used to compare the effectiveness of full vector set transition delay fault tests with reduced vector sets, minVDD, customer functional tests and customers system fails. Results show that fault models do not predict the defect coverage well and cost effective screening of frequency outliers and minVDD outliers is possible and is critical in improving customer quality.

The subject of this paper is variance reduction and nearest neighbor residual estimates for I/sub DDQ/ and other continuous-valued test measurements. The key, new concept introduced is data-driven neighborhood identification about a die to reduce the variance of good and faulty I/sub DDQ/ distributions. Using LSI Logic production data, neighborhood selection techniques are demonstrated. The main contribution of the paper is variance reduction by the systematic use of the die location and wafer- or lot-level patterns and improved identification of die outliers of continuous-valued test data such as I/sub DDQ/.

MinVDD testing using full vector set search routines consumes too much test time. A 3-step process is proposed using: (1) a reduced vector set (RVS) binary search to measure the intrinsic (defect free) minVDD for a die; (2) a feed-forward to the full vector set (FVS) for low voltage testing; and (3) delta VDD and nearest neighbor residual statistical post-processing (SPP) are applied to the data to screen the minVDD outliers that are identified using the RVS binary search. RVS vs. FVS correlation data is shown on 3 products. Data shows minVDD yield fallout of 0.2-0.8% and 20% of the minVDD outliers shows significant VDD shifts in burn-in.

We describe new methods of data analysis that identify and isolate sources of variation in production test data based on its natural taxonomy. We also describe an alternative approach to data analysis that integrates disparate data by removing each primary source of variation. This new approach has several advantages compared to traditional "divide and conquer" techniques (e.g. ANOVA). For example, the new approach enables us to identify secondary sources of variation that are normally obscured by the primary source. The methods are demonstrated on a die-speed measurement collected from seventy lots of two products produced at two fabrication facilities.

In sub-micron CMOS processes, it has become increasingly difficult to identify and separate outliers from the intrinsic distribution at test. This is due to the increasing inadequacy of reliability screens such as burn-in and IDDQ testing. Statistical Post-Processing (SPP) methods have been developed to run off-tester using the raw data generated from Automatic Test Equipment (ATE) and wafersort maps. Post-Processing modules include advanced IDDQ tests such as Delta IDDQ and the Nearest Neighbor Residual (NNR), as well as other non-IDDQ based reliability-focused modules. This work presents the application and results of SPP at LSI Logic on 0.18 /spl mu/m CMOS products. Challenges of production implementation have been overcome, which include "user definable" adaptive threshold limits, handling multiple data sources, and data flow management. Burn-in data and customer Defects per Million units (DPM) data show a 30-60% decrease in failure rate with SPP implementation with very acceptable yield loss.

The subject of this paper is variance reduction and nearest neighbor residual estimates for I/sub DDQ/ and other continuous-valued test measurements. The key, new concept introduced is data-driven neighborhood identification about a die to reduce the variance of good and faulty I/sub DDQ/ distributions. Using LSI Logic production data, neighborhood selection techniques are demonstrated. The main contribution of the paper is variance reduction by the systematic use of the die location and wafer- or lot-level patterns and improved identification of die outliers of continuous-valued test data such as I/sub DDQ/.

The subject of this paper is I/sub ddQ/ testing for deep sub-micron CMOS technologies. The key concept introduced is the need to reduce the variance of good and faulty I/sub ddQ/ distributions. Other I/sub ddQ/ based techniques are reviewed within the context of variance reduction. Using the SEMATECH data and production data, variance reduction techniques are demonstrated. The main contribution of the paper is the systematic use of the die location and patterns in the I/sub ddQ/ data to reduce variance. Variance reduction is completed before any I/sub ddQ/ threshold limits are set.