Energy-harvesting (EH) Internet of Things (IoT) devices operate under intermittent energy availability, which disrupts task execution and makes energy-intensive over-the-air (OTA) updates particularly challenging. Conventional OTA update mechanisms rely on reboots and incur significant overhead, rendering them unsuitable for intermittently powered systems. Recent live OTA update techniques reduce reboot overhead but still lack mechanisms to ensure consistency when updates interact with runtime execution. This paper presents AERO, an Adaptive and Efficient Runtime-Aware OTA update mechanism that integrates update tasks into the device’s Directed Acyclic Graph (DAG) and schedules them alongside routine tasks under energy and timing constraints. By identifying update-affected execution regions and dynamically adjusting dependencies, AERO ensures consistent update integration while adapting to intermittent energy availability. Experiments on representative workloads demonstrate improved update reliability and efficiency compared to existing live update approaches.

This paper proposes a new technique, fast waveform estimation (FWE), to quickly and accurately estimate the output waveform for general resistance-capacitance (RC) interconnect networks in the presence of coupling noise. It is a common view that the traditional transient analysis is not feasible for full-chip timing analysis. The static methods suffer from inaccuracy and inability to capture the non-monotonic nature of signal waveform in the presence of coupling noise. The dynamic methods, such as, general model order reduction techniques provide a good compromise between the accuracy and efficiency. But they make no use of the typical topological structures of the general RC interconnect networks. The proposed FWE technique achieves a better overall performance through topological reduction of the general RC interconnect networks. It is demonstrated that the accuracy of the proposed method is comparable to the general model order reduction-based methods while maintaining an efficiency that is comparable to Elmore delay based analysis.

This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is more prominent for lines with strong capacitive coupling. A performance comparison is done between power supply and ground line as inductive shield, and it is found that ground lines work better than power lines in inductive crosstalk minimization. The 100%-delay measurement technique has been proposed as opposed to the conventional 50%-delay method, and we notice that the 50%-delay technique underestimates the propagation delay for an inductive dominant line with varying signal slew times. Closed-form equations for propagation delay in terms of signal slew time have been derived, which are within 9% of HSPICE-simulated results for a set of interconnect structures. These expressions are simple, and accuracy increases with growing number of interconnect lines.

With the technology scaling and shrinking feature sizes, coupling noise has become one of the most critical concerns in today's interconnect-centric design, especially for long global buses. A very common consequence of coupling is that the output signal waveform becomes non-monotonic. Traditionally, only through circuit simulation can the output waveform can be precisely acquired. However, this method suffers from low efficiency especially for today's super scale circuits. This paper proposes a fast algorithm to accurately estimate the output waveform for buses at the presence of coupling noise. Experimental results show that only a little more than 2% mean error is induced while, on average, the running time of the proposed algorithm is 23 times faster than HSPICE simulation.

It is very natural that the signal waveform becomes non-monotonic at the presence of coupling noise. Therefore, the signal delay can only be precisely predicted through using full waveform accuracy. This paper proposes an efficient algorithm to accurately estimate the delay time of global interconnects driven by gates through estimating the output waveform. Experimental results show that only a little more than 5% mean error is induced while, on average, the running time of the proposed algorithm is more than 370 times faster than HSPICE simulation.

The design targets of an interconnect are to ensure less delay cycles, high reliability and low power consumption at the same time. This paper presents an in-depth analysis of the dependencies of the reliability (in terms of bit error rate (BER)) and the power consumption of wire pipelining scheme on the number of inserted flip-flops and the size of repeaters. To trade off the design targets, a methodology is developed to optimize the repeater size and the number of flip-flops inserted, which maximizes a user-specified figure of merit. This methodology is demonstrated by calculating the optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.

This paper presents an in-depth analysis of power consumption in flip-flop based wire pipelining. A comparison for the power consumed by the repeaters and the inserted flip-flops are given for different technology nodes, and it has been observed that the power consumed by the repeaters is much higher than the power consumed by the flip-flops. A relationship between the number of inserted flip-flops and repeater size with the power consumption is demonstrated in this paper. Here it has also been illustrated that there is a lower bound for the power consumed by a certain interconnect pipelining scheme, since number of flip-flops and repeater sizes can not lowered beyond certain limit due to the solidity requirement, which is determined by maximum allowable bit error rate.