The ability to predict area-delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time. A mathematical model for predicting the area-delay tradeoff curve for pipelined and nonpipelined data paths, given a data flow graph and a choice of module styles, is proposed. The model has been validated against designs generated by pipelined and nonpipelined data-path synthesis programs.>

The authors present an approach for automatically synthesizing a time-stationary control scheme for a given pipelined data path. They have developed an efficient method of producing a control specification for the data path. A highly optimized FSM (finite state machine) controller implementation is obtained by partitioning so as to minimize the total controller area. The FSM controller is implemented using either PLAs or standard cells. The present approach has been compared to published work on FSM generation and optimization, and the results indicate large savings in total controller area.>

The authors present a novel approach to the problem of register-transfer (RT) design optimization of pipelined data paths. They perform module assignment with the goal of maximizing the interconnect sharing between RT-level components. The interconnect sharing task is modeled as a constrained clique partitioning problem. They have developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30-50 times faster than other existing heuristics while still producing better results for the authors' purposes.>

The effect of clocking schemes on overlapped execution performance in a digital system is described and quantified. Effects of branching, data dependencies, and resource conflicts between consecutive tasks are considered. Some problems of clocking scheme synthesis for the design of digital systems with maximum execution overlap are examined. Effects of performance of the choice of clocking scheme, partitioning of functions into the time steps, the number of clock phases, the length of each phase (i.e., how to pipeline), and the assignment of functions to clock phases are treated.>

A set of techniques for the synthesis of pipelined data paths is described, and Sehwa, a program that performs such synthesis, is presented. The task includes the generation of data paths from a data-flow graph along with a clocking scheme that overlaps execution of multiple tasks. Some design examples are given. Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space. Sehwa is written in Franz Lisp and executes within minutes, for problems of practical size, on a VAX 11/750.>

In this paper we give a model for predicting the shape of cost-speed tradeoff curves for pipelined designs. The model includes prediction of the number of operators, registers and multiplexers from a behavioral specification. It has been verified with the designs generated by an automated pipeline synthesis program, Sehwa. This model was developed as a part of the ADAM Advanced Design Automation System of the University of Southern California.

This paper describes a set of techniques for the synthesis of pipelined data paths, and presents Sehwa, a program which performs such synthesis. The task includes the generation of data paths from a data flow graph along with a clocking scheme which overlaps execution of multiple tasks. Some examples which Sehwa has designed are given. Sehwa can find the minimum cost design, the highest performance design, and other designs between these two in the design space. We believe Sehwa to be the first pipelined synthesis program published in the open literature. Sehwa is written in Franz LISP, and executes within minutes for problems of practical size on a VAX 11/750.

Clocking scheme synthesis includes the partitioning of functions into time steps, the number of clock phases, the length of each phase, (i.e. how to pipeline) and the assignment of functions to clock phases; each of these choices affects performance. Some important problems of clocking scheme synthesis are examined. Two efficient and powerful algorithms which synthesize near optimal clocking schemes have been programmed. These algorithms are applied to synthesis and/or performance evaluation of a design in progress. Optimizing the speed of a previously designed system is also considered.