Large language models (LLMs) have revolutionized AI applications, yet their enormous computational demands severely limit deployment and real-time performance. Quantization methods can help reduce computational costs, however, attaining the extreme efficiency associated with ultra-low-bit quantized LLMs at arbitrary precision presents challenges on GPUs. This is primarily due to the limited support for GPU Tensor Cores, inefficient memory management, and inflexible kernel optimizations. To tackle these challenges, we propose a comprehensive acceleration scheme for arbitrary precision LLMs, namely APT-LLM. Firstly, we introduce a novel data format, bipolar-INT, which allows for efficient and lossless conversion with signed INT, while also being more conducive to parallel computation. We also develop a matrix multiplication (MatMul) method allowing for arbitrary precision by dismantling and reassembling matrices at the bit level. This method provides flexible precision and optimizes the utilization of GPU Tensor Cores. In addition, we propose a memory management system focused on data recovery, which strategically employs fast shared memory to substantially increase kernel execution speed and reduce memory access latency. Finally, we develop a kernel mapping method that dynamically selects the optimal configurable hyperparameters of kernels for varying matrix sizes, enabling optimal performance across different LLM architectures and precision settings. In LLM inference, APT-LLM achieves up to a 3.99× speedup compared to FP16 baselines and a 2.16× speedup over NVIDIA CUTLASS INT4 acceleration on RTX 3090. On RTX 4090 and H800, APT-LLM achieves up to 2.44× speedup over FP16 and 1.65× speedup over CUTLASS integer baselines.

The exponential growth of data volume puts significant pressure on the throughput and CPU resource usage of conventional software-based compression systems, driving the research focus of LZ4 algorithm towards its parallel hardware implementations. However, existing parallel architectures have to make a trade-off between throughput and compression ratio. To address the challenge, this paper presents a novel segment-parallel architecture that simultaneously delivers both high throughput and good compression ratio. The proposed architecture first introduces an interconnected dictionary scheme to preserve compression ratio while enabling parallel processing, limiting compression ratio degradation to less than 8% compared with software benchmarks across various parallelization levels. Second, a priority-based arbitration mechanism for data memory and a hierarchical depth scheduling strategy for hash table are proposed to enhance memory efficiency of multi-port memories. Additionally, the bit-width of hash table entries is reduced by exploiting deterministic address mapping relationships between hash values and input strings. Implemented on FPGA platforms, the proposed architecture achieves a state-of-the-art performance of 17.71 Gbps throughput, matching the performance of our previous work while delivering a$2.91\sim 3.85\times $improvement over other designs. It also demonstrates superior memory efficiency exceeding existing parallel implementations by$1.57\sim 5.57\times $.

Polar-coded massive multiple-input multiple-output (MIMO) systems have attracted significant attention in wireless communications due to their superior performance with iterative detection and decoding (IDD). However, the practical implementation of polar-coded IDD receivers faces two critical challenges: the high computational complexity of massive MIMO detection and the difficulty in pursuing low-complexity and high-performance soft-output polar decoding. In this paper, we propose a comprehensive system design to address both challenges. For detection, we propose a vectorized Gauss-Seidel (VGS) detector supporting soft-input and soft-output (SISO) operations, achieving$2\times $higher hardware efficiency than existing works when implemented on FPGA. For decoding, we develop a partial-sum-based soft-output successive cancellation list (PS-SSCL) decoder that generates soft outputs without additional decoding procedures. Compared to state-of-the-art soft-output list (SOL) decoders, the PS-SSCL reduces memory usage by 55% and computational complexity by 62% while providing an extra 0.3 dB gain in IDD systems. Finally, an interleaved IDD receiver integrating the SISO VGS detector and PS-SSCL decoder is coded with RTL and synthesized under TSMC 28-nm CMOS technology, achieving an extra coding gain of 1.5 dB at FER$= 10^{-3}$over conventional separate detection and decoding (SDD) receiver with only 5% sacrifice in area efficiency.

The Inverted File with Product Quantization (IVF-PQ) is a widely used method for Approximate Nearest Neighbor Search (ANNS), playing a critical role in AI-driven applications such as search engines, recommendation systems, and advertising platforms. With the advent of Large Language Models (LLMs), the demand for efficient and real-time index construction has significantly increased, especially for edge-side personal applications. In this paper, we propose a scalable and high-speed FPGA implementation of IVF-PQ index construction, significantly reducing indexing latency and making it feasible for edge scenarios. First, we optimize the original index construction algorithm by introducing batch-mode centroid updates and replacing floating-point division with hardware-efficient operations, while maintaining competitive recall performance (with less than 5% degradation and up to 12.5% improvement compared to the original algorithm). Next, based on the modified algorithm, we design a flexible and scalable hardware architecture that supports two distance metrics (L2 and Inner Product), six PQ configurations, and input data with up to 1024 dimensions, all without necessitating hardware recompilation. Our implementation maximizes computational efficiency through finely tuned parallelism and dataflow, ensuring full pipeline utilization. Finally, we implement our design in Verilog and evaluate it on the Xilinx XCU280-FSVH2892-2L-E FPGA platform. Experimental results show that our accelerator achieves up to$30\times $speedup over a high-end server CPU (Intel Xeon Gold 6248R), reducing the indexing time from hours to minutes.

The Mamba model, based on state space models (SSM), excels at long-sequence modeling with linear complexity, surpassing Transformers and emerging as a strong LLM candidate. However, various low-arithmetic-intensity operations in Mamba, along with the complex computational dependencies of the SSM, result in low efficiency on general-purpose computing platforms. Therefore, this paper introduces S$\rm ^{2}$Mamba, an efficient Mamba accelerator that leverages the sparsity of SSM. First, we develop a Mamba processing core (MPC) for low-arithmetic-intensity linear operations. By combining the linear-conv layer fusion scheme, the MPC facilitates fast depthwise convolution (DWC) computation, while continuous element-wise (EW) operations are designed to achieve efficient SSM computation. Second, we propose a word importance sparsity (WIS) algorithm that takes advantage of redundancy in natural language to filter 40.20% of unimportant words, leading to an average 37.25% reduction in the SSM computation. The saved computation is accelerated dynamically by the Dynamic Series Modules. Finally, we introduce a reconfigurable SiLU/Softplus unit (RSSU) for performing low-arithmetic-intensity nonlinear operations. The accelerator is implemented using a 28 nm CMOS process with an area of 17.56 mm$\rm ^{2}$. Extensive evaluations on representative benchmark tasks show that, S$\rm ^{2}$Mamba delivers 35.48–$97.11\times $speedup and 147.72–$332.47\times $energy efficiency gains over GPUs, while outperforming state-of-the-art Mamba accelerators with 1.52–$25.67\times $speedup and 1.10–$25.25\times $energy savings.

To address performance degradation from the domain shift and to support user-specific services while considering privacy, security, and communication overhead, there is an urgent need for efficient on-device training accelerators for deep neural networks (DNNs). Given limited computing resources and battery capacity constraints, implementing complex DNN training on edge devices is extremely challenging. To address these issues, we introduce a Winograd-Integrated Gradient Optimization Framework (WIGOF) for cross-phase operand sharing in the Winograd domain, which significantly reduces the number of multiplications and additions. Additionally, we develop WiFlow, an efficient, precision-scalable on-device training accelerator, minimizing area and power overheads of the dedicated Winograd transformation unit. The WiFlow supports 16-bit floating point (FP16), 16-bit brain floating point (BF16), and 8 and 4-bit fixed point (INT8 and INT4), demonstrating scalable improvements in both computational throughput (TOPS) and energy efficiency (TOPS/W) at low precision. A novel data rearrangement pattern, named channel augmentation, addresses the imperfect decomposition to enhance the utilization of processing element units. Furthermore, we propose a Winograd interleaved block-execution dataflow (WInBlock), along with Hierarchical Adaptive Reuse Memory Optimization (HARM) to improve data reuse and reduce both the amount of DRAM and SRAM access. The end-to-end training of WiFlow is achieved on Xilinx XCVU440 FPGA. WiFlow is also synthesized with a 28nm CMOS technology, achieving an area efficiency of 624 GOPS/mm2and an energy efficiency of 4.4 TOPS/W at a supply voltage of 0.9V and an operating frequency of 500 MHz. WiFlow accomplishes$7.75\times $higher area efficiency and$2.91\times $higher energy efficiency in actual DNN training compared with the state-of-the-art on-device training accelerators.

Recent advancements in multimodal large language models (MLLMs) have boosted hardware design driven by artificial intelligence (AI), yet a critical gap persists in circuit-diagram-to-Verilog (CD2V) generation—essential for translating structural intent into code. For complex, performance-critical modules, current MLLMs struggle to perform CD2V due to the lack of multimodal datasets that capture hierarchical architectures and hardware optimization techniques (HOTs). General matrix multiplication (GEMM), the computational backbone of AI accelerators that dominates workload and power consumption while demanding deep design expertise, serves as an ideal benchmark for validating CD2V solutions. In this work, we propose MGEMMV, an open-source multimodal framework tailored for GEMM CD2V. It constructs a hierarchical dataset covering basic logic and HOT-enhanced GEMM variants, an automated CD2V pair generation workflow, and a standardized evaluation framework. Experiments show our fine-tuned MLLMs achieve 94.6% syntax and 90.8% functionality correctness, 20.8% and 63.9% higher than the strongest baseline. To our knowledge, MGEMMV is the first GEMM-dedicated CD2V framework, filling a key gap in AI-driven hardware design.

Analog compute-in-memory (ACIM) architectures offer significant throughput and energy benefits by performing multiplication-and-accumulation (MAC) operations directly within memory arrays. However, their overall efficiency is fundamentally constrained by the high power consumption of the per-column high-resolution analog-to-digital converters (ADCs) required to support modern DNNs (e.g., transformers), many of which demand both high computational precision and large-column throughput. In conventional ADC designs, energy in the noise-limited regime scales near-exponentially, typically by$4\times $per additional bit, making high-resolution ADCs on every column power-prohibitive. This article proposes a high-precision and power-efficient multicolumn residue accumulation (MCRA) ACIM architecture to efficiently support precision-demanding modern DNNs. Each column uses a low-resolution coarse ADC (cADC), while the per-column residuals are accumulated and further quantized by an energy-efficient time-domain multi-input incremental sigma–delta (Mi-$\Sigma \Delta $) fine ADC (fADC). This approach amortizes the near-exponential energy growth across columns, while exploiting the more favorable power-resolution scaling of the time-domain Mi-$\Sigma \Delta $quantization. Postlayout simulations demonstrate a 66.2-dB signal-to-noise-and-distortion ratio (SNDR) per column at only 1/21 the energy of the baseline with per-column high-resolution ADCs, and$0.405\times $(1/2.47) the energy of an energy-saving ADC per column, which achieves a similar SNDR. Circuit- and system-level simulations demonstrate that our MCRA CIM architecture achieves negligible accuracy degradation in precision-demanding ViT tasks while delivering high energy and area efficiency.

The computation-intensive modular multiplications in number theoretic transform (NTT) present significant bottlenecks for lattice-based post-quantum cryptography (PQC). In this article, we propose a systematic area optimization strategy through joint algorithm-hardware codesign. First, we propose two high-throughput architectures to accommodate diverse throughput requirements: a fully parallel NTT and a folded 64-point variant derived from the former, which both feature area-efficient constant modular multipliers. A novel permutation-based algorithm is developed to reuse the NTT architecture for inverse NTT without structural modifications. Second, an area-driven, automated decomposition-based design strategy for constant modular multipliers is developed to reduce hardware overhead. The strategy involves a three-stage process: decomposing, analyzing, and selecting, which are based on finite-field properties and comprehensive circuit modeling. Finally, the proposed architectures are evaluated on Artix-7 AC701 FPGA with the parameters of the module-lattice-Based key-encapsulation mechanism (ML-KEM) from the latest PQC standard. The results show that the optimized modular multipliers deliver an average resource reduction of approximately 46% over the prior art. Furthermore, operating at 189 MHz, the core throughputs reach 47.2 and$94.5\times 10^{6}$operations per second (OPS) for the proposed folded and fully parallel structures, respectively, while both architectures achieve an I/O-limited throughput of$23.6{\,}\times{\,}10^{6}$OPS. Compared to the state-of-the-art highly parallel designs, our work provides a 31.1% area efficiency improvement.

Reed–Solomon (RS) codes are widely used in modern communication and storage systems. However, conventional iteration-based RS decoder architectures are struggling to meet the stringent demands of emerging latency-critical applications. Although noniterative architectures have been proposed for$t \leq 4$RS codes with low latency and low complexity, the design of such architectures remains largely unexplored for five-error-correcting RS codes. Motivated by this gap, we extend the Peterson–Gorenstein–Zierler (PGZ) algorithm to directly compute the error locator polynomial for$t=5$RS codes, thereby eliminating the need for iterative computation in the circuit. Then, a systematic three-step optimization method is further proposed to mitigate the hardware complexity increase caused by PGZ, which significantly decreases the required number of multipliers. Besides, given the prohibitive complexity of noniterative root-finding algorithms for$t = 5$RS codes, we instead adopt a hybrid PGZ-Chien search (PGZ-CS) architecture for the whole decoder. Based on the proposed methods, a low-latency and area-efficient$t=5$RS decoder is finally developed and implemented under the example RS(255, 245, and 5)code. Synthesized under 28-nm CMOS technology, the proposed decoder reduces decoding latency by 65.6%, overall area by 29.7%, and power consumption by 32.6% compared to the compensated simplified reformulated inversionless Berlekamp–Massey (CS-RiBM) decoder.

Placement is an important part in the flow of physical design, which can affect the performance of a circuit significantly. Many algorithms have been proposed to refine the placement in the past years and Mixed Integer Programming (MIP) is one of the directions that can further improve the placement quality, since MIP is able to perform a finer-grained placement with precise MIP formulations. Many previous MIP works try to prune the search space for efficiency, but the strategies for selecting valuable search space do not contain enough analysis of the initial placement before refinement. In this work, we propose an MIP-based algorithm that can refine large scale placement by considering more global factors from initial placement, while achieving the trade-off between efficiency and quality. A force-directed displacement technique is proposed, which quantifies multiple metrics in each orientation to assign a potential region for each cell's movement. Meanwhile, we also propose an accurate wirelength prediction method for high-degree nets by introducing the concept of centroid for net breaking. Experiments on benchmarks of ISPD18 and ISPD19 show that our algorithm is able to reduce the wirelength and vias by 1.02% and 0.58% on average and our work outperforms the state-of-the-art related work in wirelength optimization under both its comprehensive mode and wirelength-only mode.

Large language models (LLMs) have been widely applied but face challenges in efficient inference. While quantization methods reduce computational demands, ultra-low bit quantization with arbitrary precision is hindered by limited GPU Tensor Core support and inefficient memory management, leading to suboptimal acceleration. To address these challenges, we propose a comprehensive acceleration scheme for arbitrary precision LLMs. At its core, we introduce a novel bipolar-INT data format that facilitates parallel computing and supports symmetric quantization, effectively reducing data redundancy. Building on this, we implement an arbitrary precision matrix multiplication scheme that decomposes and recovers matrices at the bit level, enabling flexible precision while maximizing GPU Tensor Core utilization. Furthermore, we develop an efficient matrix preprocessing method that optimizes data layout for subsequent computations. Finally, we design a data recovery-oriented memory management system that strategically utilizes fast shared memory, significantly enhancing kernel execution speed and minimizing memory access latency. Experimental results demonstrate our approach's effectiveness, with up to 2.4× speedup in matrix multiplication compared to NVIDIA's CUTLASS. When integrated into LLMs, we achieve up to 6.7× inference acceleration. These improvements significantly enhance LLM inference efficiency, enabling broader and more responsive applications of LLMs.

Deformable attention (DA) provides an efficient and adaptive solution for capturing diverse object shapes, reducing computational complexity across multiple vision tasks. However, the various DA types lead to flexible matrix computation dimensions and complex attention pipelines. Moreover, the sampling operator's dynamic and irregular memory access significantly reduces data reuse and processing elements (PE) utilization, hindering DA from fully leveraging its low computational complexity. In this paper, we propose UEDA, a universal and efficient accelerator for DA. Specifically, a flexible 3D Folded Dimension Systolic Array (FDSA) is designed for efficient matrix multiplication computations with various dimensions, while achieving consistent high efficiency in supporting multiple networks. Secondly, a Reorganized Feature Map (RFM) sampling strategy is proposed to address parallel memory access conflicts, boosting the sampling module's processing rate by up to 4 times. Finally, an Inter-tile Cross Parallel (ITCP) dataflow is proposed to further hide the sampling module's latency, enhancing circuit throughput. The proposed UEDA is implemented on a Xilinx UltraScale+ FPGA. Experimental results show that UEDA achieves 11.7--14.8× speedup and 17.8--29.1x energy efficiency compared with GPU. Furthermore, we observe up to 2.19× better speedup and 27.8× higher energy efficiency compared to prior FPGA accelerators.

Advancements in AI have increased the demand for specialized AI accelerators, with design for general matrix multiplication (GEMM) module being crucial but time-consuming. While large language models (LLMs) show promise for automating GEMM design, challenges arise from GEMM's vast design space and performance requirements. Existing LLM-based frameworks for RTL code generation often lack flexibility and performance awareness. To overcome the challenges, we propose LLM4GV, a multi-agent LLM-based framework that integrates hardware optimization techniques (HOTs) and performance modeling, improving correctness and performance of the generated code over prior works.

The widely-used, weight-only quantized large language models (LLMs), which leverage low-bit integer (INT) weights and retain floating-point (FP) activations, reduce storage requirements while maintaining accuracy. However, this shifts the energy and latency bottlenecks towards the FP activations that are associated with costly memory accesses and computations. Existing LLM accelerators focus primarily on computation optimizations, overlooking the potential of jointly optimizing FP computations and data movement, particularly for the dominant FP-INT GeMM operations in LLM inference. To address these challenges, we investigate the sensitivity of activation precision across various LLM modules and its impact on overall model accuracy. Based on our findings, we first propose the Anda data type: an adaptive data format with group-shared exponent bits and dynamic mantissa bit allocation. Secondly, we develop an iterative post-training adaptive precision search algorithm that optimizes the bit-width for different LLM modules to balance model accuracy, energy efficiency, and inference speed. Lastly, a suite of hardware optimization techniques is proposed to maximally exploit the benefits of the Anda format. These include a bit-plane-based data organization scheme, Anda-enhanced processing units with bit-serial computation, and a runtime bit-plane Anda compressor to simultaneously optimize storage, computation, and memory footprints. Our evaluations on FP-INT GeMM operations show that Anda achieves a $2.4 \times$ speedup, $4.0 \times$ area efficiency, and $3.1 \times$ energy efficiency improvement on average for popular LLMs including OPT, LLaMA, and LLaMA-2 series over the GPU-like FP-FP baseline. Anda demonstrates strong adaptability across various application scenarios, accuracy requirements, and system performance, enabling efficient LLM inference across a wide range of deployment scenarios.

Fine-tuning large language models (LLMs) is difficult due to their huge model size. Recent Fourier domain-based methods show potential for reducing fine-tuning costs. We propose a block circulant matrix-based fine-tuning method with a stable training heuristic to leverage the properties of circulant matrices and one-dimensional Fourier transforms to reduce storage and computation costs. Experiments show that our method uses 14× less number of parameters than VeRA, 16× smaller than LoRA and 32× less FLOPs than FourierFT, while maintaining close or better task performance. Our approach presents a promising way in frequency domain to fine-tune large models on downstream tasks.

Mamba has exhibited great potential across various tasks, achieving the powerful capability of long-sequence modeling with linear complexity. Selective State Space Models (SSMs), the core component of Mamba, possess unique computational flow and massive memory requirements, which pose new challenges for deployment on edge devices and are difficult to be efficiently supported by existing deep learning accelerators. Therefore, we develop the first memory-efficient Selective SSM Accelerator, namely SSMA. Specifically, we design a reconfigurable hardware architecture and low-complexity nonlinear units to efficiently execute the rearranged and fused operations in Selective SSM. Moreover, we introduce a novel tile-stationary recurrent dataflow to achieve on-chip layer fusion by recurrently updating the tiled latent state and SSM parameters, dramatically decreasing memory usage and access. Experimental results show that the proposed SSMA, evaluated on Xilinx ZCU102 FPGA, achieves up to 3.33× speedup and 41.8 × higher energy efficiency than the optimized GPU implementation with the same setting.

This paper presents a high-speed 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) featuring tailored bit intervals (TBI). The design employs built-in SAR logic to set delays autonomously, eliminating the need for digital assistance, and thereby reducing both power and area consumption. This approach also effectively shortens the waiting time before lower-bit comparisons, enabling faster conversions. The ADC is simulated in the 16 nm process, occupying only 0.0012 mm2, with post-simulation conducted under various extreme process and temperature conditions. Compared to prior works, our design exhibits notable performance advantages, achieving an ENOB of 7.38 bits at TT 25°C with a power consumption of 6.94 mW. Furthermore, the designed TBI-ADC attains a sampling rate of 1.6 GS/s at FF -40°C, representing a 33% increase over the fastest previously reported single-channel, 1b/cycle, 8-bit SAR ADC.

Fine-tuning large diffusion models for custom applications demands substantial power and time, which poses significant challenges for efficient implementation on mobile devices. In this paper, we develop a novel training accelerator specifically for Low-Rank Adaptation (LoRA) of diffusion models, aiming to streamline the process and reduce computational complexity. By leveraging a fully quantized training scheme for LoRA fine-tuning, we achieve substantial reductions in memory usage and power consumption while maintaining high model fidelity. The proposed accelerator features flexible dataflow, enabling high utilization for irregular and variable tensor shapes during the LoRA process. Experimental results show up to 1.81× training speedup and 5.50× energy efficiency improvements compared to the baseline, with minimal impact on image generation quality.

Transformers have achieved significant success in modern deep learning. However, their intensive and complicated computations challenge Transformers’ deployment on resource-constrained devices, especially the training process. Softmax, the crucial nonlinear function in Transformers, features complex exponential and division operations. Unfortunately, existing methods cannot effectively reduce the hardware complexity of Softmax while maintaining training accuracy. In this paper, we propose an efficient architecture for Softmax training. Specifically, we present a quantized Softmax training algorithm based on integer arithmetic with sufficient training accuracy. Additionally, we design a reconfigurable architecture to efficiently support various operations during different training phases, along with a staged parallel and pipelined (SPAP) dataflow to reduce latency and improve hardware efficiency. Experimental results show that our architecture achieves up to 1.0 Softmax GinS in throughput and 4.42 GinS/W in energy efficiency at 500MHz on the Xilinx ZCU102 FPGA, which significantly outperforms prior works.

Fast Fourier Transforms (FFT) are widely used to reduce memory and computational costs in deep learning. However, existing implementations, including standard FFT and real FFT (rFFT), cannot achieve true in-place computation. In particular, rFFT maps an input of size $n$ to a complex output of size $\frac{n}{2}+1$, causing dimensional mismatch and requiring additional memory allocation. We propose the first real-domain, fully in-place FFT framework (rdFFT) that preserves input-output dimensional consistency ($n \rightarrow n$). By leveraging butterfly operation symmetry and conjugate properties in the frequency domain, we design an implicit complex encoding scheme that eliminates intermediate cache usage entirely. Theoretically, our method reduces memory usage by 50\% compared to rFFTs. Moreover, it enables zero-cache parameter updates by utilizing the derivative property of the Fourier transform to compute matrix inverses efficiently without intermediate storage. Experiments on multiple natural language understanding tasks demonstrate the method’s effectiveness in maintaining model performance while significantly lowering memory overhead, offering a promising direction for frequency-domain lightweight adaptation.

In recent years, SGX-style integrity trees (SITs) have been applied in trusted execution environments (TEEs) to protect the off-chip memory security from physical attacks, replay attacks, etc. As a tradeoff, SIT implementations incur a huge performance overhead due to its extra computations and memory accesses. Recent works reduced the memory accesses and significantly increased the speed, but the performance overhead is still high. To tackle this challenge, this article performs an insight analysis under current SIT implementations, then identifies two critical remaining performance overhead causes: 1) hash and 2) decryption computations. Next, a novel design named PreSIT based on a proposed parallel operation flow is introduced. It performs prefetching and precomputes partial results of hash and decryption processes. By designing the prediction algorithm flow and predict-assisted algorithms, along with the proposed dedicated prediction data structure to effectively store and access the precomputed results, the performance overhead is further reduced. According to the evaluations of GEM5 on SPEC 2017, GAP, PARSEC, and SPLASH2x, PreSIT improves the average instruction per cycle (IPC) by 5.1% (at most 21.6%) based on the SIT in VAULT without any security degradation.

The Lempel-Ziv (LZ) 4 compression algorithm, widely used in data transmission and storage, faces the challenge of high-speed implementation and increased complexity in the era of big data. Therefore, this paper proposes a single-core parallel architecture for LZ4 algorithm with high throughput and low complexity. Firstly, to enhance throughput, two innovative approaches are introduced from the perspective of parallelism and frequency with an acceptable compression ratio loss: each parallelization window is restricted to performing a single match, bridging the gap between actual and theoretical parallelism; the feedback loop in the circuit is broken by utilizing the spatial correlation between adjacent matches for higher frequency. Secondly, two optimization schemes are employed on resource-consuming modules to achieve low complexity. Multi-port hash tables using Live Value Table (LVT) are improved based on inherent data characteristics, significantly reducing the hardware resource consumption while ensuring excellent scalability on hash table depth and frequency. The match comparison operation is moved ahead, further reducing the logic resources by 64.36%. Finally, our design is implemented on FPGA and ASIC platforms. Experimental results on FPGA demonstrate that the proposed architecture achieves a throughput of 17.39 Gb/s, exhibiting a 2.86$\times $improvement over the state-of-the-art, along with a 6.46$\times $enhancement in area efficiency. Further optimizations including Canonic Signed Digit (CSD) coding and computational reuse on the ASIC platform result in a$45\times $improvement in area efficiency.

Pruning has emerged as an effective technique for compressing convolutional neural networks (CNNs) by eliminating redundant weights, achieving lightweight models with negligible loss in inference accuracy. To leverage the sparsity for acceleration, many accelerators built for sparse CNNs have been developed. Existing hardware accelerators can perform well with structured or customized sparsity patterns. However, when facing the unstructured sparsity which can achieve higher compression rates, the corresponding hardware always suffers from insufficient utilization of computational resources, severe load balance between process elements, and significant overhead in logic resources, which results in a reduction of throughput, making it difficult to leverage high ratio sparsity for acceleration effectively. An efficient CNN inference accelerator that can handle both structured and unstructured sparse networks is proposed to address these issues. By flexibly employing multiple parallel computation methods combined with carefully developed sorting algorithms, the proposed architecture mitigates the hardware utilization inefficiencies caused by unstructured sparsity. Through a hardware-software methodology, new sparsity rules are introduced, nearly eliminating the load imbalance issue. The proposed Processing Element (PE) architecture can effectively select inputs for sparse networks while reducing the overhead of logic resources. The proposed architecture is implemented on the XCVU9P FPGA, achieving a frequency of 200 MHz. It achieves a computational throughput of 350.49 GOPs and 326.01 GOPs on ResNet-50 and ResNet-152, respectively, demonstrating a 1.2-$2.1\times $DSP efficiency improvement compared to previous works.

Vision Transformers (ViTs) have achieved excellent performance on various computer vision tasks, while their high computation and memory costs pose challenges for practical deployment. To address this issue, token-level pruning is used as an effective method to compress ViTs, discarding unimportant image tokens that contribute little to predictions. However, directly applying unstructured token pruning to window-based ViTs damages their regular feature map structure, resulting in load imbalance when deployed on mobile devices. In this work, we propose an efficient algorithm-hardware co-optimized framework to accelerate window-based ViTs via adaptive Mixed-Granularity Sparsity (MGS). At the algorithm level, a hardware-friendly MGS algorithm is developed by integrating the inherent sparsity, global window pruning, and local N:M token pruning to balance model accuracy and its computational complexity. At the hardware level, we present a dedicated accelerator equipped with a sparse computing core and two lightweight auxiliary processing units to execute window-based calculations efficiently using MGS. Additionally, we devise a dynamic pipeline interleaving dataflow to achieve on-chip layer fusion, which reduces the processing latency and maximizes data reuse. Experimental results demonstrate that, with similar computational complexity, our highly structured MGS algorithm can achieve comparable or even better accuracy than previous compression methods. Moreover, compared to existing FPGA-based accelerators for Transformers, our design can achieve$1.80~\sim ~6.52\times $and$1.16~\sim ~12.05\times $improvements in terms of throughput and energy efficiency, respectively.

Channel estimation (CE) is a critical component in the massive multi-input multi-output (MIMO) communication systems. Compared with conventional CE algorithms, deep learning (DL)-based approach becomes a promising alternative, due to its capability of offering enhanced performance and robustness across diverse scenarios. However, efficient DL-based CE algorithms have two key properties that make them challenging for implementation in existing architectures at the edge side: the diversity of deep neural networks (DNNs) and CE strategies, and the involvements of multiple computation-intensive tasks that compass conventional signal processing, artificial intelligence (AI) inference, and online learning. To address these challenges, a domain-specific processor based on an extended RISC-V instruction set architecture (ISA) is proposed to perform these DL-based CE algorithms. First, a dedicated RISC-V ISA extension is developed to support all essential operations required by a DL-based CE algorithm, such as matrix inversion, in a flexible manner. Building on the customized ISA extension, a highly adaptable and scalable RISC-V processor is developed, featuring scalar and vector posit arithmetic units to alleviate high computational and memory demands of DNNs during both inference and training phase. Additionally, a coarse-grained matrix accelerator is integrated to expedite various matrix operations ensuring high throughput. In this way, both high flexibility and computational efficiency are achieved. Finally, our processor is implemented on a TSMC 28-nm technology. Implementation results show that the processor achieves a speedup of$5.16\sim 6.80\times $for all matrix operations compared with the state-of-the-art work. Moreover, the proposed processor provides an area efficiency improvement of$1.61\times $and an energy efficiency enhancement of$6.6\sim 15.4\times $compared to the open-source vector processor Ara. Notably, this work is the first RISC-V domain-specific processor tailored for diverse DL-based CE algorithms.

Motivated by the huge success of Transformers in the field of natural language processing (NLP), Vision Transformers (ViTs) have been rapidly developed and achieved remarkable performance in various computer vision tasks. However, their huge model sizes and intensive computations hinder ViTs’ deployment on embedded devices, calling for effective model compression methods, such as quantization. Unfortunately, due to the existence of hardware-unfriendly and quantization-sensitive non-linear operations, particularly Softmax, it is non-trivial to completely quantize all operations in ViTs, yielding either significant accuracy drops or non-negligible hardware costs. In response to challenges associated with standard ViTs, we focus our attention towards the quantization and acceleration for efficient ViTs, which not only eliminate the troublesome Softmax but also integrate linear attention with low computational complexity, and propose Trio-ViT accordingly. Specifically, at the algorithm level, we develop a tailored post-training quantization engine taking the unique activation distributions of Softmax-free efficient ViTs into full consideration, aiming to boost quantization accuracy. Furthermore, at the hardware level, we build an accelerator dedicated to the specific Convolution-Transformer hybrid architecture of efficient ViTs, thereby enhancing hardware efficiency. Extensive experimental results consistently prove the effectiveness of our Trio-ViT framework. Particularly, we can gain up to$\uparrow {3.6}\times $,$\uparrow {5.0}\times $, and$\uparrow {7.3}\times $FPS under comparable accuracy over state-of-the-art ViT accelerators, as well as$\uparrow {6.0}\times $,$\uparrow {1.5}\times $, and$\uparrow {2.1}\times $DSP efficiency. Codes are available athttps://github.com/shihuihong214/Trio-ViT.

All-in-one image restoration (IR) recovers images from various unknown distortions by a single model, such as rain, haze, and blur. Transformer-based IR methods have significantly improved the visual effects of the restored images. However, deploying complex IR models on edge devices is challenging due to massive parameters and intensive computations. Moreover, existing accelerators are typically customized for a single task, resulting in severe resource underutilization when executing multiple tasks. Therefore, this paper develops an algorithm-hardware co-design framework to accelerate a novel CNN-Transformer cooperative model for multiple IR tasks. Firstly, on the algorithm level, an Efficient Restoration Foundational Model (ERFM) is proposed to recover corrupted images from various degradations with low model complexity. Secondly, to guide adaptive corruption removal, a novel prompt learning scheme is introduced to fuse context-related degradation cues and boost high-quality reconstruction. Thirdly, on the hardware level, an integer approximation method is proposed to avoid expensive hardware overhead caused by complex nonlinear operations, such as layer normalization and softmax while maintaining comparable IR quality. Moreover, a head stationary dataflow and softmax fusion mechanism are designed to reduce data movement and enhance on-chip resource utilization. Finally, an overall hardware architecture is developed and implemented in TSMC 28 nm CMOS technology. Experimental results show that our ERFM achieves better visual perception than other baselines on seven challenging IR tasks without task-specific fine-tuning. Moreover, compared to other accelerators for vision Transformers, our design can achieve 3.3$\times$and 3.7$\times$improvements in throughput and energy efficiency.

Classic McEliece, with a remarkably stable security level, has been selected as one of the four key-establishment algorithms in the fourth-round evaluation of the post-quantum cryptography (PQC) standardization process of national institute of standards and technology (NIST). However, its memory-intensive and time-consuming key generation poses an obstacle to widespread use. In this paper, we propose a fast hardware implementation of the key generation incorporating several architectural optimizations. For the Gaussian elimination, we optimize the scheduling of computing resources and the memory access process and present a high-performance and flexible systemizer with multiple low fan-out systolic arrays. Besides, an algorithmic-level parallelized design for entry generation and Gaussian elimination is proposed to reduce the redundant computation time. A compact entry generator with a multi-level feedback mechanism and a 2-D high-speed FFT module facilitates continuous streaming the generated entries into the systemizer.FPGA implementation results show that our designs for the key generation improve time-area efficiency by 11.9% to 43.2% compared to the state-of-the-arts. Moreover, compared to the hardware implementations for the key generation of the other two quasi-cyclic code-based PQC algorithms, ours for Classic McEliece based on the random code achieves close to or better results in several metrics.

Recently, four NIST-approved Post-Quantum Cryptography (PQC) algorithms are selected to be standardized. Three of them are lattice-based cryptographic schemes and feature the number-theoretic transform (NTT) as the computing bottleneck compelling fast and low-power hardware implementations. In this work, a high-speed and power-efficient NTT accelerator is presented leveraging the compute-in-memory (CIM) technique with bottom-up optimizations. Firstly, a carry-free modular multiplication (CFMM) algorithm is proposed, which utilizes on-the-fly reduction and hybrid-redundant representation to optimize the butterfly unit operation, the cornerstone of NTT. Based on the optimized algorithm, an efficient butterfly unit in memory (BUIM) is developed by co-designing with SRAM circuit, which saves the memory access energy, decreases operation cycles, and obtains ultra-short critical path. Additionally, the data pattern of CIM array is also improved to avoid redundant memory read/write operations, which further reduces memory access overhead. Finally, a combination of pipelined operation flow and constant interstage data mapping strategy is employed to bestow the proposed hybrid-redundant CIM NTT (HRCIM-NTT) architecture with minimized computing cycles and reduced routing overhead. The implementation under 45nm CMOS technology demonstrates that HRCIM-NTT achieves the highest throughput and lowest latency among the existing CIM-based NTT accelerators.

Nowadays, brain-inspired Spiking Neural Networks (SNNs) have been proven to effectively process Dynamic Vision Sensor (DVS) event data streams due to their event-driven computation and temporal characteristics. Among the various SNN models, the spiking-based Transformer has demonstrated superior performance. However, there is few effort focused on designing dedicated accelerators for spiking-based Transformers. In this paper, we propose an energy-efficient neuromorphic accelerator based on a novel spiking-based Transformer for DVS. At the algorithmic level, we propose a Deformable Spiking Transformer (DST), which incorporates novel Spike-Driven Deformable Attention modules to enhance feature extraction while reducing computational complexity. At the hardware level, we design an energy-efficient Spiking Convolution Core and Spiking Attention Core to efficiently support sparse spiking convolutions and deformable attention mechanisms in the DST. Moreover, to leverage dynamic sparsity and minimize processing latency, we introduce a sparse spiking computing flow that enables parallel processing of sparse computations in the spiking convolutions. Based on algorithm-hardware co-optimization, we develop an energy-efficient neuromorphic accelerator for DVS processing and implement it in TSMC 28nm CMOS technology. Experimental results show that the DST achieves promising accuracy on the DVS datasets while maintaining competitive inference latency. Compared to prior hardware designs for SNNs, the proposed accelerator has the highest peak throughput. In comparison to Transformer accelerators, it achieves at least$1.11 \times $improvement in energy efficiency.

The remarkable progress of Vision Transformer (ViT) models has significantly advanced performance in computer vision tasks. However, the deployment of ViTs in resource-constrained environments remains a challenge, as the attention computation mechanisms within these models form a significant bottleneck, requiring substantial memory and computational resources. To address this challenge, we introduce TAFP-ViT, a tailored hardware-software co-design framework for Vision Transformers. On the software level, TAFP-ViT leverages a learnable compressor to perform multi-head shared compression on feature maps, and fuses decompression reconstruction, QKV generation and QKV processing together for calculation, thereby greatly reducing memory and computation requirements. Furthermore, TAFP-ViT combines dynamic inter-layer token pruning to eliminate unimportant tokens and hardware-friendly intra-block row pruning to diminish redundant computations. The proposed software design converts the calculations before and after SoftMax into dense and sparse triple matrix multiplication (TMM) forms respectively. On the hardware level, TAFP-ViT proposes a configurable systolic array (SA) to efficiently adapt to the QKV fusion computation pattern. The SA has flexible PE units that can effectively support general matrix multiplication (GEMM), dense and sparse TMM. The TMM and flexible dataflows allow TAFP-ViT to avoid handling transpositions and storing intermediate computation results, greatly enhancing computational efficiency. Besides, TAFP-ViT innovatively designs a Top-k engine to support dynamic pruning on the fly with high throughput and low resource consumption. Experiments show that the proposed TAFP-ViT achieves remarkable speedups of 123.91×, 29.5×, and 3.01∼ 20.65× compared to conventional CPUs, GPUs, and previous state-of-the-art works, respectively. Additionally, TAFP-ViT reaches a throughput of up to 731.5 GOP/s and an impressive energy efficiency of 77.9 GOPS/W.

Chiplet technology has been a hot topic due to its potential for more efficient implementation of large-scale integrated circuits. In chiplet manufacturing, the general-purpose active interposer usually integrates chiplets from different vendors with a typical mesh network. This method of manufacturing is broadly recognized for its cost-efficiency. However, untrusted vendors make the chiplet system vulnerable to security threats such as timing side-channel attacks (TSA) based on network contention information. Even worse, the reliability of each chiplet is usually unknown beforehand to a general-purpose interposer’s manufacturer, so that TSAs can be on arbitrary chiplets at arbitrary time in the manufacturer’s view. To address this challenge, this work first quantitatively analyzes the attack patterns including reinforced styles, based on which, a resilient interposer architecture named Resister is proposed. A hardware defender is designed in every router to globally detect the malicious transaction patterns at runtime, and adaptively detour the transaction packets accordingly for security while maintaining the performance. According to the evaluation of GEM5 on SPEC 2017 and PARSEC benchmarks, Resister can effectively mitigate TSA with only a 1.7% performance overhead.

Over the past decades, Field-Programmable Gate Arrays (FPGAs) have become a choice for heterogeneous computing due to their flexibility, energy efficiency, and processing speed. OpenCL is used in FPGA heterogeneous computing for its high-level abstraction and cross-platform compatibility. Previous works have introduced optimization techniques in OpenCL for FPGAs to leverage FPGA-specific advantages. However, the multi-kernel pipeline technique, which can raise throughput and resource utilization, has not performed well. This article presents a CPU+FPGA heterogeneous platform with a novel execution model to optimize multi-kernel pipeline. Firstly, we extend OpenCL by introducing new APIs and additional functions to represent the execution model. Secondly, a hardware-software co-scheduling scheme is employed to manage execution. Thirdly, we design a holistic development flow and toolkit to facilitate the deployment of algorithms on the platform or the integration of RTL IP cores to the OpenCL environment. We validate the platform using a Range Doppler algorithm. The proposed development flow and integrated toolchain enhance the efficiency of integrating traditional RTL IP cores into the OpenCL environment. Experimental results demonstrate that, with a comparable processing speed (averaging 95%) to traditional RTL implementations, the platform successfully establishes the multi-kernel pipelines. Leveraging the multi-kernel pipeline, the platform achieves a significant improvement in multi-frame processing speed compared to traditional OpenCL.

Although vision transformers (ViTs) have achieved significant success, their intensive computations and substantial memory overheads challenge their deployment on edge devices. To address this, efficient ViTs have emerged, typically featuring convolution-transformer hybrid architectures to enhance both accuracy and hardware efficiency. While prior work has explored quantization for efficient ViTs to marry the hardware efficiency of efficient hybrid ViT architectures and quantization, it focuses on uniform quantization and overlooks the potential advantages of mixed quantization. Meanwhile, although several works have studied mixed quantization for standard ViTs, they are not directly applicable to hybrid ViTs due to their distinct algorithmic and hardware characteristics. To bridge this gap, we present M2-ViT to accelerate convolution-transformer hybrid efficient ViTs with two-level mixed quantization (M2Q). Specifically, we introduce a hardware-friendly M2Q strategy, characterized by both mixed quantization precision and mixed quantization schemes [uniform and power-of-two (PoT)], to exploit the architectural properties of efficient ViTs. We further build a dedicated accelerator with heterogeneous computing engines to transform algorithmic benefits into real hardware improvements. The experimental results validate our effectiveness, showcasing an average of 80% energy-delay product (EDP) saving with comparable quantization accuracy compared to the prior work. Codes are available athttps://github.com/lybbill/M2ViT.

The efficient training of Transformer-based neural networks on resource-constrained personal devices is attracting continuous attention due to domain adaptions and privacy concerns. However, Transformers’ intensive and complicated computations, especially the crucial nonlinear Softmax and activation (Act) functions, pose challenges for training deployment on edge. This brief proposes an efficient training architecture for both Softmax and Act functions. Specifically, we present a quantized nonlinear training algorithm based on fully integer (int) arithmetic with sufficient training accuracy. Then, we develop a reconfigurable hardware architecture to efficiently support various operations during the training of these nonlinear functions. Furthermore, a staged parallel and pipelined (SPAP) dataflow is presented to reduce latency and improve hardware efficiency. Experimental results show that our architecture achieves up to 1.0 Softmax GinS in throughput and 4.42 GinS/W in energy efficiency at 500 MHz on Xilinx ZCU102 FPGA, outperforming prior works.

Approximate nearest neighbor search (ANNS) plays an important role in modern artificial intelligence (AI) systems, being extensively utilized in search engines, advertising, and recommendation systems. With the advent of large language models (LLMs), ANNS is increasingly finding applications in edge scenarios such as personal assistants. The demand for efficient and fast ANNS solutions is, therefore, more pressing than ever. In this article, we propose a scalable and efficient field-programmable gate array (FPGA) implementation of ANNS based on the inverted file with product quantization (IVF-PQ) algorithm, thus marking the first hardware implementation supporting up to 1024-D datasets. First, we devise a novel architecture for the Top-Kmodule, capable of processing multiple input data streams simultaneously and linearly increasing throughput. Second, we adjust the data precision in several parts of our design, thus achieving obvious performance improvement without losing much recall. Moreover, we introduce a flexible distance calculation (Distance Cal) module that can be reused for various computational tasks at different query stages. We code our design in Verilog and implement it on Xilinx Alveo U280. The experimental results show that our search latency can be as low as 0.0071 ms at a 94% recall, while the power is 19.80 W. Compared to the state-of-the-art application-specified integrated circuit (ASIC) implementations, our design delivers a$4.5\times $speedup in latency and a 20% reduction in energy consumption.

The Transformer model is widely used in autonomous driving (AD) networks. However, diverse attention mechanisms and varying operators in AD networks lead to high computational complexity and substantial memory access requirements, presenting challenges to existing Transformer accelerators. To address these issues, we propose RETA-AD, a reconfigurable and efficient Transformer accelerator tailored for speeding up both normal attention (NA) and deformable attention (DA) computations within AD networks. First, a highly flexible 3-D Folded Dimension Systolic Array (FDSA) is developed, which is capable of processing small-width matrix multiplications (SWMMs) across various DA configurations, significantly improving hardware utilization and speed. Second, the computation of noncomputation-intensive (NCI) operators in AD networks is optimized, including a Reorganized Feature Map (RFM) sampling strategy to reduce the sampling time, and a pipeline reconfigurable (PR) Softmax module incorporating both coarse and fine-grained pipelines to support varying attention configurations with constantly high efficiency. Lastly, an Inter-tile Cross Parallel (ITCP) dataflow is designed to minimize on-chip storage requirements and hide the latency of NCI operations. The proposed RETA-AD is implemented on a Xilinx UltraScale+ FPGA development board. Experimental results show a 6.3–$8.9\times $speedup and a 13.7–$22.5\times $improvement in energy efficiency over the GPU A100 and the edge GPU Jetson AGX Xavier. Compared to previous FPGA-based Transformer accelerators, RETA-AD demonstrates a 1.1–$1.62\times $speedup and a 2.20–$2.62\times $improvement in energy efficiency.

Deploying deep neural networks (DNNs) on those resource-constrained edge platforms is hindered by their substantial computation and storage demands. Quantized multiprecision DNNs (MP-DNNs), denoted as MP-DNNs, offer a promising solution for these limitations but pose challenges for the existing RISC-V processors due to complex instructions, suboptimal parallel processing, and inefficient dataflow mapping. To tackle the challenges mentioned above, SPEED, a scalable RISC-V vector (RVV) processor, is proposed to enable efficient MP-DNN inference, incorporating innovations in customized instructions, hardware architecture, and dataflow mapping. First, some dedicated customized RISC-V instructions are introduced based on RVV extensions to reduce the instruction complexity, allowing SPEED to support processing precision ranging from 4- to 16-bit with minimized hardware overhead. Second, a parameterized multiprecision tensor unit (MPTU) is developed and integrated within the scalable module to enhance parallel processing capability by providing reconfigurable parallelism that matches the computation patterns of diverse MP-DNNs. Finally, a flexible mixed dataflow method is adopted to improve computational and energy efficiency according to the computing patterns of different DNN operators. The synthesis of SPEED is conducted on TSMC 28-nm technology. Experimental results show that SPEED achieves a peak throughput of 737.9 GOPS and an energy efficiency of 1383.4 GOPS/W for 4-bit operators. Furthermore, SPEED exhibits superior area efficiency compared with prior RVV processors, with the enhancements of$5.9\sim 26.9\times $and$8.2\sim 18.5\times $for 8-bit operator and best integer performance, respectively, which highlights SPEED’s significant potential for efficient MP-DNN inference.

Recently, transformers have shown strong performance in tasks such as computer vision and natural language processing. Notably, Swin Transformer has gained significant attention for its low computational complexity and impressive performance in computer vision tasks, due to its window attention mechanism and hierarchical architecture. However, these features also make hardware deployment more complicated. In this brief, we present an energy-efficient field-programmable gate array (FPGA) accelerator for Swin Transformer to support the hierarchical architecture and execute the window attention. First, we introduce a systolic array with alterable datapath (SAAD) to conduct the window attention. Second, we split the patch merging operation and design a data rearrangement module, which reduces the computing latency induced by the data rearrangement in Swin Transformer. Third, we present a parallelized dual-array dataflow to support different computing operations in Swin Transformer. We implement the accelerator on the Xilinx XCZU19EG platform. The proposed architecture achieves a throughput per digital signal processing (DSP) of 0.630 giga operations per second (GOPS)/DSP, which is$1.94\times $higher than existing works.

Video compression is essential for storing and transmitting video content. Real-time decoding is indispensable for delivering a seamless user experience. Neural video compression (NVC) integrates traditional coding techniques with deep learning, resulting in impressive compression efficiency. However, the real-time deployment of advanced NVC models encounters challenges due to their high complexity and extensive off-chip memory access. This article presents a novel NVC accelerator, called video compression neural processing unit (VCNPU), via an algorithm-hardware co-design framework. First, at the algorithmic level, a reparameterizable video compression network (RepVCN) is proposed to aggregate multiscale features and boost video compression quality. RepVCN can be equivalently transformed into a streamlined structure without extra computations after training. Second, a mask-sharing pruning strategy is proposed to compress RepVCN in the fast transform domain. It effectively prevents the destruction of sparse patterns caused by model simplification, maintaining the model capacity. Third, at the hardware level, a reconfigurable sparse computing module is designed to flexibly support sparse fast convolutions and deconvolutions of the compact RepVCN. Besides, a hybrid layer fusion pipeline is advocated to reduce off-chip data communication caused by extensive motion and residual features. Finally, based on the joint optimization of computation and communication, our VCNPU is constructed to realize adaptive adjustments of various decoding qualities and is implemented under TSMC 28-nm CMOS technology. Extensive experiments demonstrate that our RepVCN provides superior coding quality over other video compression baselines. Meanwhile, our VCNPU achieves$6.7\times $improvements in throughput,$2.9\times $in area efficiency, and$4\times $in energy efficiency compared to prior video processors.

Transformer is widely used in the field of artificial intelligence (AI) due to its excellent feature extraction capabilities. Its variant, the deformable transformer, is highly appreciated in autonomous driving and robotics since it employs a deformable attention mechanism to enhance feature extraction. However, due to its out-of-order memory access and data dependency, the deployment of the deformable transformer on mobile devices is much limited. To address these problems, a deformable attention transformer accelerator (DATA) is proposed in this work to speed up the processing by co-optimizing the algorithm and hardware. Specifically, we propose a memory-aware neural architecture search (NAS) method for deformable attention by constructing a continuous search space to automatically obtain a memory-efficient feature map slicing scheme. Based on the proposed slicing scheme, we design an efficient data flow to avoid the memory access conflict problem. In addition, a space-division multiplexing and time-division multiplexing hardware computing module is introduced to perform computations in the deformable attention layer, which greatly improves the utilization of hardware resources. Finally, the proposed accelerator is implemented on an Xilinx platform. In comparison, the proposed method achieves a maximum$2.42\times $improvement in computational efficiency over prior arts, and the memory access requirement is reduced to 12.5% of the baseline.

Due to the demand for high energy efficiency in deep neural network (DNN) accelerators, computing-in-memory (CIM) is becoming increasingly popular in recent years. However, current CIM designs suffer from high latency and insufficient flexibility. To address the issues, this brief proposes a Booth-multiplication-based CIM macro (BCIM) with modified Booth encoding and partial product (PP) generation method specially designed for CIM architecture. In addition, a methodology is presented for designing precision-reconfigurable digital CIM macros. We also optimize the precision-reconfigurable shift adder in the macro based on the cutting down carry connection method. The design attains a performance of 2048 GOPS and a peak energy efficiency of 79.15 TOPS/W in the signed INT4 mode at a frequency of 500 MHz.

Swin Transformer achieves greater efficiency than Vision Transformer by utilizing local self-attention and shifted windows. However, existing hardware accelerators designed for Transformer have not been optimized for the unique computation flow and data reuse property in Swin Transformer, resulting in lower hardware utilization and extra memory accesses. To address this issue, we develop SWAT, an efficient Swin Transformer Accelerator based on FPGA. Firstly, to eliminate the redundant computations in shifted windows, a novel tiling strategy is employed, which helps the developed multiplier array to fully utilize the sparsity. Additionally, we deploy a dynamic pipeline interleaving dataflow, which not only reduces the processing latency but also maximizes data reuse, thereby decreasing access to memories. Furthermore, customized quantization strategies and approximate calculations for non-linear calculations are adopted to simplify the hardware complexity with negligible network accuracy loss. We implement SWAT on the Xilinx Alveo U50 platform and evaluate it with Swin-T on the ImageNet dataset. The proposed architecture can achieve improvements of $2.02 \times \sim 3.11 \times$ in power efficiency compared to existing Transformer accelerators on FPGAs.

Extreme edge platforms, such as in-vehicle smart devices, require efficient deployment of quantized deep neural networks (DNNs) to enable intelligent applications with limited amounts of energy, memory, and computing resources. However, many edge devices struggle to boost inference throughput of various quantized DNNs due to the varying quantization levels, and these devices lack floating-point (FP) support for on-device learning, which prevents them from improving model accuracy while ensuring data privacy. To tackle the challenges above, we propose a precision-scalable RISC-V DNN processor with on-device learning capability. It facilitates diverse precision levels of fixed-point DNN inference, spanning from 2-bit to 16-bit, and enhances on-device learning through improved support with FP16 operations. Moreover, we employ multiple methods such as FP16 multiplier reuse and multi-precision integer multiplier reuse, along with balanced mapping of FPGA resources, to significantly improve hardware resource utilization. Experimental results on the Xilinx ZCU102 FPGA show that our processor significantly improves inference throughput by 1.6$\sim 14.6\times$ and energy efficiency by 1.1$\sim 14.6\times$ across various DNNs, compared to the prior art, XpulpNN. Additionally, our processor achieves a $16.5\times$ higher FP throughput for on-device learning.

Video compression is widely used in digital television, surveillance systems, and virtual reality. Real-time video decoding is crucial in practical scenarios. Recently, neural video compression (NVC) combines traditional coding with deep learning, achieving impressive compression efficiency. Nevertheless, the NVC models involve high computational costs and complex memory access patterns, challenging real-time hardware implementations. To relieve this burden, we propose an algorithm and hardware co-design framework named NVCA for video decoding on resource-limited devices. Firstly, a CNN-Transformer hybrid network is developed to improve compression performance by capturing multi-scale non-local features. In addition, we propose a fast algorithm-based sparse strategy that leverages the dual advantages of pruning and fast algorithms, sufficiently reducing computational complexity while maintaining video compression efficiency. Secondly, a reconfigurable sparse computing core is designed to flexibly support sparse convolutions and deconvolutions based on the fast algorithm-based sparse strategy. Furthermore, a novel heterogeneous layer chaining dataflow is incorporated to reduce off-chip memory traffic stemming from extensive inter-frame motion and residual information. Thirdly, the overall architecture of NVCA is designed and synthesized in TSMC 28nm CMOS technology. Extensive experiments demonstrate that our design provides superior coding quality and up to 22.7x decoding speed improvements over other video compression designs. Meanwhile, our design achieves up to 2.2x improvements in energy efficiency compared to prior accelerators.

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment.

The development of the novel theory of unlimited sampling (US) has enabled analog-to-digital converters (ADCs) to effectively manage input signals with dynamic ranges that far exceed the threshold voltage. However, the existing design of the US asynchronous sigma-delta modulator ADC (US-ASDM-ADC) employs a nonlinear modulo operation within a two-channel architecture to generate the remainder and integer parts, leading to significant amplitude loss due to non-ideal phenomena. To address this issue, we propose a novel single-channel architecture and feedback compensation mechanism for the US-ASDM-ADC. Our approach entails a single-channel folding module to generate the remaining modulo operation while simultaneously generating the integer part of the modulo operation and initiating amplitude correction via a Schmitt trigger-based feedback system. We validate our proposed approach through transistor-level simulations.

In massive multiple-input multiple-output (MIMO) detection, likelihood ascent search (LAS) is well-known for its near-optimum performance with low complexity. It employs gradient descent to enhance the performance of suboptimal MIMO detectors, specifically minimum mean-square error (MMSE). In this paper, we introduce several new techniques to improve the MMSE-based LAS in terms of either complexity or performance. The MMSE is first replaced with optimized coordinate descent algorithm (OCD), which performs near MMSE with lower complexity. Then, the conventional OCD and LAS are reformulated and approximated to better reuse the computation for gradient descent, which is required in both algorithms. Besides, we also optimize the search strategy of LAS, leading to the improvement in both complexity and performance. The proposed detector, modulation-based successive gradient descent (MB-SGD) algorithm, outperforms MMSE-LAS and the latest low-complexity near-optimum detector in terms of either complexity or performance for 64×8 and 128×8 MIMO systems under 256-QAM. The corresponding architecture for a 128 × 8 256-QAM MIMO system has 75.8% lower latency, 2.02 × higher area efficiency, and 0.3 dB gain when implemented on a ×Xilinx Virtex-7 FPGA compared to OCD’s.

Existing binary Transformers are promising in edge deployment due to their compact model size, low computational complexity, and considerable inference accuracy. However, deploying binary Transformers faces challenges on prior processors due to inefficient execution of quantized matrix multiplication (QMM) and the energy consumption overhead caused by multi-precision activations. To tackle the challenges above, we first develop a computation flow abstraction method for binary Transformers to improve QMM execution efficiency by optimizing the computation order. Furthermore, a binarized energy-efficient Transformer accelerator, namely BETA, is proposed to boost the efficient deployment at the edge. Notably, BETA features a configurable QMM engine, accommodating diverse activation precisions of binary Transformers and offering high-parallelism and high-speed for QMMs with impressive energy efficiency. Experimental results evaluated on ZCU102 FPGA show BETA achieves an average energy efficiency of 174 GOPS/W, which is 1.76∼21.92× higher than prior FPGA-based accelerators, showing BETA’s good potential for edge Transformer acceleration.

Multi-precision (MP) convolutional neural networks (CNNs) have exploited quantization techniques to achieve notable computation reductions while maintaining accuracy. However, most existing accelerators lack sufficient support for MP multiplications, hindering their ability to satisfy the diverse precision requirements of different layers in MP CNNs. To address this issue, we propose a flexible FPGA-based accelerator that efficiently processes CNN inference, supporting both symmetric and asymmetric bit-width computation. Specifically, a reconfigurable computing unit called MP-MAC is specially designed for efficient execution of MP computations to maximize computation utilization within a single DSP. Additionally, an optimized computing data arrangement, based on our flexible parallelism scheme, is presented to further enhance the performance of MP CNN deployment. Moreover, an MP performance model is introduced to estimate the transmission and computation latency, providing valuable guidance for efficient hardware design. The proposed accelerator achieves a throughput of up to 660.60 GOPS on Intel Arria 10 SoC FPGA, with 3.77× better DSP efficiency compared to prior work when evaluated on the same network.

Vision Transformers (ViTs) have achieved significant success in computer vision. However, their intensive computations and massive memory footprint challenge ViTs’ deployment on embedded devices, calling for efficient ViTs. Among them, EfficientViT, the state-of-the-art one, features a Convolution-Transformer hybrid architecture, enhancing both accuracy and hardware efficiency. Unfortunately, existing accelerators cannot fully exploit the hardware benefits of EfficientViT due to its unique architecture. In this paper, we propose an FPGA-based accelerator for EfficientViT to advance the hardware efficiency frontier of ViTs. Specifically, we design a reconfigurable architecture to efficiently support various operation types, including lightweight convolutions and attention, boosting hardware utilization. Additionally, we present a time-multiplexed and pipelined dataflow to facilitate both intra- and inter-layer fusions, reducing off-chip data access costs. Experimental results show that our accelerator achieves up to 780.2 GOPS in throughput and 105.1 GOPS/W in energy efficiency at 200MHz on the Xilinx ZCU102 FPGA, which significantly outperforms prior works.

The rapid advancement of Vision Transformer (ViT) models has greatly enhanced performance in computer vision tasks. However, deploying ViTs in resource-constrained environments presents a challenge as attention computation forms a bottleneck, necessitating extensive memory and computation resources. To address this issue, we propose HSViT, a dedicated hardware and software co-design framework specified for ViT. HSViT introduces a configurable and efficient accelerator with dedicated dataflows that takes advantage of the multi-level compression, including feature map compression, token pruning and hardware-friendly sparsity. The proposed accelerator reduces intermediate transmission for feature maps and Query, Key, and Value matrices while enhancing data reuse and processing element utilization for chain matrix multiplications. Moreover, an innovative Top-k engine, integrated into the accelerator, is presented to support various selection scenarios with high speed and low resource consumption. Experiments validate that the proposed HSViT delivers significant speedups of 123.91×, 29.5×, and 3.01 ∼ 20.65× over conventional CPUs, GPUs, and prior arts, respectively. HSViT also achieves the throughput of up to 731.5 GOP/s and PE utilization as high as 92%.

RISC-V processors encounter substantial challenges in deploying multi-precision deep neural networks (DNNs) due to their restricted precision support, constrained throughput, and suboptimal dataflow design. To tackle these challenges, a scalable RISC-V vector (RVV) processor, namely SPEED, is proposed to enable efficient multi-precision DNN inference by innovations from customized instructions, hardware architecture, and dataflow mapping. Firstly, dedicated customized RISC-V instructions are proposed based on RVV extensions, providing SPEED with fine-grained control over processing precision ranging from 4 to 16 bits. Secondly, a parameterized multi-precision systolic array unit is incorporated within the scalable module to enhance parallel processing capability and data reuse opportunities. Finally, a mixed multi-precision dataflow strategy, compatible with different convolution kernels and data precision, is proposed to effectively improve data utilization and computational efficiency. We perform synthesis of SPEED in TSMC 28nm technology. The experimental results demonstrate that SPEED achieves a peak throughput of 287.41 GOPS and an energy efficiency of 1335.79 GOPS/W at 4-bit precision condition, respectively. Moreover, when compared to the pioneer open-source vector processor Ara, SPEED provides an area efficiency improvement of 2.04× and 1.63× under 16-bit and 8-bit precision conditions, respectively, which shows SPEED’s significant potential for efficient multi-precision DNN inference.

Convolutional neural networks (CNNs) with large kernels, drawing inspiration from the key operations of vision transformers (ViTs), have demonstrated impressive performance in various vision-based applications. To address the issue of computational efficiency degradation in existing designs for supporting large-kernel convolutions, an FPGA-based inference accelerator is proposed for the efficient deployment of CNNs with arbitrary kernel sizes. Firstly, a Z-flow method is presented to optimize the computing data flow by maximizing data reuse opportunity. Besides, the proposed design, incorporating the kernel-segmentation (Kseg) scheme, enables extended support for large-kernel convolutions, significantly reducing the storage requirements for overlapped data. Moreover, based on the analysis of typical block structures in emerging CNNs, vertical-fused (VF) and horizontal-fused (HF) methods are developed to optimize CNN deployments from both computation and transmission perspectives. The proposed hardware accelerator, evaluated on Intel Arria 10 FPGA, achieves up to 3.91 × better DSP efficiency than prior art on the same network. Particularly, it demonstrates efficient support for large-kernel CNNs, achieving throughputs of 169.68 GOPS and 244.55 GOPS for RepLKNet-31 and PyConvResNet-50, respectively, both of which are implemented on hardware for the first time.

Robot vision systems, by providing abundant and crucial environmental information, enable robots to intelligently perceive environment and make autonomous decisions. However, DNN-based models targeting the depth estimation task as well as other robotic applications tend to be computationally complex, bringing challenges to the efficient deployment on edge devices. In this paper, we propose a precision-scalable vision accelerator for robotic applications. Firstly, we develop a bit-level computing strategy to build the fundamental processing unit for precision scalability, reducing hardware complexity dramatically. Secondly, we present an efficient processing unit group with optimizations in parallelism scalability and overhead reduction. Thirdly, an energy-efficient architecture and the dataflow are proposed, enabling the accelerator to flexibly handle various operations in visual tasks targeting robotic applications like depth estimation. Our design is synthesized under TSMC 28nm CMOS technology. Experiments show that our design achieves a 6.05 TOPS/W energy efficiency as well as 2.23× and 2.13× area efficiency compared with the previous precision-scalable accelerators and the stereo vision accelerators respectively.

In this paper, we present a Reformulated Euclidean Algorithm (REA) and its optimized architecture for Reed-Solomon decoding. Through algorithm transformations on a modified Euclidean algorithm by Berlekamp et al., the REA is derived, featuring free of inversion operations. It has a fixed number 2$t$of iterations (t is the error-correction capability), and owns a very simple description. By generalizing the Horiguchi-Koetter formula and exploring the early termination mechanism, we present the optimized reformulated Euclidean algorithm (OREA). The derivative architecture is a systolic one, consisting of 2t + 1 processing elements (PEs) with the critical path of one multiplier and one adder. Complexity comparisons show that the proposed OREA saves 30% resources over sDCMEA, the state-of-art architecture based on Euclidean algorithm, and has almost the same (actually slight lower) complexity as ePIBMA, the state-of-art architecture based on Berlekamp-Massey algorithm. Thus this work fills an important gap for the hardware implementation between two RS decoding algorithms.

Polar-coded multiple-input multiple-output (MIMO) system has obtained increasing attention recently, in which iterative detection and decoding (IDD) brings improved performance compared to separate detection and decoding (SDD) schemes. IDD requires the exchange of soft information between the detector and decoder, but the best-performing decoding algorithm for polar codes, the cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL) algorithm, cannot generate soft outputs by itself. To address this issue, existing high-performance soft-output decoders combine the CA-SCL decoder with the belief propagation (BP) or soft cancellation (SCAN) decoding process to generate soft outputs, leading to high computational complexity and memory requirements. In this work, an efficient partial sum-based soft-output SCL (PS-SSCL) decoder is proposed, which utilizes the inherent partial sums generated during the CA-SCL decoding process to calculate soft outputs without introducing any additional decoding procedure. For the 5G (256,128) polar code, the proposed PS-SSCL decoder achieves a 57% reduction in memory requirements and a 62% reduction in computational complexity compared to the state-of-the-art soft-output list (SOL) polar decoder. Additionally, the PS-SSCL decoder can also bring more than 0.2 dB gain over the SOL decoder, when integrated into the IDD receiver with the linear minimum mean square error (LMMSE) detector.

In Internet of Things (IoT) endpoint devices, some data or address ciphers are used for real-time memory protection to mitigate some side-channel attacks against memories. To better meet the requirements of real-time memory protection, this article proposes a hardware engine of permutation-based address encryption (PAE) to implement memory address encryption with flexible width adaptation, low latency, and low hardware overhead. When evaluated with TSMC’s 40-nm standard CMOS technology, PAE features lightweight characteristics with a gate count of 0.589 KGates, which is only 0.37% of advanced encryption standard (AES) and 33.50% of address cipher Galois field encryption (GF-Enc). The security of PAE in memory protection is quantitatively proven through both logic cryptanalysis and side-channel attacks. The results show that PAE performs effective mitigation in some side-channel attacks and provides better security than other address ciphers in resisting the brute-force attack, chosen-plaintext attack, and the differential attack. A RISC-V system with PAE and AES is deployed on an field-programmable gate array platform to analyze the impact on performance. The evaluation data show that PAE has no impact on system throughput in the case analysis, while AES reduces system throughput by 89.47%.

The computation of elementary functions is required in many tasks of Internet of Things (IoT) endpoint devices, for example, communications, image processing, and biomedical signal processing. IoT endpoint devices generally adopt software approaches to compute elementary functions, which take many cycles. To improve efficiency, this work proposes custom instructions for elementary functions to the open-source RISC-V instruction set architecture (ISA). In particular, several variants of the custom instructions (fast, intermediate, and tiny variants) are developed to satisfy the needs of various types of IoT devices. Microarchitecture design and VLSI circuit design are then proposed to efficiently support the extended ISA. Both software emulation and on-board evaluation of the new architecture are carried out with testbenches covering typical communication and computation tasks for IoT devices. The custom instructions gain speedups ranging from 3.3 to 18.0 compared to a baseline RV32IM design. ASIC synthesis results under TSMC 28nm technology demonstrate that the power overhead is$ \lt $5% with the tiny variant,$ \lt $17% with the intermediate variant, and$ \lt $26% with the fast variant, which is not significant considering the achieved speedup. The experimental results further confirm that the proposed custom instructions are computation-efficient and versatile to adapt to different IoT devices for various applications.

Cache side channel attacks are increasingly alarming in modern processors due to the recent emergence of Spectre and Meltdown attacks. A typical attack performs intentional cache access and manipulates cache states to leak secrets by observing the victim’s cache access patterns. Different countermeasures have been proposed to defend against both general and transient execution based attacks. Despite their effectiveness, they mostly trade some level of performance for security, or have restricted security scope. In this paper, we seek an approach to enforcing security while maintaining performance. We leverage the insight that attackers need to access cache in order to manipulate and observe cache state changes for information leakage. Specifically, we propose Prefender, a secure prefetcher that learns and predicts attack-related accesses for prefetching the cachelines to simultaneously help security and performance. Our results show that Prefenderis effective against several cache side channel attacks while maintaining or even improving performance for SPEC CPU 2006 and 2017 benchmarks.

Sparse training is one of the promising techniques to reduce the computational cost of deep neural networks (DNNs) while retaining high accuracy. In particular, N:M fine-grained structured sparsity, where only${N}$out of consecutive${M}$elements can be nonzero, has attracted attention due to its hardware-friendly pattern and capability of achieving a high sparse ratio. However, the potential to accelerate N:M sparse DNN training has not been fully exploited, and there is a lack of efficient hardware supporting N:M sparse training. To tackle these challenges, this article presents a computation-efficient training scheme for N:M sparse DNNs using algorithm, architecture, and dataflow co-design. At the algorithm level, a bidirectional weight pruning method, dubbed BDWP, is proposed to leverage the N:M sparsity of weights during both forward and backward passes of DNN training, which can significantly reduce the computational cost while maintaining model accuracy. At the architecture level, a sparse accelerator for DNN training, namely, SAT, is developed to neatly support both the regular dense operations and the computation-efficient N:M sparse operations. At the dataflow level, multiple optimization methods ranging from interleave mapping, pregeneration of N:M sparse weights, and offline scheduling, are proposed to boost the computational efficiency of SAT. Finally, the effectiveness of our training scheme is evaluated on a Xilinx VCU1525 FPGA card using various DNN models (ResNet9, ViT, VGG19, ResNet18, and ResNet50) and datasets (CIFAR-10, CIFAR-100, Tiny ImageNet, and ImageNet). Experimental results show the SAT accelerator with the BDWP sparse training method under 2:8 sparse ratio achieves an average speedup of$1.75\times $over that with the dense training, accompanied by a negligible accuracy loss of 0.56% on average. Furthermore, our proposed training scheme significantly improves the training throughput by$2.97\times $–$25.22\times $and the energy efficiency by$1.36\times $–$3.58\times $over prior FPGA-based accelerators.

The expectation propagation (EP) algorithm is near-optimal in massive multiple-input multiple-output (MIMO) systems but suffers from high computation complexity. Most of the previous works exploit the channel hardening property and introduce iterative matrix inversion algorithms to simplify the EP algorithm, but the performance degrades dramatically in non-ideal channels. In this paper, we propose a more universal EP-based detector, which can perform well in both ideal and non-ideal channels. Firstly, two general methods are proposed to effectively improve the detection performance and convergence speed of iterative matrix inversion algorithms under correlated channels. The proposed diagonal preprocessing (DP) method can improve the detection performance by more than 2-dB compared to not using this method; the novel eigenvalue parameter estimation method guarantees the convergence of all the frames. These two methods are applied to the second-order Richardson iteration (SORI) algorithm to derive the DP-SORI algorithm, which converges more than twice as fast as the state-of-the-art design. Secondly, for another important part of EP-based algorithms, namely the calculation of expectation and variance, complicated operations such as exponentiations, divisions, and inversions are all removed by algorithmic optimization. Moreover, based on the proposed approximate EP with DP-SORI (EPA-DP-SORI) algorithm, an efficient hardware design is developed, combining multiple optimization methods such as efficient matrix multiplication architecture design and low-complexity LDL decomposition. In addition to better detection performance compared with the state-of-the-art design, the presented EPA-DP-SORI detector can also deliver$1.27 \times $and$1.57 \times $higher area and energy efficiency.

The IEEE 1901 standard plays a crucial role in the extensive fields of smart grids, electric vehicles, and the Internet of Things. The forward error correction (FEC) codes specified in this standard include low-density parity-check convolutional codes (LDPC-CCs), Reed-Solomon (RS) codes, and RS convolutional concatenated (RSCC) codes. This work proposes a low-complexity decoder fully compliant with the standard. First, a heterogeneous scheme is introduced to LDPC-CC decoding. The new scheme assigns different data formats among processing elements (PEs), which reduces the overall storage size and enables a customized datapath down to the PE level. Then, to efficiently support diverse FEC demands in the standard, a reconfigurable architecture is thoroughly explored from both memory and datapath aspects. Leveraging these techniques, the first decoder compatible with the IEEE 1901 standard is developed and implemented with 55nm technology. Implementation results demonstrate that the proposed decoder satisfies the standard’s requirements while exhibiting low hardware complexity.

In massive multiple-input multiple-output (MIMO) detection, the likelihood ascent search (LAS) algorithm is well-known for its near-optimum performance and low complexity. It employs gradient descent to enhance the performance of suboptimal MIMO detectors, specifically the minimum mean-square error (MMSE) algorithm. In this paper, we introduce several techniques to improve the MMSE-based LAS (MMSE-LAS) algorithm in terms of both complexity and performance. To reduce complexity, the MMSE is first replaced with the low-complexity optimized coordinate descent (OCD) algorithm at the cost of negligible performance loss. Then, the conventional OCD and LAS algorithms are optimized for better computation reuse. Besides, we derive a new soft-output computation formula for LAS to improve the coded performance. The proposed modulation-based successive gradient descent (MB-SGD) detector outperforms MMSE-LAS and the latest work in terms of either complexity or performance for$64\times 8$and$128\times 8$LDPC-coded MIMO systems with multiple modulations from QPSK to 256-QAM. The corresponding architecture for a$128\times 8$coded MIMO system supporting multiple modulations is implemented on a Xilinx Virtex-7 FPGA and with TSMC 28-nm CMOS technology, exhibiting 74.5% lower latency and 0.24 dB gain compared to OCD on FPGA, and also achieving$14.59\times $energy efficiency and$2.04\times $area efficiency over the state-of-the-art implementation on ASIC.

Convolutional neural networks (CNNs) are expected to bridge the domain shift between the training data and real-world tasks. Moreover, the efficient training of CNNs on resource-constrained platforms has become more important because of communication latency and privacy concerns. However, deploying CNN training on edge devices is challenging due to the intensive computation and diverse computational patterns. In this work, we firstly propose a hybrid decomposition Winograd (HDW) method that significantly reduces the number of multiplications and flexibly handles various convolution operations during training. Secondly, we design a reconfigurable CNN training accelerator, named WinTA, utilizing a set of unified transformation units to support various Winograd operations. Thirdly, we implement an efficient and flexible data access scheme using a hierarchical barrel shifter network (HBSN). Experimental results on the Xilinx Alveo U50 FPGA Card demonstrate that WinTA effectively accelerates CNN training. Compared to CPU and GPU implementations, WinTA achieves speedups of 7.1 texttimes and 1.65 texttimes, respectively, while improving energy efficiency by 26.6 texttimes and 10.4 texttimes, respectively. Additionally, our design provides 1.24 texttimes and 2.04 texttimes improvements in terms of throughput and resource efficiency compared to prior-art FPGA-based training accelerator.

The costly multiplications challenge the deployment of modern deep neural networks (DNNs) on resource-constrained devices. To promote hardware efficiency, prior works have built multiplication-free models. However, they are generally inferior to their multiplication-based counterparts in accuracy, calling for multiplication-reduced hybrid models to marry the benefits of both approaches. To achieve this goal, recent works, i.e., NASA and NASA+, have developedNeuralArchitectureSearch (NAS) andAcceleration frameworks to search for and accelerate such hybrid models via a tailored differentiable NAS (DNAS) engine and dedicated ASIC-based accelerators. In this paper, we delve deeper into the inherent advantages of FPGAs and present an enhanced approach called NASA-F, which focuses on FPGA-oriented search and acceleration for hybrid models. Specifically,on the algorithm level, we develop a tailored one-shot supernet-based NAS engine to streamline the search for hybrid models, eliminating the need for executing NAS for each deployment as well as additional training/finetuning steps.On the hardware level, we develop a chunk-based accelerator to fully leverage the diverse hardware resources available on FPGAs for the acceleration of heterogeneous layers in hybrid models, aiming to enhance both hardware utilization and throughput. Extensive experimental results consistently validate the superiority of our NASA-F framework, e.g., we can gain$\uparrow 0.67\%$top-1 accuracy over the prior work NASA on CIFAR100 even without additional training steps for searched models. Additionally, we can achieve up to$\uparrow 1.86\times $throughout and$\uparrow 2.16\times $FPS with$\uparrow 0.39$% top-1 accuracy over the state-of-the-art multiplication-based system on Tiny-ImageNet. Codes are available athttps://github.com/shihuihong214/NASA-F.

The significant computational cost of multiplications hinders the deployment of deep neural networks (DNNs) on edge devices. While multiplication-free models offer enhanced hardware efficiency, they typically sacrifice accuracy. As a solution, multiplication-reduced hybrid models have emerged to combine the benefits of both approaches. Particularly, prior works, i.e., NASA and NASA-F, leverage Neural Architecture Search (NAS) to construct such hybrid models, enhancing hardware efficiency while maintaining accuracy. However, they either entail costly retraining or encounter gradient conflicts, limiting both search efficiency and accuracy. Additionally, they overlook the acceleration opportunity introduced by accelerator search, yielding sub-optimal hardware performance. To overcome these limitations, we propose NASH, a Neural architecture and Accelerator Search framework for multiplication-reduced Hybrid models. Specifically, as for NAS, we propose a tailored zero-shot metric to pre-identify promising hybrid models before training, enhancing search efficiency while alleviating gradient conflicts. Regarding accelerator search, we innovatively introduce coarse-to-fine search to streamline the search process. Furthermore, we seamlessly integrate these two levels of searches to unveil NASH, obtaining optimal model and accelerator pairing. Experiments validate our effectiveness, e.g., when compared with the state-of-the-art multiplication-based system, we can achieve$\uparrow 2.14\times $throughput and$\uparrow 2.01\times $FPS with$\uparrow 0.25\%$accuracy on CIFAR-100, and$\uparrow 1.40\times $throughput and$\uparrow 1.19\times $FPS with$\uparrow 0.56\%$accuracy on Tiny-ImageNet. Codes are available athttps://github.com/xuyang527/NASH.

The massive memory accesses of feature maps (FMs) in deep neural network (DNN) processors lead to huge power consumption, which becomes a major energy bottleneck of DNN accelerators. In this article, we propose a unified framework named Transform and Entropy-based COmpression (TECO) scheme to efficiently compress FMs with various attributes in DNN inference. We explore, for the first time, the intrinsic unimodal distribution characteristic that widely exists in the frequency domain of various FMs. In addition, a well-optimized hardware-friendly coding scheme is designed, which fully utilizes this remarkable data distribution characteristic to encode and compress the frequency spectrum of different FMs. Furthermore, the information entropy theory is leveraged to develop a novel loss function for improving the compression ratio and to make a fast comparison among different compressors. Extensive experiments are performed on multiple tasks and demonstrate that the proposed TECO achieves compression ratios of in ResNet-50 on image classification, in UNet on dark image enhancement, and in Yolo-v4 on object detection while keeping the accuracy of these models. Compared with the upper limit of the compression ratio for original FMs, the proposed framework achieves the compression ratio improvement of 21%, 157%, and 152% on the above models.

Placement is a critical step in the physical design for digital application specific integrated circuits (ASICs), as it can directly affect the design qualities such as wirelength and timing. For many domain specific designs, the demands for high performance parallel computing result in repetitive hardware instances, such as the processing elements in the neural network accelerators. As these instances can dominate the area of the designs, the runtime of the complete design’s placement can be traded for optimizing and reusing one instance’s placement to achieve higher quality. Therefore, this work proposes a mixed integer programming (MIP)-based placement refinement algorithm for the repetitive instances. By efficiently modeling the rectilinear steiner tree wirelength, the placement can be precisely refined for better quality. Besides, the MIP formulations for timing-driven placement are proposed. A theoretical proof is then provided to show the correctness of the proposed wirelength model. For the instances in various popular fields, the experiments show that given the placement from the commercial placers, the proposed algorithm can perform further placement refinement to reduce 3.76%/3.64% detailed routing wirelength and 1.68%/2.42% critical path delay under wirelength/timing-driven mode, respectively, and also outperforms the state-of-the-art previous work.

Recent research has shown that in massive multiple-input multiple-output (MIMO) detection, the model-driven machine learning (ML) detection algorithm with online training method can adapt to channel variations in real application scenarios and has high detection performance. However, the on-device training hardware of the ML-enhanced detector has not yet been addressed in the current literature. In this article, the architecture for the targeted hardware is designed through optimization on both the algorithms and the hardware. We first introduce a magnitude-based pruning strategy and then propose efficient MMNet (EMMNet)-type algorithms. In the improved algorithms, several algorithmic transformations or approximations are incorporated to reduce computational complexity. For instance, the exponential operation is replaced by a linear fitting function, and division is converted into hardware-efficient shift and subtraction operations. Moreover, to improve energy efficiency, the EMMNet-type algorithms are quantized with fixed-point (FXP) data formats and adopt a hardware-friendly stochastic gradient descent (SGD)-momentum optimizer. Based on the proposed algorithms, a low-complexity and high-throughput training architecture with reusable units is developed, which can support modulations from QPSK to QAM64. Compared with the MMNet, the presented EMMNet detector exhibits a 48% reduction in the number of multiplications without sacrificing detection performance, demonstrating remarkable hardware efficiency.

The homomorphic encryption over the torus (TFHE) is a promising fully homomorphic encryption (FHE) scheme that allows arbitrary homomorphic computations with the programmable bootstrapping (PBS) algorithm. However, PBS suffers from prohibitive computation complexity and latency, which hinders the practical applications of TFHE. To address these challenges, we propose ALT, a field-programmable gate array (FPGA) accelerator for PBS that exhibits high area efficiency and low latency. Our approach involves modifying the parameters of the PBS algorithm to strike a balance between the computation complexity and the decryption failure rate (DFR). In addition, we leverage the Chinese residue theorem (CRT) to exploit the inherent parallelism and construct the primes to eliminate the need of CRT process and facilitate fast modular arithmetic. The ALT design comprises several carefully designed computation units, including inverse CRT (ICRT), divide-and-round (DR) operation, and monomial number theoretic transform (MNTT). We employ algorithmic and architectural co-optimization techniques to optimize these units. Notably, ALT features a low-complexity MNTT module, enabling the utilization of the bootstrapping key unrolling (BKU) technique with reduced latency and minimal hardware resources. Furthermore, all submodules of ALT are parameterized and scalable, allowing the entire design to be configurable according to varying requirements across different application scenarios. Experimental results on FPGA demonstrate that ALT significantly outperforms a similar configurable work in terms of latency, throughput, and efficiency. In comparison with the fastest FPGA implementation, ALT can realize lower latency while reducing digital signal processor (DSP) reduction by over$50\%$, leading to enhanced area efficiency and energy efficiency.

Vision transformers (ViTs) have excelled in computer vision (CV) tasks but are memory-consuming and computation-intensive, challenging their deployment on resource-constrained devices. To tackle this limitation, prior works have explored ViT-tailored quantization algorithms but retained floating-point scaling factors, which yield nonnegligible requantization overhead, limiting ViTs’ hardware efficiency and motivating more hardware-friendly solutions. To this end, we propose P2-ViT, the first power-of-two (PoT) posttraining quantization (PTQ) and acceleration framework to accelerate fully quantized ViTs. Specifically, as for quantization, we explore a dedicated quantization scheme to effectively quantize ViTs with PoT scaling factors, thus minimizing the requantization overhead. Furthermore, we propose coarse-to-fine automatic mixed-precision quantization to enable better accuracy-efficiency tradeoffs. In terms of hardware, we develop a dedicated chunk-based accelerator featuring multiple tailored subprocessors to individually handle ViTs’ different types of operations, alleviating reconfigurable overhead. In addition, we design a tailored row-stationary dataflow to seize the pipeline processing opportunity introduced by our PoT scaling factors, thereby enhancing throughput. Extensive experiments consistently validate P2-ViT’s effectiveness. Particularly, we offer comparable or even superior quantization performance with PoT scaling factors when compared with the counterpart with floating-point scaling factors. Besides, we achieve up to$10.1\times $speedup and$36.8\times $energy saving over GPU’s Turing Tensor Cores, and up to$1.84\times $higher computation utilization efficiency against SOTA quantization-based ViT accelerators. Codes are available athttps://github.com/shihuihong214/P2-ViT.

Inspired by the key operation of vision transformers (ViTs), convolutional neural networks (CNNs) have widely adopted arbitrary-kernel convolutions to achieve high performance in diverse vision-based tasks. However, existing hardware efforts primarily focus on implementing CNN models that consist of a stack of small kernels, which poses challenges in supporting large-kernel convolutions. To address this limitation, we propose Amoeba, a flexible field-programmable gate array (FPGA)-based inference accelerator designed for efficiently supporting CNNs with arbitrary kernel sizes. Specifically, we present an optimized dataflow approach in collaboration with the Z-flow method and kernel-segmentation (Kseg) scheme, which enables flexible support for arbitrary-kernel convolutions without sacrificing efficiency. Additionally, we incorporate vertical-fused (VF) and horizontal-fused (HF) methods into the layer execution schedule to optimize the computation and data transfer process. To further enhance the CNN deployment performance, we employ the loop tiling scheme search (LTSS) method, guided by a fine-grained performance model, during the early design phase. The proposed Amoeba accelerator is evaluated on Intel Arria 10 SoC FPGA. The experimental results demonstrate excellent performance on prevalent and emerging CNNs, achieving a throughput of up to 286.2 GOPs. Notably, Amoeba achieves 4.36$\times$better DSP efficiency compared to prior works on the same network, highlighting its superior utilization of hardware resources for CNN inference tasks.

N:M fine-grained structured sparsity has attracted attention due to its practical sparsity ratio and hardware-friendly pattern. However, the potential to accelerate N:m sparse deep neural network (DNN) training has not been fully exploited, and there is a lack of efficient hardware supporting N:M sparse training. To tackle these challenges, this paper presents a computation-efficient scheme for N:M sparse DNN training, called CEST. A bidirectional weight pruning method, dubbed BDWP, is firstly proposed to significantly reduce the computational cost while maintaining model accuracy. A sparse accelerator, namely SAT, is further developed to neatly support both the regular dense operations and N:M sparse operations. Experimental results show CEST significantly improves the training throughput by$1.89-12.49\times$and the energy efficiency by$1.86-2.76\times$.

Vision Transformer (ViT) has emerged as a competitive alternative to convolutional neural networks for various computer vision applications. Specifically, ViTs’ multi-head attention layers make it possible to embed information globally across the overall image. Nevertheless, computing and storing such attention matrices incurs a quadratic cost dependency on the number of patches, limiting its achievable efficiency and scalability and prohibiting more extensive real-world ViT applications on resource-constrained devices. Sparse attention has been shown to be a promising direction for improving hardware acceleration efficiency for NLP models. However, a systematic counterpart approach is still missing for accelerating ViT models. To close the above gap, we propose a first-of-its-kind algorithm-hardware codesigned framework, dubbed VITALITY, for boosting the inference efficiency of ViTs. Unlike sparsity-based Transformer accelerators for NLP, VITALITY unifies both low-rank and sparse components of the attention in ViTs. At the algorithm level, we approximate the dot-product softmax operation via first-order Taylor attention with row-mean centering as the low-rank component to linearize the cost of attention blocks and further boost the accuracy by incorporating a sparsity-based regularization. At the hardware level, we develop a dedicated accelerator to better leverage the resulting workload and pipeline from VITALITY’s linear Taylor attention which requires the execution of only the low-rank component, to further boost the hardware efficiency. Extensive experiments and ablation studies validate that VITALITY offers boosted end-to-end efficiency (e.g., 3× faster and 3× energy-efficient) under comparable accuracy, with respect to the state-of-the-art solution. We make the codes available on https://github.com/GATECH-EIC/ViTaLiTy

Pre-trained BERT models have achieved impressive accuracy on natural language processing (NLP) tasks. However, their excessive amount of parameters hinders them from efficient deployment on edge devices. Binarization of the BERT models can significantly alleviate this issue but comes with a severe accuracy drop compared with their full-precision counterparts. In this paper, we propose an efficient and robust binary ensemble BERT (BEBERT) to bridge the accuracy gap. To the best of our knowledge, this is the first work employing ensemble techniques on binary BERTs, yielding BEBERT, which achieves superior accuracy while retaining computational efficiency. Furthermore, we remove the knowledge distillation procedures during ensemble to speed up the training process without compromising accuracy. Experimental results on the GLUE benchmark show that the proposed BEBERT significantly outperforms the existing binary BERT models in accuracy and robustness with a 2× speedup on training time. Moreover, our BEBERT has only a negligible accuracy loss of 0.3% compared to the full-precision baseline while saving 15× and 13× in FLOPs and model size, respectively. In addition, BEBERT also outperforms other compressed BERTs in accuracy by up to 6.7%.

Posit has been a promising alternative to the IEEE-754 floating point format for deep learning applications due to its better trade-off between dynamic range and accuracy. However, hardware implementation of posit arithmetic requires further exploration, especially for the dot-product operations dominated in deep neural networks (DNNs). It has been implemented by either the combination of multipliers and an adder tree or cascaded fused multiply-add units, leading to poor computational efficiency and excessive hardware overhead. To address this issue, we propose an open-source posit dot-product unit, namely PDPU, that facilitates resource-efficient and high-throughput dot-product hardware implementation. PDPU not only features the fused and mixed-precision architecture that eliminates redundant latency and hardware resources, but also has a fine-grained 6-stage pipeline, improving computational efficiency. A configurable PDPU generator is further developed to meet the diverse needs of various DNNs for computational accuracy. Experimental results evaluated under the 28nm CMOS process show that PDPU reduces area, latency, and power by up to 43%, 64%, and 70%, respectively, compared to the existing implementations. Hence, PDPU has great potential as the computing core of posit-based accelerators for deep learning applications.

The Internet of Things (IoT)-centric applications, such as augmented reality and self-driven cars, require real-time task processing, large bandwidth, and low data transmission latency. FPGA-based edge computing is considered an effective solution to tackle these challenges. As an excellent tool in these applications, nonlinear optimization methods involve computation-intensive and data-dependency operations leading to limited real-time applications. The limited-memory Broyden-Fletcher-Goldfarb-Shanno (L-BFGS) algorithm ranks among the most efficient algorithms for large-scale optimization problems. In this paper, we propose, for the first time, a high-parallel FPGA-based architecture for the two key parts of the L-BFGS algorithm: the search direction computation and line searching. Compared with the implementation on CPU, the search direction computation and line searching implementation on FPGA achieve$\mathbf{39.73}\times$and$\mathbf{5.50}\times$speedups, respectively. Compared with the straightforward implementation on GPU, the search direction computation on FPGA obtains a speedup of$\mathbf{31.03}\times$.

The verifiable delay function (VDF), as a kind of cryptographic primitives, has recently been adopted quite often in decentralized systems. Highly correlated to the security of VDFs, the fastest implementation for VDF evaluation is generally desired to be publicly known. In this paper, for the first time, we propose a low-latency hardware implementation for the complete VDF evaluation in the class group by jointly exploiting optimizations. On one side, we reduce the required computational cycles by decreasing the hardware-unfriendly divisions and increase the parallelism of computations by reducing the data dependency. On the other side, we provide low-latency large-number divisors, multipliers, and adders, respectively, while those operators are generally very hard to be accelerated. Besides, we carefully schedule the sub-modules and devise the low-latency architecture for the complete VDF evaluation. Finally, the proposed design is coded and synthesized under the TSMC 28-nm CMOS technology. The experimental results show that our design can achieve a speedup of 3.5x compared to the optimal C++ implementation for the VDF evaluation over an advanced CPU. Moreover, compared to the state-of-the-art hardware implementation for the squaring, a key step of VDF, we achieve about 2x speedup.

In the field of digital VLSI design, multimode circuits are the designs where the modes can be switched according to different application scenarios, and are commonly used in communication systems. In a multimode circuit, different modes are usually implemented by different circuits, which can lead to large circuit area consumption. For different modes, sharing their isomorphic circuit regions in the standard cell level can save the area. This goal is similar to that in the subgraph isomorphism problem, which is to check if a given graph is a subgraph of another one. However, subgraph isomorphism needs unacceptable runtime to solve as it is NP-complete. Even worse, finding the largest isomorphic regions of different circuits is a problem harder than subgraph isomorphism. In this article, we propose a novel algorithm for efficiently finding enough isomorphic circuit regions of different digital circuits in polynomial time, and give the theoretical proof of the correctness. The experiments show that the proposed approach can save 20%–25% area on average by sharing the standard cells between 2 and 4 circuits, while keeping the functional correctness. The proposed algorithm also has reasonable runtime and mostly incurs negligible timing overhead.

Recently, the National Institute of Standards and Technology (NIST) has identified the first four quantum-resistant algorithms for post-quantum cryptography (PQC) standardization. CRYSTALS-Kyber (Kyber) is the only public-key encryption and key-establishment algorithm among them. In this article, we propose a reconfigurable, high-speed, and area-efficient polynomial multiplication accelerator for Kyber to facilitate its practical applications. The cornerstone of polynomial multiplication is the butterfly unit (BU) structure, composed of modular addition, subtraction, and multiplication. For the modular multiplication, we adopt the Barrett reduction method and reduce the size of operands leveraging the form of modulus with a novel formula transformation, which significantly decreases the computational complexity and increases the maximum clock frequency. On the hardware side, we make four BU modules constitute a binomial arithmetic core (Bi-Core) as the basic reconfigurable unit. The memory access scheme tailored for parallel processing is explored with data-reusing and memory-grouping methods, and a compact control logic is devised. The complete polynomial multiplication architecture is coded with Verilog and implemented on a Xilinx Artix-7 xc7a100t-3 device. Experiment results demonstrate that our implementations with different configurations all outperform the state-of-the-art works in area efficiency by up to 39% improvement in terms of area-time product (ATP). Moreover, the proposed design with four Bi-Cores achieves the fastest speed among existing designs.

In recent years, to prevent computer systems from software attacks, hardware monitors are proposed as a type of efficient security enforcement scheme, which can detect software attacks at runtime. However, due to the limited flexibility of dedicated hardware monitors, one monitor can be only applied to a few targeted application scenarios, and is hard to defend against unconsidered attacks. This leads to high cost for redesigning monitors for new scenarios. Although recent studies propose flexible hardware monitors, the scope and security of the reconfigurable monitoring policies are still limited. To further improve the flexibility and security, this work proposes a monitor instruction set and multiple security-assisting designs for supporting general operations needed by various attack detection schemes. Based on the above efforts, an efficient programmable hardware monitor named ProMiSE is designed. After implemented on the RocketChip RISC-V processor, ProMiSE can be programmed to realize a wider range of monitoring policies with higher security and similar hardware resource overhead, compared with stateof-the-art flexible hardware monitors. With these advantages, ProMiSE still has the detection latency as low as 18-59 CPU cycles. The performance overhead ranges from 0%-23.4%, which is also reasonable compared with the dedicated hardware monitors of corresponding policies.

As the computation bottleneck in lattice-based cryptography (LBC), the polynomial multiplication based on number theoretic transform (NTT) has been continuously studied for flexible hardware implementations with high area-efficiency. This paper presents an area-efficient and configurable NTT-based polynomial multiplier (AC-PM) incorporating algorithmic and architectural level optimization techniques. For the core operation of polynomial multiplication, two low-complexity and fast modular multiplication algorithms are introduced with loose constraints of LBC-friendly primes. Based on the proposed algorithms, a reconfigurable processing element (RPE) is dedicatedly designed to execute all the operations in an NTT-based polynomial multiplication: NTT, inverse NTT (INTT), and coefficient-wise multiplication (CWM). The proposed AC-PM can be configured with different numbers of RPEs and supports various polynomial degrees without recompilation. Additionally, the dataflow complexity is greatly simplified. More importantly, to the best of our knowledge, the twiddle factors are reused, for the first time, to support both NTT and INTT with multiple polynomial degrees, which leads to increased flexibility of AC-PM with small overhead on hardware resource. FPGA implementation results demonstrate that the proposed AC-PM significantly outperforms the prior arts in both flexibility and area efficiency.

Multiplication is arguably the most computation-intensive operation in modern deep neural networks (DNNs), limiting their extensive deployment on resource-constrained devices. Thereby, pioneering works have handcrafted multiplication-free DNNs, which are hardware-efficient but generally inferior to their multiplication-based counterparts in task accuracy, calling for multiplication-reduced hybrid DNNs to marry the best of both worlds. To this end, we propose a Neural Architecture Search and Acceleration (NASA) framework for the above hybrid models, dubbed NASA+, to boost both task accuracy and hardware efficiency. Specifically, NASA+ augments the state-of-the-art (SOTA) search space with multiplication-free operators to construct hybrid ones, and then adopts a novel progressive pretraining strategy to enable the effective search. Furthermore, NASA+ develops a chunk-based accelerator with novel reconfigurable processing elements to better support searched hybrid models, and integrates an auto-mapper to search for optimal dataflows. Experimental results and ablation studies consistently validate the effectiveness of our NASA+ algorithm-hardware co-design framework, e.g., we can achieve up to 65.1% lower energy-delay-product with comparable accuracy over the SOTA multiplication-based system on CIFAR100. Codes are available athttps://github.com/GATECH-EIC/NASA.

Due to the rapid progress made in quantum computers, modern cryptography faces great challenges. Many digital signature schemes that have resistance to quantum computing are studied and standardized by several influential international organizations. The Leighton-Micali signature (LMS) protocol, one of the hash-based signature schemes, is standardized by both the Internet Engineering Task Force (IETF) and the National Institute of Standards and Technology (NIST) due to its well-studied security and relatively small signature size. However, the heavy computation load and high latency of LMS limits its practical applications. In this paper, for the first time, we propose a full hardware implementation of LMS to accelerate all the three stages:$key~generation$,$signature~generation$, and$verification$. Considering the scalability requirement and the characteristic of the parameter sets of LMS, we extract the coarse-grained basic logic, a hash group, and build a reconfigurable architecture for all available parameters by carefully designing the parallelism degree while achieving low latency and high hardware utilization efficiency. Then, we devise a fusion architecture for$key~generation$and$signature~generation$based on the hash group module. Moreover, for the$signature~verification$stage, we propose a separate architecture by applying the hash group module along with an efficient depth-first Merkle tree module. We code our designs with Verilog language in parameterized style and implement them on a Xilinx XCVU7P FPGA platform. The experimental results show that significant improvements are obtained for different parameter sets by the proposed designs when compared to state-of-the-art works.

Deformable convolutional networks (DCNs) have shown outstanding potential in video super-resolution with their powerful inter-frame feature alignment. However, deploying DCNs on resource-limited devices is challenging, due to their high computational complexity and irregular memory accesses. In this work, an algorithm-hardware co-optimization framework is proposed to accelerate the DCNs on field-programmable gate array (FPGA). Firstly, at the algorithm level, an anchor-based lightweight deformable network (ALDNet) is proposed to extract spatio-temporal information from the aligned features, boosting the visual effects with low model complexity. Secondly, to reduce intensive multiplications, an innovative shift-based deformable 3D convolution is developed using low-cost bit shifts and additions, maintaining comparable reconstruction quality. Thirdly, at the hardware level, a dedicated critical processing core, together with a block-level interleaving storage scheme, is presented to avoid dynamic and irregular memory accesses caused by the deformable convolutions. Finally, an overall architecture is designed to accelerate the ALDNet and implemented on an Intel Stratix 10GX platform. Experimental results demonstrate that the proposed design can provide significantly better visual perception than other FPGA-based super-resolution implementations. Meanwhile, compared with the prior hardware accelerators, our design can achieve$2.75\times $and$1.63\times $improvements in terms of throughput and energy efficiency, respectively.

Improving the performance of high-level computer vision tasks in adverse weather (e.g., haze) is highly critical for autonomous driving safety. However, collecting and annotating training sets for various high-level tasks in haze weather are expensive and time-consuming. To address this issue, we propose a novel haze generation model called HazeGEN by coupling the variational autoencoder and the generative adversarial network to automatically generate annotated datasets. The proposed HazeGEN leverages a shared latent space assumption based on an optimized encoder–decoder architecture, which guarantees high fidelity in the cross-domain image translations. To ensure that the generated image can truly facilitate high-level vision task performance, a semisupervised learning strategy is developed for HazeGEN to efficiently learn the useful knowledge from both the real-world images (with unsupervised losses) and the synthetic images generated following the atmosphere scattering model (with supervised losses). Extensive experiments and ablation studies demonstrate that training the model with our generated haze dataset greatly improves accuracy in high-level tasks such as semantic segmentation and object detection. Furthermore, one important but under-exploited issue is investigated to find out whether the developed dataset can be a good substitute for the real ones. Results show that the generated dataset has the most similar performance to the real-world collected haze dataset on multiple challenging industrial scenarios compared with prior works.

Text style transfer is an important task to render artistic texts from a reference image or style, and is widely desired in many visual creations. Previous works have brought some efficient methods for text style transfer, which facilitate users to design various artistic texts automatically. However, these works mainly focus on relatively simple text effects, and do not perform well on complex reference styles. In this paper, we propose a coarse-to-fine framework to generate exquisite texts with complex texture and structure in an unsupervised way, achieving real-time control of style scales (i.e., text stylistic degree or deformation degree). The key idea is to decouple the overall task into two steps, prototype generation and detail refinement, and explore delicate networks for each step to imitate the features at different levels. Based on this idea, in the first step, we present a novel pro-gen GAN to generate prototypes of artistic texts using the reference style, and develop a deformable module to empower the pro-gen GAN to continuously characterize the multi-scale shape features without network retraining. Furthermore, we propose a mix-attention training scheme for text style transfer, which can avoid artifacts and retain a clear text background. In the second step, we introduce two optimized networks for detail refinements. Experimental results show that the proposed method can synthesize exquisite stylized texts with complex reference styles, and surpass the state of the arts in texture reconstruction, contour imitation, and text image quality drastically.

Recently, the efficient training of deep neural networks (DNNs) on resource-constrained platforms has attracted increasing attention for protecting user privacy. However, it is still a severe challenge since the DNN training involves intensive computations and a large amount of data access. To deal with these issues, in this work, we implement an efficient training accelerator (ETA) on field-programmable gate array (FPGA) by adopting a hardware-algorithm co-optimization approach. A novel training scheme is proposed to effectively train DNNs using 8-bit precision with arbitrary batch sizes, in which a compact but powerful data format and a hardware-oriented normalization layer are introduced. Thus the computational complexity and memory accesses are significantly reduced. In the ETA, a reconfigurable processing element (PE) is designed to support various computational patterns during training while avoiding redundant calculations from nonunit-stride convolutional layers. With a flexible network-on-chip (NoC) and a hierarchical PE array, computational parallelism and data reuse can be fully exploited, and memory accesses are further reduced. In addition, a unified computing core is developed to execute auxiliary layers such as normalization and weight update (WU), which works in a time-multiplexed manner and consumes only a small amount of hardware resources. The experiments show that our training scheme achieves the state-of-the-art accuracy across multiple models, including CIFAR-VGG16, CIFAR-ResNet20, CIFAR-InceptionV3, ResNet18, and ResNet50. Evaluated on three networks (CIFAR-VGG16, CIFAR-ResNet20, and ResNet18), our ETA on Xilinx VC709 FPGA achieves 610.98, 658.64, and 811.24 GOPS in terms of throughput, respectively. Compared with the prior art, our design demonstrates a speedup of 3.65× and an energy efficiency improvement of 8.54× on CIFAR-ResNet20.

Nowadays, generative adversarial network (GAN) is making continuous breakthroughs in many machine learning tasks. The popular GANs usually involve computation-intensive deconvolution operations, leading to limited real-time applications. Prior works have brought several accelerators for deconvolution, but all of them suffer from severe problems, such as computation imbalance and large memory requirements. In this article, we first introduce a novel fast transformation algorithm (FTA) for deconvolution computation, which well solves the computation imbalance problem and removes the extra memory requirement for overlapped partial sums. Besides, it can reduce the computation complexity for various types of deconvolutions significantly. Based on FTA, we develop a fast computing core (FCC) and the corresponding computing array so that the deconvolution can be efficiently computed. We next optimize the dataflow and storage scheme to further reuse on-chip memory and improve the computation efficiency. Finally, we present a computation-efficient hardware architecture for GANs and validate it on several GAN benchmarks, such as deep convolutional GAN (DCGAN), energy-based GAN (EBGAN), and Wasserstein GAN (WGAN). The experimental results show that our design can reach 2211 GOPS under 185-MHz working frequency on Intel Stratix 10SX field-programmable gate array (FPGA) board with satisfactory visual results. In brief, the proposed design can achieve more than 2× hardware efficiency improvement over previous designs, and it can reduce the storage requirement drastically.

With the popularity of deep learning, the hardware implementation platform of deep learning has received increasing interest. Unlike the general purpose devices, e.g., CPU or GPU, where the deep learning algorithms are executed at the software level, neural network hardware accelerators directly execute the algorithms to achieve higher energy efficiency and performance improvements. However, as the deep learning algorithms evolve frequently, the engineering effort and cost of designing the hardware accelerators are greatly increased. To improve the design quality while saving the cost, design automation for neural network accelerators was proposed, where design space exploration algorithms are used to automatically search the optimized accelerator design within a design space. Nevertheless, the increasing complexity of the neural network accelerators brings the increasing dimensions to the design space. As a result, the previous design space exploration algorithms are no longer effective enough to find an optimized design. In this work, we propose a neural network accelerator design automation framework named GANDSE, where we rethink the problem of design space exploration, and propose a novel approach based on the generative adversarial network (GAN) to support an optimized exploration for high-dimension large design space. The experiments show that GANDSE is able to find the more optimized designs in negligible time compared with approaches including multilayer perceptron and deep reinforcement learning.

Among expectation propagation (EP)-based massive multiple-input–multiple-output (MIMO) detection algorithms, EP with weighted Neumann-series approximation (EPA-wNSA) has the lowest computational complexity while requiring many iterations to guarantee the detection performance, which severely limits the throughput of hardware implementations. Through the joint optimization of algorithm and hardware architecture, we propose an EP-based detector with higher throughput and area efficiency. First, the second-order Richardson iteration (SORI) algorithm is employed to replace the wNSA algorithm for higher convergence speed. Then three algorithmic transformations are proposed to minimize the overall complexity. Simulation results show that the proposed EPA-SORI algorithm requires much fewer iterations to achieve comparable or even better detection performance compared with EPA-wNSA. Furthermore, an efficient detector architecture is delicately designed by incorporating multiple optimization methods, such as reverse data flow, advanced addition, and rounding cells. Implemented with the Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm CMOS technology, the proposed detector has$2.2 \times $higher throughput than the state-of-the-art EP-based detector.

Transformers have achieved significant success in deep learning, and training Transformers efficiently on resource-constrained platforms has been attracting continuous attention for domain adaptions and privacy concerns. However, deploying Transformers training on these platforms is still challenging due to its dynamic workloads, intensive computations, and massive memory accesses. To address these issues, we propose an Efficient Training Accelerator for TRansformers (TRETA) through a hardware-algorithm co-optimization strategy. First, a hardware-friendly mixed-precision training algorithm is presented based on a compact and efficient data format, which significantly reduces the computation and memory requirements. Second, a flexible and scalable architecture is proposed to achieve high utilization of computing resources when processing arbitrary irregular general matrix multiplication (GEMM) operations during training. These irregular GEMMs lead to severe under-utilization when simply mapped on traditional systolic architectures. Third, we develop training-oriented architectures for the crucial Softmax and layer normalization functions in Transformers, respectively. These area-efficient modules have unified and flexible microarchitectures to meet various computation requirements of different training phases. Finally, TRETA is implemented under Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm technology and evaluated on multiple benchmarks. The experimental results show that our training framework achieves the same accuracy as the full precision baseline. Moreover, TRETA can achieve 14.71 tera operations per second (TOPS) and 3.31 TOPS/W in terms of throughput and energy efficiency, respectively. Compared with prior arts, the proposed design shows 1.4–$24.5\times $speedup and 1.5–$25.4\times $energy efficiency improvement.

The orthogonal matching pursuit (OMP) has been widely explored to realize real-time compressed sensing (CS) reconstruction. The matrix pseudo-inverse of the least squares (LSs) is the most computationally complex operation in the OMP. Among various algorithms to realize this complex operation, the alternative Cholesky decomposition (ACD) algorithm performs the best. However, it typically involves a very long computation time due to its iterative procedure. To accelerate the ACD-OMP algorithm, a novel method called clustered computing look-ahead (CCL) is proposed. Inspired by the famous parallel carry look-ahead adder (CLA), CCL adds a propagation matrix to decouple the data dependency in ACD and then uses a clustering operator to transform the iterative computation of ACD into a pipelined and parallelized computation. This brief also proposes an efficient hardware architecture of the CCL-based ACD-OMP algorithm for CS reconstruction. The proposed algorithm is implemented on field programmable gate array (FPGA). For sparse signals with the same sparsity and length, the proposed implementation is 1.96 times faster than state-of-the-art work.

Extended integrated interleaved (EII) codes, as the versatile alternative to locally recoverable codes (LRCs), show great potential in distributed storage systems, in which the output bit-error-rate (BER) below 10−15is usually demanded. However, it is time-consuming to reach such a low BER through normal software simulation, which brings inconvenience to the code construction. To solve the above problem, this work presents an analysis method to evaluate the decoding performance of EII codes, and no simulation is required. Numerical results show that the estimated frame-error-rate (FER) matches well with the simulated FER, so does the BER. Moreover, the failure probability of each decoding stage can be predicted accurately. Therefore, we can dig deep into the decoding behavior of each stage, which guides the adjustment of redundancy distribution, improving the error correction performance. Finally, the theoretical analysis for regular EII codes is simplified to reduce calculations.

With the rapid development of Ethernet, RS (544, 514) (KP4-forward error correction), which was widely used in high-speed Ethernet standards for its good performance-complexity trade-off, may not meet the demands of next-generation Ethernet for higher data transmission speed and better decoding performance. A concatenated code based on KP4-FEC has become a good solution because of its low complexity and excellent compatibility. For concatenated codes, aside from the selection of outer and inner codes, an efficient interleaving scheme is also very critical to deal with different channel conditions. Aiming at burst errors in wired communication, we propose a novel matrix interleaving scheme for concatenated codes which set the outer code as KP4-FEC and the inner code as Bose-Chaudhuri-Hocquenghem (BCH) code. In the proposed scheme, burst errors are evenly distributed to each BCH code as much as possible to improve their overall decoding efficiency. Meanwhile, the bit continuity in each symbol of the RS codeword is guaranteed during transmission, so the number of symbols affected by burst errors is minimized. Simulation results demonstrate that the proposed interleaving scheme can achieve a better decoding performance on burst-error channels than the original scheme. In some cases, the extra coding gain at the bit-error-rate (BER) of 1 × 10−15can even reach 1 dB.

Detailed routing for large-scale integrated circuits (ICs) is time-consuming. It needs to finish the wiring for millions of nets and handle complicated design rules. Due to the heterogeneity of net sizes, the greedy nature of the backbone maze routing, and interdependent workloads, accelerating detailed routing with parallelization is rather challenging. In this paper, we propose a FPGA-based implementation to accelerate the maze routing kernels in a most recent detailed router. Experimental results demonstrate that batched maze routing kernel is 3.1 × speedup on FPGA. Besides, our design gets deterministic results and has less than 1% quality degradation on ISPD 2018 contest benchmarks [1] .

Existing works on dialogue summarization often follow the common practice in document summarization and view the dialogue, which comprises utterances of different speakers, as a single utterance stream ordered by time. However, this single-stream approach without specific attention to the speaker-centered points has limitations in fully understanding the dialogue. To better capture the dialogue information, we propose a 2D view of dialogue based on a time-speaker perspective, where the time and speaker streams of dialogue can be obtained as strengthened input. Based on this 2D view, we present an effective two-stream model called ATM to combine the two streams. Extensive experiments on various summarization datasets demonstrate that ATM significantly surpasses other models regarding diverse metrics and beats the state-of-the-art models on the QMSum dataset in ROUGE scores. Besides, ATM achieves great improvements in summary faithfulness and human evaluation. Moreover, results on machine reading comprehension datasets show the generalization ability of the proposed methods and shed light on other dialogue-based tasks. Our code will be publicly available online.

Cache side channel attacks are increasingly alarming in modern processors due to the recent emergence of Spectre and Meltdown attacks. A typical attack performs intentional cache access and manipulates cache states to leak secrets by observing the victim's cache access patterns. Different countermeasures have been proposed to defend against both general and transient execution based attacks. Despite their effectiveness, they all trade some level of performance for security. In this paper, we seek an approach to enforcing security while maintaining performance. We leverage the insight that attackers need to access cache in order to manipulate and observe cache state changes for information leakage. Specifically, we propose PREFENDER,a secure prefetcher that learns and predicts attack-related accesses for prefetching the cachelines to simultaneously help security and performance. Our results show that PREFENDER is effective against several cache side channel attacks while maintaining or even improving performance for SPEC CPU2006 benchmarks.

Multiplication is arguably the most cost-dominant operation in modern deep neural networks (DNNs), limiting their achievable efficiency and thus more extensive deployment in resource-constrained applications. To tackle this limitation, pioneering works have developed handcrafted multiplication-free DNNs, which require expert knowledge and time-consuming manual iteration, calling for fast development tools. To this end, we propose a Neural Architecture Search and Acceleration framework dubbed NASA, which enables automated multiplication-reduced DNN development and integrates a dedicated multiplication-reduced accelerator for boosting DNNs' achievable efficiency. Specifically, NASA adopts neural architecture search (NAS) spaces that augment the state-of-the-art one with hardware inspired multiplication-free operators, such as shift and adder, armed with a novel progressive pretrain strategy (PGP) together with customized training recipes to automatically search for optimal multiplication-reduced DNNs; On top of that, NASA further develops a dedicated accelerator, which advocates a chunk-based template and auto-mapper dedicated for NASA-NAS resulting DNNs to better leverage their algorithmic properties for boosting hardware efficiency. Experimental results and ablation studies consistently validate the advantages of NASA's algorithm-hardware co-design framework in terms of achievable accuracy and efficiency tradeoffs. Codes are available at https://github.com/shihuihong214/NASA.

Transformers have been an indispensable staple in deep learning. However, it is challenging to realize efficient deployment for Transformer-based model due to their substantial computation and memory demands. To address this issue, we present an efficient sparse Transformer accelerator on FPGA, namely STA, by exploiting N:M fine-grained structured sparsity. Our design features not only a unified computing engine capable of performing both sparse and dense matrix multiplications with high computational efficiency, but also a scalable softmax module eliminating the latency from intermediate off-chip data communication. Experimental results show that our implementation achieves the lowest latency compared to CPU, GPU, and prior FPGA-based accelerators. Moreover, compared with the state-of the-art FPGA-based accelerators, it can achieve up to $12.28\times$ and $51.00\times$ improvement on energy efficiency and MAC efficiency, respectively.

Recently, on-device DNN training has attracted much attention due to its high performance on edge devices and great ability to protect user privacy. Low-power and high throughput implementations of DNN training are highly desired for resource-limited devices. In this paper, we present an efficient hardware accelerator that exploits triple sparsity to reduce the number of unnecessary operations during DNN training. The gradients pruning algorithm is employed to bring error sparsity. Firstly, sparse data are represented in compressed sparse block format, which is suitable for different memory access patterns in all training phases. Secondly, an efficient sparsity detection logic based on the aforementioned data storage format is proposed, which adopts a 2-level grained mechanism. Coarse-grained mask-matching units are reused to improve the energy efficiency, while fine-grained mask-matching units make PEs work independently to enhance throughput. Thirdly, based on the above sparsity detection logic, we propose an efficient architecture for DNN training. Experimental results show that our design can achieve up to 42.1 TOPS and 174.0 TOPS/W in terms of throughput and energy efficiency, respectively. The energy efficiency of our design is $2.12\times $ higher than the state-of-the-art training processor. For training a ResNet-50 model on the CIFAR10 dataset, the energy efficiency of our design achieves 14.10, 96.57, and 84.43 TOPS/W in the FP, BP, and WG phases, respectively.

Vision Transformer (ViT) has emerged as a powerful model with its extraordinary performance on multiple computer vision applications. However, the huge model size and the enormous energy consumption incurred by the dense matrix multiplications make ViT hard to be implemented on edge devices. To tackle these challenges, we develop a unified compression framework for Vision Transformer (UCViT), whose main focus is on compressing the original ViT model by incorporating the low bit-width quantization and the dense matrix decomposition. To maximally reduce the energy expenditure, we propose a dedicated design by leveraging aggressive quantization, in which the majority of the matrix multiplications are converted to the hardware-friendly shift and addition operations. Besides, we incorporate a small module into the quantized model by harnessing the unique characteristic of multi-head attention during matrix decomposition, which achieves significant accuracy recovery from the deeply compressed model with minimal impact on the energy efficiency. Benefited from the effective fusion of different compression techniques and the hardware-friendly operations, the proposed model can save up to 98% energy consumption in inference compared to the original ViT model. Experiments on CIFAR-10 and CIFAR-100 image classification tasks show that the proposed model obtains a highly compact structure with a competitive compression ratio (up to 6.7×), while causes small loss (less than 1%) on the accuracy.

Three-dimensional generative adversarial networks (3D-GAN) have attracted widespread attention in three-dimension (3D) visual tasks. 3D deconvolution (DeConv), as an important computation of 3D-GAN, significantly increases computational complexity compared with 2D DeConv. 3D DeConv has become a bottleneck for the acceleration of 3D-GAN. Previous accelerators suffer from several problems, such as large memory requirements and resource underutilization. To handle the above issues, a fast algorithm for 3D DeConv (F3DC) is proposed in this paper. F3DC applies a fast algorithm to reduce the number of multiplications and achieves a significant algorithmic strength reduction. Besides, F3DC removes the extra memory requirement for overlapped partial sums and avoids computational imbalance to fully utilize resources. Moreover, we design an F3DC-based hardware architecture, which consists of four fast processing units (FPUs). Each FPU includes a pre-process module, a EWMM module and a post-process module for F3DC transformation. By implementing our design on the Xilinx VC709 platform for 3D-GAN, we achieve a throughput up to 1700 GOPS and 4× computational efficiency improvement compared with prior works.

Deep convolutional neural networks (CNNs) have brought a significant amount of interlayer data during computation, resulting in a large data-exchange delay and power consumption. This paper proposes a Least-Squares Fitting Compression (LSFC) method to compress the interlayer data to resolve the above problem. In LSFC, the feature maps are firstly divided into block groups; then, two base blocks are selected for each block group. Finally, the LSFC core is applied to get the fitting parameters, and the fitting parameters are selectively stored in the on-chip memory according to the mean-squared error (MSE) results. The proposed compression method is hardware-implemented and integrated into an AI accelerator to support the on-the-fly compression process with a slight hardware overhead and latency. Experiments show that the LSFC can reduce the required on-chip storage space by 21.9% $\sim$ 33.6% during CNN computation without loss of network prediction.

The Lagrange Coded Computing (LCC), proposed recently by Yu et at., is regarded as a promising solution for most distributed learning algorithms thanks to its good tradeoff between resiliency, security, and privacy over cloud servers. As a kind of coded computing, LCC also costs extra computations in a local computer for encoding and decoding, which contains many complex operations, such as the continued product operations and divisions. In this paper, we present an efficient high-speed LCC codec architecture based on the linear regression algorithm for the first time. By analyzing the formulas and evaluating the hardware resource, we select a set of optimal parameters and remove most of the complex operations by storing the precomputed coefficients. Besides, the proposed architecture is inherently scalable and can be fully utilized and reused for encoding and decoding. The experimental results on an FPGA show that a significant speedup is achieved compared with the prior art.

Recently, deconvolutional neural network (DeCNN) has attracted widespread attention in various applications. The deconvolution (DeConv), as the main operation in DeCNN, has become the bottleneck of acceleration, due to its high computational complexity. Previous works have introduced fast algorithms such as the cascaded fast FIR algorithm (CFFA) and the Winograd algorithm to reduce the computational complexity of DeConv for the applications on mobile devices. Since these fast algorithms need different computing parameters to accelerate various operations, directly applying these methods to process DeCNNs with different kernels usually causes limited flexibility. To address this problem, we propose a reconfigurable scheme based on the fast transformation algorithm (FTA) to accelerate multiple types of DeConvs, minimizing the hardware overhead for reconfigurability. Based on this scheme, a reconfigurable hardware architecture is developed to support several types of DeConvs. In addition, an adaptive dataflow is proposed to handle different convolutional layers. The presented design can support several types of operations and achieve up to 222.54 GOPS under 210 MHz on the Intel Arria 10SX FPGA platform, which shows our design can obtain better flexibility and computational efficiency compared with prior arts.

Deep Forest is a prominent machine learning algorithm known for its high accuracy in forecasting. Compared with deep neural networks, Deep Forest has almost no multiplication operations and has better performance on small datasets. However, due to the deep structure and large forest quantity, it suffers from large amounts of calculation and memory consumption. In this paper, an efficient hardware accelerator is proposed for deep forest models, which is also the first work to implement Deep Forest on FPGA. Firstly, a delicate node computing unit (NCU) is designed to improve inference speed. Secondly, based on NCU, an efficient architecture and an adaptive dataflow are proposed, in order to alleviate the problem of node computing imbalance in the classification process. Moreover, an optimized storage scheme in this design also improves hardware utilization and power efficiency. The proposed design is implemented on an FPGA board, Intel Stratix V, and it is evaluated by two typical datasets, ADULT and Face Mask Detection. The experimental results show that the proposed design can achieve around $40 \times$ speedup compared to that on a 40 cores high performance x86 CPU.

Abstract The informed dynamic scheduling (IDS) strategies, in which the edge message with the maximum message‐residual is updated preferentially, achieve remarkable error‐correction performance when applied to low‐density parity‐check (LDPC) codes. However, the IDS strategies incur inferior convergence in iterative decoding owing to the greedy problem, which is called the update‐relayed trend here. In order to solve the greediness, two locally informed dynamic scheduling algorithms based on the law of large numbers are proposed. The proposed decoding algorithms use random select of check nodes over a predefined update range (RSPUR) which effectively suppresses the propagation of the update‐relayed trend and accordingly restrains the forming of multi‐update cycles. Moreover, the decoding algorithm is further improved based on random select of check nodes over an adjustable update range (RSCAR). The update ranges are selected based on the law of large numbers. Therefore, the computational resources can be allocated more equitably by increasing iterations. Simulation results show that both the proposed algorithms achieve excellent performance in terms of throughput and convergence with low decoding complexity over the Additive White Gaussian Noise (AWGN) and the fading channels compared to the previous IDS strategies. Hence, the proposed algorithms behave excellently over the wireless channels.

With the rapid revolution of open-source hardware, RISC-V architecture has been prevalent in both academic research and industrial developments. Due to the increasing threats of information leakage, it is imperative to provide a secure RISC-V ecosystem to defend against malicious software exploits. Toward this goal, data-flow integrity (DFI) is employed as a strict security policy for enforcing the legitimacy of each data access, thereby filtering out most of the attack exploits. However, due to the intensive computations needed by DFI, there are only limited proposals successfully implementing partial DFI with low performance overhead. Moreover, all the previous studies failed to enforce thecompleteDFI policy in a real hardware platform, while trading off security strength for performance efficiency. To provide RISC-V architecture with high security enforcement and low performance overhead, we leverage the open-source Rocket Chip and proposeRvDfi, the first complete DFI implementation based on RISC-V architecture with only 17.8% performance overhead on average and 3.9% in minimum, incurring much less performance loss compared to the 166.3% overhead caused by previous complete DFI implementation.

Thanks to relatively small public and secret keys, the Supersingular Isogeny Key Encapsulation (SIKE) protocol made it into the third evaluation round of the post-quantum standardization project of the National Institute of Standards and Technology (NIST). Even though a large body of research has been devoted to the efficient implementation of SIKE, its latency is still undesirably long for many real-world applications. Most existing implementations of the SIKE protocol use the Montgomery representation for the underlying field arithmetic since the corresponding reduction algorithm is considered the fastest method for performing multiple-precision modular reduction. In this paper, we propose a new data representation for supersingular isogeny-based Elliptic-Curve Cryptography (ECC), of which SIKE is a sub-class. This new representation enables significantly faster implementations of modular reduction than the Montgomery reduction, and also other finite-field arithmetic operations used in ECC can benefit from our data representation. We implemented all arithmetic operations in C using the proposed representation such that they have constant execution time and integrated them to the latest version of the SIKE software library. Using four different parameters sets, we benchmarked our design and the optimized generic implementation on a 2.6 GHz Intel Xeon E5-2690 processor. Our results show that, for the prime of SIKEp751, the proposed reduction algorithm is approximately 2.61 times faster than the currently best implementation of Montgomery reduction, and our representation also enables significantly better timings for other finite-field operations. Due to these improvements, we were able to achieve a speed-up by a factor of about 1.65, 2.03, 1.61, and 1.48 for SIKEp751, SIKEp610, SIKEp503, and SIKEp434, respectively, compared to state-of-the-art generic implementations.

The appealing property of low area, low power, and high bit error tolerance has made Stochastic Computing (SC) a promising alternative to conventional binary arithmetic for many computation intensive tasks, e.g., convolutional neural networks (CNNs). However, current SC-based CNN accelerators suffer from the intrinsic computation error and exponentially growing latency. In this work, we optimize both the architecture of SC multiply-and-accumulate (MAC) unit and the overall acceleration strategy of CNN accelerator to favor SC. A low-complexity bit-stream-extending method is proposed to suppress the computation error of SC and ensure the trained fix-point model can be deployed into SC-based hardware without fine-tuning. Besides, distribution-determined partition scheme is developed to design hybrid stochastic-binary computing (SBC) MAC unit which boosts the processing of bit streams at a minimum overhead. For the overall accelerator, the SBC-based MAC array is extended to reuse hardware resources and improve throughput, since the judiciously chosen loop unrolling strategy can better benefit SC operations. The proposed CNN accelerator with extended SBC-MAC array is synthesized and validated using TSMC 28nm CMOS on several representative CNNs, targeted at ImageNet dataset. Compared with precise binary implementation, our proposed design gains 44% area reduction and 50% power saving but induces only 4% additional computation latency and 0.5% accuracy degradation.

Existing deep convolutional neural networks (CNNs) generate massive interlayer feature data during network inference. To maintain real-time processing in embedded systems, large on-chip memory is required to buffer the interlayer feature maps. In this paper, we propose an efficient hardware accelerator with an interlayer feature compression technique to significantly reduce the required on-chip memory size and off-chip memory access bandwidth. The accelerator compresses interlayer feature maps through transforming the stored data into frequency domain using hardware-implemented$8\times 8$discrete cosine transform (DCT). The high-frequency components are removed after the DCT through quantization. Sparse matrix compression is utilized to further compress the interlayer feature maps. The on-chip memory allocation scheme is designed to support dynamic configuration of the feature map buffer size and scratch pad size according to different network-layer requirements. The hardware accelerator combines compression, decompression, and CNN acceleration into one computing stream, achieving minimal compressing and processing delay. A prototype accelerator is implemented on an FPGA platform and also synthesized in TSMC 28-nm COMS technology. It achieves 403GOPS peak throughput and$1.4\times \sim 3.3\times $interlayer feature map reduction by adding light hardware area overhead, making it a promising hardware accelerator for intelligent IoT devices.

Recently, massive multiple-input multiple-output (MIMO) detection schemes based on message passing detection (MPD) have attracted extensive attention due to their good performance-complexity tradeoff. In this paper, to facilitate a high-throughput detector design, we introduce a layered updating schedule and propose an improved layered MPD (ILMPD) algorithm. In the new algorithm, several algorithmic transformations or approximations are derived for lower complexity. For instance, by exploiting the property of quadratic functions, the numbers of multiplications and additions in the constellation matching are both reduced by half; Through reasonable approximations, the multiplication, addition, and sorting operations in the initialization are all removed. Moreover, a lightweight early termination strategy is explored, reducing the number of detection iterations by nearly 20%. Based on the proposed ILMPD algorithm, an area-efficient architecture is devised, where several optimization methods are proposed for fewer resources and higher clock frequency. Compared with the state-of-the-art design, the presented ILMPD detector can deliver a nearly$3\times $higher area efficiency. A reconfigurable version of the proposed detector has also been developed, which can well support modulations QPSK to 256-QAM and still exhibits a superior area efficiency.

To enable efficient deployment of convolutional neural networks (CNNs) on embedded platforms for different computer vision applications, several convolution variants have been introduced, such as depthwise convolution (DWCV), transposed convolution (TPCV), and dilated convolution (DLCV). To address the utilization degradation issue occurred in a general convolution engine for these emerging operators, a highly flexible and reconfigurable hardware accelerator is proposed to efficiently support various CNN-based vision tasks. Firstly, to avoid workload imbalance of TPCV, a zero transfer and skipping (ZTS) method is proposed to reorganize the computation process. To eliminate the redundant zero calculations of TPCV and DLCV, a sparsity-alike processing (SAP) method is proposed based on weight-oriented dataflow. Secondly, the DWCV or pooling layers are configured to be directly executed after standard convolutions without external memory accesses. Furthermore, a programmable execution schedule is introduced to gain better flexibility. Finally, the proposed accelerator is evaluated on Intel Arria 10 SoC FPGA. Experimental results show state-of-the-art performance on both large-scale and lightweight CNNs for image segmentation or classification. Specifically, the accelerator can achieve a processing speed up to 339.9 FPS and computational efficiency up to 0.58 GOPS/DSP, which is$3.3\times $better than the prior art evaluated on the same network.

Adaptive computing (AC) is a technique to dynamically select the layers to pass in a prespecified deep neural network (DNN) according to the input samples. In previous literature, AC was deemed as a standalone complexity-reduction skill. This brief studies AC through a different lens: we investigate how this strategy interacts with mainstream compression techniques in a unified complexity-reduction framework and whether its "input sample related" feature helps with the improvement of model robustness. Following this direction, we first propose a defensive accelerating branch (DAB) based on the AC strategy that can reduce the average computational cost and inference time of DNNs with higher accuracy compared with its counterparts. Then, the proposed DAB is jointly applied with the mainstream parameterwise compression skills, pruning and quantization, to build a unified complexity-reduction framework. Extensive experiments are conducted, and the results reveal quasi-orthogonality between the input-related and parameterwise complexity-reduction skills, which means that the proposed AC can be integrated into an off-the-shelf compressed model without hurting its accuracy. Besides, the robustness of the proposed compression framework is explored, and the experimental results demonstrate that DAB can be used as both the detector and the defensive tool when the model is under adversarial attacks. All these findings shed light on the great potential of DAB in building a unified complexity-reduction framework with both a high compression ratio and great adversarial robustness.

In this article, an efficient high-throughput depth engine is proposed to generate high-quality 3-D depth maps for speckle-pattern structured-light depth cameras. A dynamic-binarization (DB) method is introduced with a significant reduction of computational complexity in contrast to the sum-of-absolute-distance (SAD) method. The depth map evaluation shows good robustness compared with other window-based correlation methods. Parallel architecture and reuse of intermediate results are employed for efficient hardware implementation. Our design is verified on a field-programmable gate array (FPGA) and implemented in the SMIC 55-nm CMOS technology, achieving a frame rate of 1731.77 fps ($640\times480$) with an area efficiency of 3.75 fps/KGE. The proposed engine shows a$2.71\times $promotion of area efficiency in contrast to the SAD-based implementation. In addition, the subpixel estimation algorithm deployed in postprocessing is optimized for efficient hardware implementation, reducing the gate count by 69.2% without significant performance loss.

The IEEE 1901 standard for power line communication (PLC) enables simple connection among Internet of Things devices. The forward error correction (FEC) codes specified in the IEEE 1901 standard include low-density parity-check convolutional codes (LDPC-CCs) and Reed-Solomon convolutional concatenated (RSCC) codes. This work introduces an efficient reconfigurable encoder in full compliance with the IEEE 1901 standard. First, we propose a reconfigurable LDPC-CC encoder to fulfill the multirate requirement and improve the architecture by fine-tuned parallelization, which takes full advantage of the characteristics of the codeword structure. Then, for area reduction, the optimization regarding the RSCC encoder is extensively exploited. Moreover, the commonality between the encoders is discovered, and some circuitries are shared to reduce the hardware complexity. Equipped with these techniques, an efficient reconfigurable encoder for the IEEE 1901 standard is developed and implemented with 28-nm technology. Implementation results demonstrate that the proposed encoder can meet the throughput requirement of the IEEE 1901 standard and is both power- and area-efficient.

The Transformer has been an indispensable staple in deep learning. However, for real-life applications, it is very challenging to deploy efficient Transformers due to the immense parameters and operations of models. To relieve this burden, exploiting sparsity is an effective approach to accelerate Transformers. Newly emerging Ampere graphics processing units (GPUs) leverage a 2:4 sparsity pattern to achieve model acceleration, while it can hardly meet the diverse algorithm and hardware constraints when deploying models. By contrast, we propose an algorithm–hardware co-optimized framework to flexibly and efficiently accelerate Transformers by utilizing general N:M sparsity patterns. First, from an algorithm perspective, we propose a sparsity inheritance mechanism along with inherited dynamic pruning (IDP) to obtain a series of N:M sparse candidate Transformers rapidly. A model compression scheme is further proposed to significantly reduce the storage requirement for deployment. Second, from a hardware perspective, we present a flexible and efficient hardware architecture, namely, STA, to achieve significant speedup when deploying N:M sparse Transformers. STA features not only a computing engine unifying both sparse–dense and dense–dense matrix multiplications with high computational efficiency but also a scalable softmax module eliminating the latency from intermediate off-chip data communication. Experimental results show that, compared to other methods, N:M sparse Transformers, generated using IDP, achieves an average of 6.7% improvement on accuracy with high training efficiency. Moreover, STA can achieve$14.47\times $and$11.33\times $speedups compared to Intel i9-9900X and NVIDIA RTX 2080 Ti, respectively, and perform$2.00 \,\,\sim 19.47 \times $faster inference than the state-of-the-art field-programmable gate array (FPGA)-based accelerators for Transformers.

Recently, secure neural network (NN) inference, a combination of homomorphic encryption (HE) and NN, has attracted much attention. Nevertheless, a large number of computations, mainly brought by the HE scheme, form the bottleneck in real-time applications. In this article, we present a hardware accelerator on a field-programmable gate array (FPGA) for the homomorphic convolution layer (HomConvL), which is the most computation-intensive part of the HE-based secure inference. First, we propose a new HomConvL algorithm called packed rotations at inputs (PaRotI), which is suitable for hardware implementation for its inherent high parallelism and low complexity with acceptable noise growth and moderate resource consumption. Then, we present three highly parallel architectures for different parameter sets and application scenarios of state-of-the-art HomConvL algorithms. The new architectures are implemented on a Xilinx VCU110 FPGA board, and the experimental results demonstrate that our designs can achieve 15.31–$19.46\times $speedups compared with the software implementations.

Training deep neural networks (DNNs) on edge devices has attracted increasing attention in real-world applications for domain adaption and privacy protection. However, deploying DNN training on resource-limited edge devices is challenging as there are massive computations and data transportation in training. To address this issue, we propose an energy-efficient training accelerator in this work by employing a hybrid compression strategy. Here, various data redundancies are fully exploited, and the real triple-side sparsity is achieved. Hence, the computational complexity is drastically reduced with negligible accuracy loss across a range of transfer learning tasks. To facilitate triple-side zero-skipping operations during different training stages, we first present a novel sparse data representation and a triple-sparsity index matching scheme. Second, a sparse tensor processing unit (STPU) arranged in a hierarchical structure is developed, which enables a flexible dataflow to process convolutional (Conv) and fully connected (FC) layers with diverse computational patterns throughout the entire training. Third, an auxiliary processing unit (APU) is designed to execute some postprocessing operations, such as rectified linear unit (ReLU) and on-the-fly pruning. Finally, the training accelerator is implemented under Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm process and evaluated on multiple benchmarks. The experimental results show that THETA achieves 7.28–22.32 tera operations per second (TOPS) and 45.24–133.70 TOPS/W in performance and energy efficiency, reducing 40–$72\times $training time and 19–$63\times $energy consumption over dense training, respectively. Compared with the prior art, our design offers$1.6\times $throughput and$1.9\times $energy efficiency, respectively.

Quasi-cyclic low-density parity-check (QC-LDPC) codes for modern communication standards usually have multiple code rates and block lengths. Therefore, reconfigurable LDPC decoders have received widespread attention, which require circular-shift networks to support various expansion factors. Besides, for inputs smaller than the network size, the circular-shift network is desired to process multiple frames in parallel to maximize hardware utilization efficiency. The increasing demands put severe challenges to low-complexity implementations of shift networks, especially for codes with numerous expansion factors, such as 5G LDPC codes. In this brief, we present a universal design of efficient reconfigurable circular-shift networks. Through an ingenious modification on the order of permutations, the generation of control signals is considerably simplified, leading to a significant reduction of area and critical path. Moreover, a hybrid architecture organically integrating different networks is proposed for further complexity reduction. Implementation results under TSMC 90 nm technology demonstrate that the proposed network can achieve 25% area reduction and 46% area-efficiency (AE) improvement over the state-of-the-art ones.

The lattice-based cryptography (LBC) has been widely used recently in many compute-intensive applications, such as the post-quantum cryptography (PQC) and privacy-preserving deep learning, where the main task for such applications is to improve the computational efficiency. The modular multiplication operations, mainly involved in the number theoretic transform (NTT), comprise a large proportion of the whole computations required by an LBC. This paper presents a novel "decompose-and-reduce" modular multiplication algorithm (DARM), considering primes with the form of q = 22N−δ and δN−2. The inherent structure of the modulus is exploited and the intermediates’ data widths are reduced. Moreover, a low-complexity and fast multiplier is elaborately devised based on DARM. To further validate the performance of our multiplier, an n-point NTT design with DARM is implemented with various configurations. FPGA implementation results demonstrate that compared with the prior arts, the proposed multiplier has 1.12-1.89× speedups with the least DSP utilization. For the case of ⌈log2q⌉ = 60 and n = 4096, the NTT implementation with DARM achieves up to 41.2% and 61.2% reductions in LUTs and DSPs, respectively.

Despite the great success in Natural Language Processing (NLP) area, large pre-trained language models like BERT are not well-suited for resource-constrained or real-time applications owing to the large number of parameters and slow inference speed. Recently, compressing and accelerating BERT have become important topics. By incorporating a parameter-sharing strategy, ALBERT greatly reduces the number of parameters while achieving competitive performance. Nevertheless, ALBERT still suffers from a long inference time. In this work, we propose the ELBERT, which significantly improves the average inference speed compared to ALBERT due to the proposed confidence-window based early exit mechanism, without introducing additional parameters or extra training overhead. Experimental results show that ELBERT achieves an adaptive inference speedup varying from 2× to 10× with negligible accuracy degradation compared to AL-BERT on various datasets. Besides, ELBERT achieves higher accuracy than existing early exit methods used for accelerating BERT under the same computation cost. Furthermore, to understand the principle of the early exit mechanism, we also visualize the decision-making process of it in ELBERT. Our code is publicly available online.1

Recently, style transfer networks have received widespread attention in computer vision field, which combine stylistic features from a style image and content information from a content image to generate an output. However, the high-resolution synthesized outputs come at the cost of intensive computation, making it difficult to employ style transfer networks on embedded devices with limited computational resources. To address this issue, we propose a compression algorithm for one of the influential CNN-based style transfer networks, which is named Image Transform Net (ITNet), and gain a Light-weight Image Transform Net (LITNet) accordingly. To improve the performance of ITNet, normalization layers and the structure of upsampling blocks are modified, and depthwise separable convolutions combined with width multiplier are employed to obtain a brand-new light-weight network. However, since the representation ability of light-weight networks is too weak for unsupervised learning tasks such as style transfer, directly using the above techniques to compress the model leads to unstable training processes and yields poor outputs. To solve this problem, a novel distillation loss is proposed to convert unsupervised learning into supervised learning. Besides, the weights between the original losses and the distillation loss are balanced for better visual results. Experimental results demonstrate the effectiveness of our LITNet. With minimal visual quality degradation, the light-weight network can achieve more than 67 × compression in model size and 63× reduction in FLOPs. Codes and pre-trained models are available at https://github.com/shihuihong214/LITNet.

Open-source deep-learning frameworks are prevalent in designing, training, and deploying deep neural networks (DNNs) on general-purpose computing devices, such as CPU, GPU, and DSP. However, for custom-designed reconfigurable hardware accelerators, there is no existing universal framework, capable of optimizing DNN deployment configuration and guiding the hardware design with specific accuracy and efficiency requirements. In the paper, we proposed a cross- platform framework, which can convert deep-learning models from popular open-source frameworks to intermediate representation and optimize weight/activation dynamic ranges and quantization strategy to achieve better efficiency and accuracy based on a baseline reference design of hardware accelerator. With a few unlabeled data, the proposed framework can analyze the statistical inference information, compare different bit-width impacts, and optimize network structure. We further illustrate the detailed experiment results using the framework, showing mAP and top-1 accuracy loss is less than 1.5% and 1.2% with 12-bit and 8-bit activation-constrained quantization schemes respectively for object detection and image classification.

Three-dimensional convolutional neural networks (3D CNNs) have attracted great attention in many complex computer vision tasks. However, it is difficult to deploy 3D CNNs on practical applications due to high algorithmic complexity, imposing the urgent requirement for dedicated accelerators. In this paper, F3D, a fast algorithm for 3D CNNs, is proposed based on 3D Fast Fourier Transform (FFT) and achieves a significant algorithmic strength reduction. We then propose an F3D-based hardware architecture, featuring a flexible FFT module and an efficient partial sum aggregation module. Furthermore, a dataflow for efficient mapping of 3D CNNs is designed, leading to a significant reduction of memory access. To demonstrate the efficiency of the above-mentioned techniques, we implement the widely used 3D CNN model, C3D, as our benchmark on the Xilinx VC709 platform. The experimental result shows that compared with the state-of-the-art accelerator, our work achieves a considerable throughput up to 864.1 GOPs, along with 1.68x and 2.00 x efficiency improvement on energy and DSP utilization, respectively.

To achieve higher accuracy in machine learning tasks, very deep convolutional neural networks (CNNs) are designed recently. However, the large memory access of deep CNNs will lead to high power consumption. A variety of hardware-friendly compression methods have been proposed to reduce the data transfer bandwidth by exploiting the sparsity of feature maps. Most of them focus on designing a specialized encoding format to increase the compression ratio. Differently, we observe and exploit the sparsity distinction between activations in earlier and later layers to improve the compression ratio. We propose a novel hardware-friendly transform-based method named 1D-Discrete Cosine Transform on Channel dimension with Masks (DCT-CM), which intelligently combines DCT, masks, and a coding format to compress activations. The proposed algorithm achieves an average compression ratio of 2.9× (53% higher than the state- of-the-art transform-based feature map compression works) during inference on ResNet-50 with an 8-bit quantization scheme.

Due to the rapid progress made in quantum computers, modern cryptography faces great challenges. Many new digital signature schemes that have resistance to quantum computing are being presented for Post-Quantum Cryptography (PQC) standardization. The Leighton-Micali signature (LMS), a kind of hash-based signature scheme, is selected as a promising candidate for the PQC signature protocols by the Internet Engineering Task Force (IETF) because of its small private and public key sizes. However, the low-efficiency in key generation forms the bottleneck in practical applications. In this paper, we propose a high-speed architecture for the key generation to accelerate the LMS for the first time. The architecture is delicately devised to be scalable, supporting all the parameter sets for the LMS. The degree of parallelism is carefully designed to achieve low latency and high hardware utilization efficiency. Moreover, the control flow is well managed to accommodate different parameter sets with constant power for the consideration of anti-power analysis attacks. We code our design with Verilog language and implement it on the Xilinx Zynq UltraScale+ FPGA. The experimental results show that, compared with the optimal software implementation running on an Intel(R) Core(TM) i7-6850K 3.60GHz CPU with threading enabled, the new design achieves 55x to 2091x speedup in different parameter configurations.

The extended Greatest Common Divisor (GCD) is an extension of the GCD operation, which computes not only the GCD of integers a and b but also the Bezout's coefficients that are integers x and y such that ax + by =3D GCD(a,b). Recently, the large-number extended GCD algorithm is used in the core function of the next-generation blockchain systems and served as the most time-consuming operation. Considering the efficiency, speeding up this operation is urgently desired. However, the extended GCD, which is rarely explored in literature, is extremely hard to parallelize because of long serial operations with strong data dependency. In this paper, we propose a low- latency architecture for the extended GCD of large numbers by utilizing many algorithmic transformations and architectural optimizations. Firstly, a parallel extended GCD algorithm is well studied and modified to be practical in hardware. Secondly, a high-parallel architecture is designed for the selected extended GCD, where the trade-off is well evaluated between computation latency and power consumption. Finally, the architecture is coded using Verilog language and synthesized under the TSMC 28- nm CMOS technology. The experimental results for the 1024-bit extended GCD show that our design significantly outperforms the prior arts.

Abstract Multiple‐input multiple‐output‐sparse code multiple access, a non‐trivial integration of sparse code multiple access and multiple‐input multiple‐output techniques, is able to achieve high spectrum efficiency and massive user connections. However, this integration also increases the complexity of signal detection. Here, the signal detection problem of multiple‐input multiple‐output sparse code multiple access is transformed into a tree search problem and use sphere decoding to detect the signal. By setting the initial radius to positive infinity, sphere decoding can achieve optimal maximum likelihood performance while the complexity is high. In order to further reduce the complexity of sphere decoding, a block‐wise sorted QR decomposition algorithm is proposed. Based on block‐wise sorted QR decomposition, the improved sphere decoding, namely block‐wise sorted QR decomposition‐sphere decoding, is able to make the tree search more efficient. Since only the detection order of each user's signal has been changed, block‐wise sorted QR decomposition‐sphere decoding can maintain the optimal maximum likelihood performance. Simulation results and complexity analysis show that block‐wise sorted QR decomposition‐sphere decoding can achieve optimal performance and both hard‐output and soft‐output block‐wise sorted QR decomposition‐sphere decoding have much lower complexity than joint message passing algorithm. Furthermore, given the same signal‐to‐noise ratio, the complexity of block‐wise sorted QR decomposition‐sphere decoding decreases with the increase of receiving antennas, while the complexity of joint message passing algorithm increases linearly.

The training of Deep Neural Networks (DNNs) brings enormous memory requirements and computational complexity, which makes it a challenge to train DNN models on resource-constrained devices. Training DNNs with reduced-precision data representation is crucial to mitigate this problem. In this article, we conduct a thorough investigation on training DNNs with low-bit posit numbers, a Type-III universal number (Unum). Through a comprehensive analysis of quantization with various data formats, it is demonstrated that the posit format shows great potential to be employed in the training of DNNs. Moreover, a DNN training framework using 8-bit posit is proposed with a novel tensor-wise scaling scheme. The experiments show the same performance as the state-of-the-art (SOTA) across multiple datasets (MNIST, CIFAR-10, ImageNet, and Penn Treebank) and model architectures (LeNet-5, AlexNet, ResNet, MobileNet-V2, and LSTM). We further design an energy-efficient hardware prototype for our framework. Compared to the standard floating-point counterpart, our design achieves a reduction of 68, 51, and 75 percent in terms of area, power, and memory capacity, respectively.

Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing a low-complexity check-node update function, greatly improving the reliability of check-to-variable messages. By further incorporating the proposed column degree adaptation strategy, our decoder could offer a 0.4dB performance gain over the existing ones. In addition, this article presents an efficient 5G LDPC decoder architecture. Benefiting the specific structure of 5G LDPC codes, layer merging, split storage method, and selective-shift structure are introduced to facilitate a significant reduction of decoding delay and area consumption. Implementation result on 90-nm CMOS technology demonstrates that the proposed decoder architecture yields an impressive improvement in throughput-to-area ratio, achieving up to 173.3% compared to conventional design.

Pairs trading is a solidly profitable strategy in the algorithmic trading area, and an important step of this strategy is selecting pairs of stocks. Compared with other existing pairs selection approaches, the Engle-Granger cointegration is more stable and reliable. Nowadays, as trading is becoming faster and faster in stock markets all over the world, it is necessary to accelerate the pairs selection process to increase potential profits. However, intensive computations and complicated data flow in the cointegration approach bring challenges to hardware acceleration. In this paper, for the first time, we propose an efficient and hardware-friendly computing scheme to accelerate the Engle-Granger cointegration. Besides, a novel algorithmic strength reduction strategy and approximation methods are used to significantly reduce the complexity of the proposed scheme. Based on the improved algorithm, both FPGA and ASIC accelerators are developed. The implementation results show that our FPGA and ASIC accelerators perform 36× and 207× faster than GPU, respectively. Thus, our design can significantly reduce the latency of the pairs selection process, and make more profit for investors and traders.

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least 2dB reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems.

The supersingular isogeny key encapsulation (SIKE) protocol, as one of the post-quantum protocol candidates, is widely regarded as the best alternative for curve-based cryptography. However, the long latency, caused by the serial large-degree isogeny computation which is dominated by modular multiplications, has made it less competitive than most popular post-quantum candidates. In this paper, we propose a high-speed and low-latency architecture for our recently presented optimized SIKE algorithm. Firstly, we design a new field arithmetic logic unit (FALU) with many algorithmic transformations and architectural optimizations. Especially, for the FALU, an extremely low-latency modular multiplier is devised based on a modified algorithm by fully parallelizing and highly optimizing the small-size multipliers and the reduction submodules. Secondly, we develop a compact control logic and update the instructions based on the benchmark provided in the newest SIKE library, fitting well with our design. Thirdly, an efficient memory access method is proposed by scheduling the input and output of the arithmetic logic unit (ALU) in two identical RAMs, which can significantly reduce the latency. Finally, we code the proposed architectures using the Verilog language and integrate them into the SIKE library. The implementation results on a Xilinx Virtex-7 FPGA show that for SIKEp751, our design only costs 9.3 ms with a frequency of 155.8 MHz, about 2× faster than the state-of-the-art, and achieves the best area efficiency among existing works. Particularly, the modular multiplier merely needs 16 clock cycles, reducing the delay by nearly one order of magnitude with a small factor of increase in hardware resource.

Designing hardware accelerators for convolutional neural networks (CNNs) has recently attracted tremendous attention. Plenty of existing accelerators are built for dense CNNs or structured sparse CNNs. By contrast, unstructured sparse CNNs can achieve higher compression ratio with equivalent accuracy. However, their corresponding hardware implementations generally suffer from load imbalance and conflict access to on-chip buffers, which results in under utilization of processing elements (PEs). To tackle these issues, we propose a hardware/power-efficient and highly flexible architecture to support both unstructured and structured sparse CNNs with various configurations. Firstly, we propose an efficient weight reordering algorithm to preprocess compressed weights and balance the workload of PEs. Secondly, an adaptive on-chip dataflow, namely hybrid parallel (HP) dataflow, is introduced to promote weight reuse. Thirdly, the partial fusion scheme, which was first introduced in one of our prior works, is incorporated as the off-chip dataflow. Benefited from dataflow optimizations, the repetitive data exchanges between on-chip buffers and external memories are significantly reduced. We implement the design on the Intel Arria10 SX660 platform and evaluate with MobileNet-v2, ResNet-50, and ResNet-18 on ImageNet dataset. Compared to existing sparse accelerators on FPGAs, the proposed accelerator can achieve 1.35 ~ 1.81× improvement in power efficiency with the same sparsity. Compared to prior dense accelerators, this accelerator can achieve an improvement of 1.92 ~ 5.84× in DSP efficiency.

As one of the postquantum protocol candidates, the supersingular isogeny key encapsulation (SIKE) protocol delivers promising public and secret key sizes over other candidates. Nevertheless, the considerable computations form the bottleneck and limit its practical applications. The modular multiplication operations occupy a large proportion of the overall computations required by the SIKE protocol. The VLSI implementation of the high-speed modular multiplier remains a big challenge. In this article, we propose three improved modular multiplication algorithms based on an unconventional radix for this protocol, all of which cost about 20% fewer computations than the prior art. Besides, a multiprecision scheme is also introduced for the proposed algorithms to improve the scalability in hardware implementation, resulting in three new algorithms. We then present very efficient high-speed constant-time modular multiplier architectures for the six algorithms. It is shown that these new architectures can be extensively pipelined and highly optimized to obtain high throughput and low latency. The field-programmable gate array (FPGA) implementation results show that all proposed multipliers achieve much higher throughput than previous designs, but the increase in resources is relatively small. In addition, the multipliers without the multiprecision scheme have very low latency, which is very friendly to high-speed applications of the SIKE protocol.

To overcome the memory bottleneck of von-Neuman architecture, various memory-centric computing techniques are emerging to reduce the latency and energy consumption caused by data communication. The great success of artificial intelligence (AI) algorithms, which involve a large number of computations and data movements, has motivated and accelerated the recent researches of in-memory computing (IMC) techniques to significantly reduce or even diminish the accesses of off-chip data, where memory is not only storing data but can also directly output computation results. For example, the multiply-and-accumulate (MAC) operations in deep learning algorithms can be realized by accessing the memory using the input activations. This paper will investigate the recent trends of IMC from techniques (SRAM, flash, RRAM and other types of non-volatile memory) to architecture and to applications, which will serve as a guide to the future advances on computing in-memory (CIM).

The appealing property of low area, low power, flexible precision, and high bit error tolerance has made Stochastic Computing (SC) a promising alternative to conventional binary arithmetic for many computation intensive tasks, e.g., convolutional neural networks (CNNs). However, to relieve the intrinsic fluctuation noise in SC, long bit stream is normally required in SC-based CNN accelerators to achieve satisfactory accuracy, which leads to extortionate latency. Although the bit parallel structure of a SC multiplier has been proposed to reduce latency, the resulting extra overhead still considerably degrade the overall efficiency of SC. In this paper, we optimize both the micro-architecture of SC multiply-and-accumulate (MAC) unit and the overall acceleration scheme of CNN accelerator to favor SC. An optimized and scalable SC-MAC unit, which fully utilizes the property of low-discrepancy bit stream, is proposed with adjustable parameters to reduce the latency with minor area increase. For the overall accelerator, the parallel dimensions of SC-based MAC array are extended to reuse hardware resources and improve throughput, since the judiciously chosen loop unrolling strategy can better benefit SC operations. The proposed CNN accelerator with extended SC-MAC array is synthesized and demonstrated using TSMC 28nm CMOS on several representative CNNs, which gains 2× performance speedup, 2.8× energy savings and 15% area reduction compared to state-of-the-art SC based CNN accelerator.

With the strong capability of modeling time sequence, long short-term memory (LSTM) networks have been widely applied to predicting financial time series. This has attracted tremendous attention in the quantitative trading area. A complete quantitative trading system usually has three tasks, including market timing, stock selection, and portfolio management. In this paper, we present an LSTM-based quantitative trading system and optimize this system from the following two aspects. Firstly, in the process of stock selection, we first introduce the dynamic K-top method in the LSTM-based quantitative trading system to follow the market change. Secondly, concerning portfolio management, we further incorporate the Kelly Criterion to attain an appropriate position ratio. Taking CSI300 constituent stocks as the study example, extensive experiments have been carried out to show the superiority of the proposed method. In comparison with the straight forward LSTM-based trading strategy, the improved LSTM-based trading strategy with the dynamic K-top method and the Kelly Criterion can achieve an increase of 44.97% over ten days in terms of accumulative return. In addition, our novel method can gain a win ratio of 55.95%, a monthly alpha of 0.16, a monthly Sharpe ratio of 2.17, and a monthly Sortino ratio of 2.96 disregarding the transaction costs.

Pairs trading is a classic strategy in the algorithmic trading area and has achieved great success in the stock market. It consists of two stages: pairs selection and trading based on the selected stock pairs. The process of pairs selection is the key to higher returns. Among existing pairs selection methods, pairs trading based on Engle-Granger cointegration has been proven to be superior. However, the cointegration approach is computationally expensive and brings high latency which may greatly affect the returns. In this paper, the Engle-Granger cointegration algorithm is drastically simplified. Meanwhile, a low latency hardware architecture is proposed for the modified algorithm. In the experiment of selecting stocks of length 5000, our hardware design is more than 1290× faster than CPU and 190× faster than GPU. To the best of our knowledge, this is the first work on hardware accelerator for Engle-Granger cointegration in open literature.

Approximate multipliers have recently attracted great attention due to their substantially lower energy consumption and area overhead. But previous approximate multiplier designs are mainly focused on the design of approximate compressors, little attention is paid to the compression strategy of partial product matrix. This paper proposes an optimized universal compression scheme for the compressor-based approximate multiplier. When we apply the new compression scheme to the state-of-the-art compressors, the accuracy of the approximate multiplier is largely increased and fewer exact adders are needed. To prove the efficiency of the new compression strategy, an 8-bit and a 12-bit approximate multipliers are designed using Verilog and synthesized under the TSMC 40-nm CMOS technology. Compared to the state-of-the-art, the experimental results indicate that the mean error distance of 8-bit multiplier decreases by 19.6%, with area and power reduced by 5.38% and 2.38% respectively; 12-bit multiplier has a reduction of 18.1% for mean error distance, with area and power reduced by 6.29% and 3.24% respectively. Moreover, application to image processing is presented, which shows that the proposed approximate multiplier has a better performance.

The Smith-Waterman (S-W) algorithm is widely adopted by the state-of-the-art DNA sequence aligners in next-generation sequencing (NGS). Prevailing read aligners, such as BWA-MEM and Bowtie 2, use the S-W algorithm to implement the seed-and-extend paradigm. In this work, we further extend the functionality of the S-W algorithm to evaluate the similarity between a pair of sequences without going through traceback process, and design a three-level hardware scoring system to compute final result efficiently. The system is made reconfigurable to align pairs of sequences of various length with a restriction of maximum number of errors. Experimental results show that the system can achieve a throughput of 685Mb/s at 69 iterations in the case of 126bp and the accuracy rate of the outputs is over 98% campared with software results. To the best of our knowledge, this is the first hardware implementation for a similarity evaluation system based on the S-W algorithm.

Tabu-list random-penalty gradient descent bit-flipping (TRGDBF) decoder is the state-of-the-art hard-decision low-density parity-check (LDPC) decoder in terms of error-correction performance on binary symmetric channel (BSC). However, the TRGDBF decoder suffers from a long critical path caused by the global maximum-finding operation, limiting the achievable throughput. This brief proposes an information storage bit-flipping (ISBF) decoder to solve this problem. Different from the existing bit-flipping (BF) decoders which adopt serial decoding manner, in the ISBF decoder, by storing the previous decoding information, the global maximum-finding operation can be executed in parallel to other decoding operations, significantly shortening the critical path. Moreover, a nonuniform flipping rule is incorporated to achieve a better decoding performance. We also present an efficient architecture to implement the ISBF decoder. The design example demonstrates that compared to other hard-decision BF decoders, the ISBF decoder could provide both the best decoding performance and throughput on BSC.

Deconvolutional neural network (DeCNN), such as fully convolutional network (FCN) and generative adversarial network (GAN), has shown great potential in various vision tasks. Convolution and deconvolution, the two major operations of DeCNN, both require real-time hardware acceleration. However, some previous designs for deconvolutions require large memory for overlapped results, while others incur computation imbalance and cause resource underutilization. In this article, we propose an efficient method to convert deconvolutions to convolutions, which enables balanced computations to make full use of processing elements. Based on the fast FIR algorithm, a reconfigurable conv-deconv unit (RCU) with low complexity is designed, which can support various types of convolutions and deconvolutions. By exploiting the computing characteristics of RCUs, a computation-balance scheme is developed to eliminate large memory requirements caused by overlapped results. In addition, a fast convolution architecture for deconvolutional network acceleration (F-DNA) is proposed. The dataflow of F-DNA improves the computation efficiency through input data reuse. The architecture is implemented on Xilinx Virtex-UltraScale, for two typical DeCNNs, DCGAN and FSRCNN. Implementation results show that the proposed design outperforms existing works significantly, particularly in terms of computation efficiency and memory requirements.

This article presents hardware implementation for computing arbitrary roots of a single-precision floating-point number. The proposed architecture is based on Generalized Hyperbolic COordinate Rotation Digital Computer (GH CORDIC) algorithm. Benefiting from the wide range of floating-point numbers, our design is able to compute the Nth root (N ≥ 2) of a single-precision floating-point number. After implementation, a series of tests have been carried out, including accuracy, power consumption, performance comparison, and so on. Simulation results indicate that our proposed method is capable of calculating the Nth root of a positive single-precision floating-point number with a relative error of 10-7approximately and promises an error-flatten performance. Synthesized results from a design compiler under TSMC-40-nm CMOS technology show that our design can achieve the highest frequency of 2.38 GHz with the area consumption of 140894.44 μm2and power consumption of 86.9573 mW.

This paper presents an Enhanced Offset Min-Sum (EOMS) decoder for Low-Density Parity-Check (LDPC) codes used in the 5th generation (5G) mobile communications. It is observed that a significant part of Variable Nodes (VNs) in the 5G LDPC codes are with degree-1 and are very sensitive to be erroneous, leading to the fact that the decoding performance is generally reduced. In the EOMS decoding, the core check nodes (CN) and extension CNs are processed with different update rules. A new CN -update criterion is also proposed by making use of the third minimum value. As a result, the offset factors are adaptively selected and the error probability of degree-1 VNs is significantly reduced. Simulation results show that the proposed EOMS decoder offers a much better error-correction performance than the state-of-the-art benchmarks for several 5G LDPC codes with a negligible complexity overhead.

Low-latency and low-power implementations of Convolutional Neural Network (CNN) are highly desired for budget-restricted scenarios. Pruning and Winograd algorithm are two representative approaches to reduce the computation complexity of CNNs. Coupling them is very attractive, but the Winograd transformation removes data sparsity brought by pruning. In this paper, we present a low-latency sparse-Winograd CNN accelerator (LSW-CNN) for pruned Wino-grad CNN models. The ReLU-modified algorithm is employed to solve the zero refilling issue. Our design fully leverages the sparsity in both weights and activations, and thus eliminates all unnecessary computation and cycles. Moreover, a novel fast mask indexing algorithm for sparse data compression is developed. Accumulation buffers are scaled to reduce the latency brought by irregular serial channel merging. On VGG-16, experimental results demonstrate that the latency of LSW-CNN is reduced by 5.1 and 1.7 times, respectively, compared with state-of-the-art dense-Winograd and sparse-Winograd accelerators. Besides, the consumed hardware resource is also significantly reduced.

Polar codes are a great breakthrough in coding theory, which have been standardized for the next generation mobile communication and are promising to improve the reliability of MLC NAND flash. The successive-cancellation (SC) decoding is low-complexity, while its error-correction performance is not satisfactory. The SC flip (SCF) decoding offers a better error-correction performance than the SC decoding while keeps a similar complexity to the SC decoding. To reduce the latency, recently the fast simplified SC (Fast-SSC) decoding is merged with the SCF, resulting in the Fast-SSC-Flip decoding. In this paper, we propose a new Fast-SSC-Flip decoding algorithm for polar codes. A novel decision LLR calculation method and bit-flipping scheme in single-parity-check (SPC) nodes are presented, leading to a better error-correction performance than the prior art. Besides, more types of special nodes in the decoding tree are considered in the proposed algorithm to reduce the decoding latency. Moreover, our algorithm can find the first erroneous bit of an invalid codeword more effectively than the prior algorithm, which can reduce the number of flipping trials and also makes contribution to a lower decoding latency.

In the era of artificial intelligence (AI), deep neural networks (DNNs) have emerged as the most important and powerful AI technique. However, large DNN models are both storage and computation intensive, posing significant challenges for adopting DNNs in resource-constrained scenarios. Thus, model compression becomes a crucial technique to ensure wide deployment of DNNs.

Probabilistic gradient descent bit-flipping (PGDBF) is the state-of-the-art hard-decision algorithm for decoding low-density parity-check (LDPC) codes on binary symmetric channel (BSC). However, there still exists a considerable performance gap between the PGDBF algorithm and soft-decision algorithms, especially in the error-floor region. To bridge this performance gap, a tabu-list aided PGDBF (T-PGDBF) algorithm is proposed in this paper. In the T-PGDBF algorithm, a tabu-list is employed to help the decoding escape from trapping sets, which is the main cause of the error-floor phenomenon. The bits which are flipped in the current iteration will be added to the tabu-list to prevent them being flipped in the next iteration. Simulation results show that the T-PGDBF algorithm offers a significant performance gain when compared to the PGDBF algorithm, which can reach that of soft-decision algorithms. We also present the hardware architecture to implement the T-PGDBF algorithm. Synthesis results show that the improved performance offered by the T-PGDBF algorithm can be obtained with a small hardware overhead.

Due to the intensive computational complexity and various types of convolution, it is a challange to implement different CNN models on a specific hardware. Many previous works focus on data reuse and sparsity exploration to accelerate computation but fail to support various types of convolution efficiently. When dealing with variants of conventional convolution, such as deconvolution or dilated convolution, previous accelerators waste time on padding zeroes and convolving with padded feature maps. In this paper, we propose a unified convolution algorithm to intelligently combine several convolution types together and exploit the sparsity in activations. The padding process can be skipped by the proposed algorithm. Moreover, a unified systolic convolution array (USCA) architecture is developed based on the algorithm. The USCA architecture is implemented with a TSMC 28nm CMOS technology. The implementation results demonstrate that the architecture costs 206k logic gates and 114.7kB on-chip memory. It can reach a peak performance of 374.7GOPs and comsumes 201.1mW at a frequency of 1449MHz. Compared to similar works, USCA architecture achieves 3 × energy efficiency, which is measured by the number of GOPS per watt. Besides, to the best of our knowledge, USCA is the first architecture that can simultaneously support conventional convolution, deconvolution, and dilated convolution in an efficient way.

Generative neural networks have been developing rapidly in the field of deep learning nowadays. Generative models have obtained much popularity in various applications such as image generation, reading comprehension and style transfer. Convolutional (CONV) and deconvolutional (DeCONV) layers are typical components of generative neural networks. The use of traditional convolution accelerators will cause problems of overlapping and resource under-utilization while doing deconvolutions. There is little research on acceleration of deconvolution implementations. In this paper, we propose efficient reconfigurable architecture of generative neural networks. Firstly, the fast reconfigurable unit (FRU) based on cascaded fast FIR algorithm (CFFA) is proposed to support both convolutions and deconvolutions. The problems of overlapping and resource under-utilization are solved. Secondly, the reconfigurable architecture on the basis of FRUs for CONV and DeCONV layers is proposed accordingly. Thirdly, a novel shift scale quantization method is proposed to uniformly quantize CONV and DeCONV layers. Only integer computations are required with the quantization method. Finally, we choose a typical generative neural network and implement it on Xilinx Zynq ZC706. It is estimated that the performance reaches 62.85 GOPS under 330MHz working frequency on Xilinx ZC706. In brief, the proposed design outperforms existing works significantly, particularly surpasses related reconfigurable design by more than 20 times in terms of performance density.

Non-binary low-density parity-check (NB-LDPC) codes exhibit a much better performance than their binary counterparts, especially for moderate codeword length and high-order modulation. However, their decoding algorithms suffer from very high computational complexity. In this paper, a low-complexity algorithm is proposed, named parity-check erased algorithm (PCEA), where an additional parity check bit is added to each symbol of the codeword when encoding and a series of simple operations are performed based on these bits during decoding. As a universal joint coding and decoding algorithm, the PCEA can be combined with arbitrary NB-LDPC encoding schemes and decoding algorithms based on message passing. The proposed algorithm facilitates significant improvement of decoding performance with a small decrease of the code rate. Additionally, it usually has an even better performance than a nearly same-rate code constructed by the original method, and requires much lower decoding complexity due to smaller size of the parity check matrix.

This paper proposes a generalized hyperbolic COordinate Rotation Digital Computer (GH CORDIC) to directly compute logarithms and exponentials with an arbitrary fixed base. In a hardware implementation, it is more efficient than the state of the art which requires both a hyperbolic CORDIC and a constant multiplier. More specifically, we develop the theory of GH CORDIC by adding a new parameter called base to the conventional hyperbolic CORDIC. This new parameter can be used to specify the base with respect to the computation of logarithms and exponentials. As a result, the constant multiplier is no longer needed to convert base e (Euler's number) to other values because the base of GH CORDIC is adjustable. The proposed methodology is first validated using MATLAB with extensive vector matching. Then, example circuits with 16-bit fixed-point data are implemented under the TSMC 40-nm CMOS technology. Hardware experiment shows that at the highest frequency of the state of the art, the proposed methodology saves 27.98% area, 50.69% power consumption, and 6.67% latency when calculating logarithms; it saves 13.09% area, 40.05% power consumption, and 6.67% latency when computing exponentials. Both calculations do not compromise accuracy. Moreover, it can increase 13% maximum frequency and reduce up to 17.65% latency accordingly compared to the state of the art.

In[1], the iterative formulas of generalized hyperbolic CORDIC, i.e.,(21), should read as follows:

In this paper, a new large dither injection technique is proposed for improving linearity in pipelined analog-to-digital converters (ADCs), without losing the dynamic range of the ADCs and deteriorating the corresponding amplifier's linearity. First, analyses of a proper pipelined ADC's architecture are performed for large dither injection. Then, a 9-bit capacitive digital-toanalog converter (DAC) with split architecture is developed to inject the dither ranging from -511/1024 least significant bit (LSB) to 511/1024 LSB of the first stage. To counteract the consumption of the correction range by the capacitive injection dither, the novel 6-bit complementary DACs embedded in the comparator threshold generation circuit are proposed to realize comparator dither injection. In addition, the dither injection amplitude is configurable for investigating different amplitude's effects on the linearity of the ADC. Finally, the proposed dither injection circuit, together with a 16-bit 150 million samples per second (MSPS) ADC, is implemented in a 0.18-μm CMOS technology. The measured results demonstrate the effectiveness of the proposed techniques. The optimum dither is the 9-bit dither, improving not only the spurious free dynamic range (SFDR) of the small signal by at least 13 dB but also that of the large signal by more than 8 dB compared to the case without dither injection. Moreover, dither injection makes the noise floor clean.

Convolutional neural networks (CNNs) are widely used in various intelligent tasks. However, the huge computational complexity of CNNs makes it hard to be implemented in many real-time embedded devices. Various methods have been employed to reduce the model size of CNNs, where the Canonical Polyadic Decomposition (CPD) has shown its capability to reduce both the computational complexity and the storage requirement with negligible accuracy loss. In this paper, an efficient configurable hardware architecture called EadNet is proposed for CPD-CNNs. In detail, to minimize the on-chip memory access, different data reuse patterns are first analyzed. Based on the chosen optimal reuse scheme, a much improved computation flow is also developed for efficiently caching activations. The EadNet is implemented with a TSMC 90nm CMOS technology. The implementation results indicate that EadNet achieves considerable improvements on computation efficiency compared to the state-of-the-art CNN accelerator architectures.

Due to the aggressive technology scaling, the memory reliability has been seriously degraded, which poses a challenge to the widely used low-density parity-check (LDPC) codes. Non-binary LDPC (NB-LDPC) codes present larger coding gain and lower error floor than their binary counterparts in many cases, which show a great potential to be used in the next-generation memories. However, the excessive computational complexity of current NB-LDPC decoding algorithms form a bottleneck and limit their applications. In this paper, a novel algorithm, called dual-threshold-based shrinking based improved trellis-based min-sum algorithm (simply TIT-MSA), is proposed to deal with this problem. The improvements include two steps. The first step is for the check node processing (CNP). Based on the CNP of the simplified min-sum algorithm (SMSA) and that of the trellis-based extended min-sum algorithm (T-EMSA), an improved trellis-based min-sum algorithm (IT-MSA) is developed, which achieves better error performance and lower computational complexity than its origins. The second step is for the whole decoding process. Based on the IT-MSA, the TIT-MSA is proposed, for which two constant thresholds are introduced to remove redundant messages by constructing two subsets of the Galois field. Simulation results show that the error performance of the TIT-MSA is nearly the same as that of the EMSA. Meanwhile, the proposed algorithm can save almost 90% computations compared to the SMSA and T-EMSA.

Turbo product codes (TPCs) are being considered as a competitive forward error correction scheme for ultra high speed network communication beyond 100Gbps [1], [2]. Conventional soft-input soft-output (SISO) decoders for turbo product codes (TPCs) need to exchange extrinsic soft messages between row and column component decoders. However, the extrinsic information increases the difficulty of hardware implementation. First of all, for a two dimensional message memory, row and column component decoders access soft messages in horizontal and vertical directions, respectively, resulting in potential memory access conflict. Secondly, the computation complexity of calculating the soft extrinsic information is very high. Finally, storing the extrinsic information needs additional memory and updating it frequently increas the decoding latency and power consumption. In this paper, we propose a new soft-input hard-output (SIHO) decoding algorithm for TPCs. The proposed SIHO decoding algorithm requires the exchange of only hard information between row and column component decoders, leading to simpler decoder architectures. Moreover, each component decoder of a SIHO TPC decoder does not generate any soft information. In terms of error correction performance, the SIHO decoding algorithm is in between the SISO and the hard-input hard-output decoding algorithm. It is believed that the SIHO decoding algorithm is a good tradeoff between high net coding gain (NCG) and low complexity implementation.

Cloud service for deep learning (DL) has been widely used except for applications involving medical, financial, or other sensitive data due to privacy and security requirements. By employing homomorphic encryption, trained deep convolutional neural networks (CNNs) can be converted to CryptoNets, which is suitable for privacy-preserving DL cloud service. However, the high computation complexity of CryptoNets leads to tremendous implementation challenge. In this paper, to the best of our knowledge, efficient hardware acceleration of CryptoNets is discussed for the first time in open literature. In more detail, without compromise of security and inference accuracy, encryption parameters and modular multiplication algorithm are carefully selected to reduce the computation complexity of polynomial multiplication. Besides, based on the negative wrapped convolution and fast finite impulse filter schemes, an efficient algorithm for convolutions in CryptoNets is developed. Moreover, a dedicated low complexity convolution core architecture for CryptoNets is proposed and implemented with a 90nm CMOS technology. Compared to a well optimized CPU implementation of CryptoNets, this architecture is 11.9× faster while consuming a power of only 537mW.

Long short-term memory (LSTM) and its variants have been widely adopted in processing sequential data. However, the intrinsic large memory requirement and high computational complexity make it hard to be employed in embedded systems. This incurs the need of model compression and dedicated hardware accelerator for LSTM. In this letter, efficient clipped gating and top-k pruning schemes are introduced to convert the dense matrix computations in LSTM into structured sparse-matrix-sparse-vector multiplications. Then, mixed quantization schemes are developed to eliminate most of the multiplications in LSTM. The proposed compression scheme is well suited for efficient hardware implementations. Experimental results show that the model size and the number of matrix operations can be reduced by 32× and 18.5×, respectively, at a cost of less than 1% accuracy loss on a word-level language modeling task.

Many studies were carried out for the construction of low density parity-check (LDPC) codes. They usually focused on introducing the construction methods for good LDPC codes instead of a general method for code optimization. This paper proposes a method with high versatility, called the parallel vector message passing-based edge exchange (PMPE), for optimizing a type of graph-based LDPC codes, without changing the code parameters of mother codes, such as the code length, code rate, and degree distribution. With the approximately nearest codewords searching approach, we find the optimization method can increase the Hamming distance of the LDPC codes. For the quasi-cyclic (QC) LDPC codes, an optimization method, called the parallel vector message passing oriented-to the QC-LDPC codes (QC-PMP), is further suggested, with which the quasi-cyclic characteristics of QC-LDPC codes can remain unchanged in the optimization. To evaluate the performance of the parity-check matrix corresponding to a Tanner graph, a very simple metric, the cycles metric, is introduced to work with the proposed PMPE and QC-PMP algorithms. The experimental results show that the performance of the LDPC codes optimized with the proposed PMPE can be improved significantly at low BER range compared with the mother codes of the random codes, including the regular MacKay code of rate 0.5 and the regular PEG code of rate 0.9. For the case of the regular and irregular QC-LDPC codes with different code lengths and code rates, the optimized LDPC codes with the proposed QC-PMP algorithm significantly outperform the mother codes.

Binary weight convolutional neural networks (BCNNs) can achieve near state-of-the-art classification accuracy and have far less computation complexity compared with traditional CNNs using high-precision weights. Due to their binary weights, BCNNs are well suited for vision-based Internet-of-Things systems being sensitive to power consumption. BCNNs make it possible to achieve very high throughput with moderate power dissipation. In this paper, an energy-efficient architecture for BCNNs is proposed. It fully exploits the binary weights and other hardware-friendly characteristics of BCNNs. A judicious processing schedule is proposed so that off-chip I/O access is minimized and activations are maximally reused. To significantly reduce the critical path delay, we introduce optimized compressor trees and approximate binary multipliers with two novel compensation schemes. The latter is able to save significant hardware resource, and almost no computation accuracy is compromised. Taking advantage of error resiliency of BCNNs, an innovative approximate adder is developed, which significantly reduces the silicon area and data path delay. Thorough error analysis and extensive experimental results on several data sets show that the approximate adders in the data path cause negligible accuracy loss. Moreover, algorithmic transformations for certain layers of BCNNs and a memory-efficient quantization scheme are incorporated to further reduce the energy cost and on-chip storage requirement. Finally, the proposed BCNN hardware architecture is implemented with the SMIC 130-nm technology. The postlayout results demonstrate that our design can achieve an energy efficiency over 2.0TOp/s/W when scaled to 65 nm, which is more than two times better than the prior art.

With better spectral efficiency, multiple-input and multiple-output (MIMO) systems have drawn increasing attentions. Due to its near-optimal performance, K-best algorithm has been widely adopted for MIMO detection. To the best knowledge of the authors, this paper first proposes a joint detection and decoding (JDD) method for MIMO with low-density parity-check (LDPC) codes. By pruning the searching tree of K-best detection with LDPC coding constraint, the proposed JDD scheme benefits from both reduced tree-search complexity and improved performance compared to its uncoded MIMO counterpart. Numerical results of 16-QAM MIMO with (8, 2) LDPC code and 64-QAM MIMO with (18, 6) LDPC code have shown that, the proposed JDD scheme's performance is evidently superior over separated detection and decoding (SDD) scheme. More specifically, for the latter case with 12 antennas, JDD shows nearly 10 dB performance improvement than SDD when BER = 10-3. Hardware architecture and complexity analysis are also given in this paper to demonstrate JDD's advantages.

Energy efficient and high throughput LDPC decoders are highly demanded, especially in the coming 5-th generation (5G) mobile communication era. In this paper, to the best of our knowledge, approximate computing units (ACUs) for the update of soft messages in row layered LDPC decoders are proposed for the first time. Under the TSMC 90nm CMOS technology, the synthesis results demonstrate that for typical LDPC codes employed in industrial standards, the corresponding ACUs achieve significant reduction in critical path delay (CPD), area and energy consumption. Numerical results show that the presented ACUs cause negligible degradation in the error-correction performance.

Video representation is an important and challenging task in the computer vision community. In this paper, we consider the problem of modeling and classifying video sequences of dynamic scenes which could be modeled in a dynamic textures (DTs) framework. At first, we assume that image frames of a moving scene can be modeled as a Markov random process. We propose a sparse coding framework, named joint video dictionary learning (JVDL), to model a video adaptively. By treating the sparse coefficients of image frames over a learned dictionary as the underlying "states", we learn an efficient and robust linear transition matrix between two adjacent frames of sparse events in time series. Hence, a dynamic scene sequence is represented by an appropriate transition matrix associated with a dictionary. In order to ensure the stability of JVDL, we impose several constraints on such transition matrix and dictionary. The developed framework is able to capture the dynamics of a moving scene by exploring both the sparse properties and the temporal correlations of consecutive video frames. Moreover, such learned JVDL parameters can be used for various DT applications, such as DT synthesis and recognition. Experimental results demonstrate the strong competitiveness of the proposed JVDL approach in comparison with the state-of-the-art video representation methods. Especially, it performs significantly better in dealing with DT synthesis and recognition on heavily corrupted data.

Linear feedback shift register (LFSR) has been widely applied in BCH and CRC encoding. In order to increase the system throughput, the parallelization of LFSR is usually needed. Previously, a technique named state-space transformation was presented to reduce the complexity of parallel LFSR architectures. Exhaustive searches are performed to find good transformation matrix candidates. This brief proposes a new technique for construction of the transformation matrix together with a more efficient searching algorithm. The realization results indicate that the proposed architecture outperforms the prior arts, improving the hardware efficiency by around 35% and the corresponding searching algorithm finds the desirable transformation matrix much faster.

The flooding belief propagation (FO-BP) and the soft-cancelation (SCAN) algorithms are the two most popular soft-output BP algorithms for the decoding of capacity-achieving polar codes. The FO-BP algorithm has high throughput at the cost of performance degradation in high signal-to-noise ratio (SNR) region or with large block length. The SCAN algorithm has much better decoding performance while suffering from long decoding latency and low throughput. In this paper, an improved BP algorithm, named reduced complexity soft-cancelation (RCSC) algorithm, is proposed. Compared with the SCAN algorithm, the number of memory entries required by the RCSC algorithm is reduced by more than 50% in general, while achieving comparable or even better (e.g., when block size N = 215) decoding performance. When block size is large (e.g., N ≥ 215), the proposed RCSC algorithm reduces the required memory entries by more than 23% compared with the state-of-the-art FO-BP algorithm. The numerical results show that the error performance improvement of the RCSC algorithm is more significant when the SNR increases. For a different tradeoff, a reduced latency soft-cancelation (RLSC) algorithm is proposed to reduce the decoding latency and increase the throughput of the RCSC algorithm while slightly sacrificing decoding performance. Finally, the optimized VLSI architectures are presented for the RCSC and RLSC algorithms, respectively. The synthesis results demonstrate the efficiency of the proposed algorithms and architectures.

Recurrent neural networks (RNNs) have achieved the state-of-the-art performance on various sequence learning tasks due to their powerful sequence modeling capability. However, RNNs usually require a large number of parameters and high computational complexity. Hence, it is quite challenging to implement complex RNNs on embedded devices with stringent memory and latency requirement. In this paper, we first present a novel hybrid compression method for a widely used RNN variant, long-short term memory (LSTM), to tackle these implementation challenges. By properly using circulant matrices, forward nonlinear function approximation, and efficient quantization schemes with a retrain-based training strategy, the proposed compression method can reduce more than 95% of memory usage with negligible accuracy loss when verified under language modeling and speech recognition tasks. An efficient scalable parallel hardware architecture is then proposed for the compressed LSTM. With an innovative chessboard division method for matrix-vector multiplications, the parallelism of the proposed hardware architecture can be freely chosen under certain latency requirement. Specifically, for the circulant matrix-vector multiplications employed in the compressed LSTM, the circulant matrices are judiciously reorganized to fit in with the chessboard division and minimize the number of memory accesses required for the matrix multiplications. The proposed architecture is modeled using register transfer language (RTL) and synthesized under the TSMC 90-nm CMOS technology. With 518.5-kB on-chip memory, we are able to process a 512×512 compressed LSTM in 1.71 μs, corresponding to 2.46 TOPS on the uncompressed one, at a cost of 30.77-mm2chip area. The implementation results demonstrate that the proposed design can achieve significantly high flexibility and area efficiency, which satisfies many real-time applications on embedded devices. It is worth mentioning that the memory-efficient approach of accelerating LSTM developed in this paper is also applicable to other RNN variants.

Discrete Fourier Transformation (DFT)/Fast Fourier Transformation (FFT) are the widely used techniques in numerous modern signal processing applications. In general, because of their inherent multiplication-intensive characteristics, the hardware implementations of DFT/FFT usually require a large amount of hardware resource, which limits their applications in area-constraint scenarios. To overcome this challenge, this paper, for the first time, proposes area-efficient error-resilient DFT designs using stochastic computing. By leveraging low-complexity stochastic multipliers, two types of stochastic DFT design are presented with significant reduction in overall area. Analysis results show that compared with the conventional design, the proposed two 256-point stochastic DFT designs achieve 76% and 62% reduction in area, respectively. More importantly, these stochastic DFT designs also show much stronger error-resilience, which is very attractive in nanoscale CMOS era.

In recent years stochastic computing (SC) is re-gaining increasing attention for its unique advantages on low hardware cost and strong error resilience that are the key metrics for nanoscale CMOS era. However, the potential deployment of SC in practical applications is impeded by the long latency of sequential bit-stream and large complexity of pseudo random number generator (PRNG). Aiming to mitigate these challenges, this paper exploits the design space for hardware-efficient stochastic computing with a case study on 4-point discrete cosine transformation (DCT). First, an efficient compensation mechanism is proposed to solve the scaling problem of SC system. Then, two approaches, namely Splitting-Shuffling (SS) and PRNG sharing techniques are proposed to reduce the overall area and processing latency, respectively. Analysis results show that, sustaining the same computing accuracy, the joint use of the proposed approaches leads to 44% reduction in area and 49% reduction on latency than conventional SC design, respectively.

The belief propagation (BP) decoding algorithm not only is an alternative to the successive cancelation (SC) decoders of polar codes, but also provides soft outputs that are necessary for joint detection and decoding. The BP decoders with the flooding schedule achieve high throughput with excessive hardware cost especially when the block length is large. The soft-cancelation (SCAN) decoders for polar codes have reduced memory complexity compared to the BP decoders based on the flooding schedule. The simplified SC aided reduced complexity soft-cancelation (S-RCSC) decoders further reduce the computational and memory complexity of the SCAN decoders at the cost of negligible error performance degradation. Both the SCAN and S-RCSC decoders have limited throughput due to their serial decoding schedules. In this paper, we first propose an improved S-RCSC (IS-RCSC) decoding algorithm and then present a high throughput decoder architecture based on our IS-RCSC algorithm. Our IS-RCSC decoding algorithm performs the message passing on a binary tree representation of a polar code. Compared to the S-RCSC decoding algorithm, our IS-RCSC decoding algorithm accelerates the computing of the returned soft messages when certain types of nodes are activated. The corresponding hardware architecture of our IS-RCSC decoder is also proposed. In terms of area efficiency, the hardware implementation results demonstrate that our IS-RCSC decoders are 19% to 43% better than decoders in the literature.

A novel modification is introduced in this paper for the belief propagation decoder of polar codes, wherein adjacent two processing stages are efficiently combined together to speed up decoding. Corresponding path based belief estimation method is presented in detail. The proposed decoder halves the number of stages of the conventional decoder and thus can significantly reduce the decoding latency and lower message memory requirement.

Among various discrete transforms, discrete Fourier transformation (DFT) is the most important technique that performs Fourier analysis in various practical applications, such as digital signal processing, wireless communications, to name a few. Due to its ultra-high computing complexity as O(N2), in practice the N-point DFT is usually performed in the form of fast Fourier transformation (FFT) with complexity as O(NlogN). Despite this significant reduction in computing complexity, the hardware cost of the multiplication-intensive N-point FFT is still very prohibitive; especially for many large-scale applications that requires large N.

Storing multiple bits in a flash memory cell is a primary technique to linearly increase flash memory capacity, but memory endurance is tremendously sacrificed. This paper presents a multilevel fault tolerance technique for MLC flash memories. The main idea is to explore multi-level forward error correction (FEC) for multiple bits in a flash cell. The associated practical implementation issues are well addressed in this paper. Compared to the conventional error protection methods for flash memory, the proposed multi-level FEC approach can obtain much larger system coding gain using the same amount of redundant bits. As a result, the proposed technique reduces power consumption considerably compared to the conventional methods since the required throughout of LDPC codec is drastically reduced. It can also increase flash memory endurance as it can allocate more redundancy to LDPC code while maintaining overall redundancy ratio.

The recently proposed single block-row quasi-cyclic low-density parity-check (QC-LDPC) codes are favorable for high-speed applications. However, conventional decoder design methods are not suitable for this kind of codes. To tackle this issue, this paper aims at designing efficient column-layered single block-row QC-LDPC decoder architecture without affecting the decoding performance. Moreover, the simplified version which only requires single minimum value is also proposed for further hardware reduction. Results show that, for the rate-0.9006 (1640, 1477) single block-row QC-LDPC code, the proposed two designs achieves significant advantages in both hardware and latency over their row-layered counterpart.

As an extension of binary low-density parity-check (LDPC) codes, non-binary LDPC (NB-LDPC) codes show significantly better performance when the code length is moderate or small. Recently, enhanced iterative hard reliability based (EIHRB) decoding algorithm is proposed to reduce the computation complexity. However, the EIHRB algorithm suffers a lot from significant performance degradation when the column weight is small. In this paper, a symbol reliability based (SRB) decoding algorithm, which also performs well when the column weight is low, is proposed for NB-LDPC decoding to improve the decoding performance. With the same maximum iteration number, around 0.38 dB extra coding gain is achieved. Furthermore, the corresponding efficient decoder architecture is proposed. Comparison results have shown that the proposed SRB algorithm can not only achieve good coding gain, but the cost for hardware implementation is reasonable.

Non-binary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance when the code length is moderate. Previously, forward-backward schemes are used to implement check node processing, which need large amount of memory. In this paper, a novel approach-TCL-EMS is proposed for NB-LDPC decoding. Compared to original EMS decoding algorithm, the memory efficiency is improved and the average number of iterations is reduced significantly. Also, the overall decoder architecture is proposed.

Low-density parity-check (LDPC) codes constructed over the Galois field GF(q) (q>;2), which are also called non-binary LDPC codes, are an extension of binary LDPC codes with significantly better performance. In this paper, an efficient column-layered decoding algorithm, which can reduce the message memory as well as the average number of iterations dramatically, is proposed for min-max decoding. In addition, a non-uniform quantization scheme is developed for reducing the word length while achieving similar performances compared to a conventional quantization scheme. Meanwhile, the corresponding decoder architecture is also proposed.

High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. We propose a pre-computation architecture incorporated with T-algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.

Reed-Solomon (RS) codes are widely used as forward correction codes (FEC) in digital communication and storage systems. Correcting random errors of RS codes have been extensively studied in both academia and industry. However, for burst-error correction, the research is still quite limited due to its ultra high computation complexity. In this brief, starting from a recent theoretical work, a low-complexity reformulated inversionless burst-error correcting (RiBC) algorithm is developed for practical applications. Then, based on the proposed algorithm, a unified VLSI architecture that is capable of correcting burst errors, as well as random errors and erasures, is firstly presented for multi-mode decoding requirements. This new architecture is denoted as unified hybrid decoding (UHD) architecture. It will be shown that, being the first RS decoder owning enhanced burst-error correcting capability, it can achieve significantly improved error correcting capability than traditional hard-decision decoding (HDD) design.

Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13 µm VLSI implementation technology. It is shown that a decoding throughput of nearly 4 Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.

This paper presents a low-power decoder design approach for generic quasi-cyclic low-density parity-check (QC-LDPC) codes based on the layered min-sum decoding algorithm. To reduce the energy consumption, a novel message length-shortening scheme is explored. The check node processing unit (CNU) is accordingly optimized using bit-serial architecture. This low cost design scheme can greatly lower the power consumption while maintaining the necessary throughput required by mobile applications. We further demonstrate the benefits of the proposed techniques by applying the new architecture to the QC-LDPC code in CMMB standard.

This paper presents a memory-reduced VLSI architecture for the decoding of double-binary convolutional Turbo code (DB CTC) using maximum a posteriori probability (MAP) algorithm. For such kind of soft-in soft-out (SISO) decoding, the branch metrics (BMs) γ become the dominant factor in determining the overall required memory size inside the SISO decoder. We propose to decompose each BM into a information metric and a parity metric, which leads to 50% reduction of the memory size for BMs. We further modify the MAP algorithm based on the new formulation of BMs. The new MAP algorithm reveals that: 1) the partitioning of BMs does not introduce any computational overhead when the MAP algorithm is modified; 2) the extrinsic metrics are independent from a posteriori log-likelihood ration, which is attractive for low-power SISO decoder design.

In this paper, we present a layered decoding algorithm for non-binary LDPC codes. Differing from the flooding message-passing schedule in conventional designs, the proposed scheme updates check node messages in serial. Furthermore, since fully serial decoding will lead to long latency, the locally-parallel globally-serial schedule is adopted. Basically the check nodes can be divided into several groups, i.e. layers. The layers are processed one by one while the check nodes in each layer are processed in parallel. Simulation results show that the proposed algorithm not only brings some improvement in error correcting performance but also gives some advantage in VLSI implementation of efficient partially parallel decoders.

This paper presents an area-efficient LDPC decoder architecture for the China multimedia mobile broadcasting (CMMB) standard. Several techniques are adopted to reduce memory size, including the min-sum algorithm (MSA), optimal bit-width quantization of the iterative messages and reduced complexity for the interconnect network. The decoder for the rate-1/2 9216-bit code is implemented using the 90 nm 1.0 V CMOS technology. It achieves the decoding throughput of 48 Mbps at 5 iterations when operating at 60 MHz and the power dissipation is only 34 mW.

Viterbi decoder (VD) is widely used in modern communication systems. For low power applications, trace-back approach (TBA) is usually employed for the survivor memory unit (SMU) of VD. However, TBA suffers from long latency and low throughput. Employing multiple memory banks can resolve the throughput issue on a great extent. In this paper, we present efficient schemes to improve the latency issue of conventional TBA by exploiting pre-trace-back method. In the meantime, we adopt buffer-based TBA method to reduce memory access times, thus reduce power assumption significantly. Simulation results show that the proposed decoding schemes cause either zero or negligible performance loss.

This paper presents an efficient decoder design for the LDPC codes in IEEE 802.15 standard. This decoder features by high parallel level, low message memory requirement and code rate flexibility. By processing 72 columns and 72 rows in parallel, it can reach a throughput of 2.8 Gbps to fulfill the standard requirement. Furthermore, the decoder supports three different code rates by employing flexible check node processor units.

With the extensive applications in high-speed communication systems, the current high-throughput Reed-Solomon decoders are required to achieve the target data rates from 10 Gb/s to 100 Gb/s with low hardware complexity. In this paper, pipeline interleaving inversionless Berlekamp-Massey (PI-iBM) algorithm and pipeline interleaving reformulated inversionless Berlekamp-Massey (PI-RiBM) algorithms for decoding Reed-Solomon codes are presented. Based on these two new algorithms PI-iBM and PI-RiBM Reed-Solomon decoders targeted at 10-100 Gb/s applications are developed. Compared with previously published works, the proposed designs can achieve very high throughput with relatively low hardware complexity. Thus they are well suited for modern high data rate communication systems.

This paper presents a high-throughput GCM VLSI architecture fully compliant to IEEE 802.1ae applications, which can be operated in all modes specified in the standard. Unlike previous works, with the modified parallel GHASH module, the design implements encryption efficiently without knowing the total number of data blocks in advance. Furthermore, a fully subpipelined version of loop-free key expansion architecture is employed to support constant key changes in each clock cycle. An encryptor design example with 2-parallel modified GHASH module is implemented and fabricated in Fujitsu 0.13 mum 1.2 V 1P8M CMOS technology. The ASIC implementation results demonstrate that the maximum operating frequency can reach 764.5 MHz and our design can obtain 97.9 Gb/s throughput with 547 k gates.

This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90 nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2 Gbps at 10 iterations. The operating frequency is 950 MHz after synthesis and the chip area is 2.9 mm2.

This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. The computation core is further optimized to reduce the computation delay. It is estimated that 4.7 Gb/s decoding throughput can be achieved at 15 iterations using the current technology.

Low-density parity-check (LDPC) code, a very promising near-optimal error correction code (ECC), is being widely considered in next generation industry standards. The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namelyshift-LDPCcodes. With girth optimization, this kind of codes can perform as well as computer generated random codes. More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds. In addition, more than 50% of message memory can be generally saved over conventional partially parallel decoder architectures. We demonstrate the benefits of the proposed techniques with an application-specific integrated circuit (ASIC) design (in 0.18-mum CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15 iterations.

Recently developed algebraic soft-decision (ASD) decoding of Reed-Solomon (RS) codes have attracted much interest due to the fact that they can achieve significant coding gain with polynomial complexity. One major step of ASD decoding is the interpolation. Available interpolation algorithms can only add interpolation points or increase interpolation multiplicities. However, backward interpolation, which eliminates interpolation points or reduces interpolation multiplicities, is indispensable to enable the reusing of interpolation results in the following two scenarios: 1) interpolation needs to be carried out on multiple test vectors, which share common entries and 2) iterative ASD decoding where interpolation points have decreasing multiplicities. Examples for these cases are the low-complexity chase (LCC) decoding and bit-level generalized minimum distance (BGMD) decoding. With lower complexity, these algorithms can achieve similar or higher coding gain than other practical ASD algorithms. In this paper, we propose novel backward interpolation schemes and corresponding efficient implementation architectures for LCC and BGMD decoding through constructing equivalent GrOumlbner bases. The proposed architectures share computational units with forward interpolation architectures. Hence, the area overhead for incorporating the backward interpolation is very small. Substantial area saving or speedup can be achieved by using the backward interpolation. When the proposed architecture is applied to the LCC decoding of a (255, 239) RS code with eta = 3, the area is reduced to 39% of those required by prior architectures. In terms of speed/area ratio, the proposed architecture is 48% more efficient than the best available architecture. For the BGMD decoding of the same code, the proposed architecture can achieve around 20% higher efficiency.

In this paper, we propose an extended layered decoding approach for low density parity check (LDPC) codes. Compared to conventional layered decoding algorithms, the proposed approach has no constraint in the column weight of each layer. Hence, it enables more flexibility in high-throughput LDPC decoder design with layered decoding. Simulations on structured and random LDPC codes show that the proposed decoding method achieves significantly faster convergence and slightly better error correction performance than the conventional two phase massage passing sum-product algorithm. We also propose an efficient highly parallel decoder architecture for generic quasi-cyclic LDPC codes to facilitate the practical application of the proposed decoding scheme.

Reed-Solomon (RS) codes are one of the most extensively used error control codes in digital communication and storage systems. Recently, significant advancements have been made on algebraic soft-decision decoding (ASD) of RS codes. These algorithms can achieve substantial coding gain with polynomial complexity. One major step of ASD is the interpolation. Various techniques have been proposed to reduce the complexity of this step. Further speedup of this step is limited by the inherent serial nature of the interpolation algorithm. In this paper, taking the bit-level generalized minimum distance (BGMD) ASD as an example, we propose a novel technique to combine the computations from multiple interpolation iterations. Compared to the single interpolation iteration architecture for a (255, 239) RS code, the combined architecture can achieve 2.7 times throughput with only 2% area overhead in high signal-to-noise ratio scenarios.

This paper presents an efficient algorithm for noncoherent demodulation of Gaussian frequency shift keying (GFSK) signals when the receiver is operating in a decision-feedback mode to aid the current symbol demodulation based on the previous decision bits. Enlightened by the data-aided noncoherent demodulation of DPSK signal, the maximum likelihood (ML) noncoherent receiver for GFSK signals is derived. The proposed algorithm adopts a recursive structure that significantly reduces the computational cost compared with the standard ML methods. The simulation results show that the proposed method achieves comparable bit-error-rate (BER) performance with the matched filter band (MFB) receiver using an observation period of 7 bits, but with two orders of magnitude lower computation complexity.

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can provide substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the Low-Complexity Chase (LCC) decoding can achieve similar or higher coding gain. Interpolation is a major step in ASD. Since the maximum multiplicity of the interpolation point is only one in LCC, the interpolation over each point has low complexity. However, 2ηtest vectors are involved in the LCC, and the interpolation needs to be carried out on each of them. In order to reduce the computational complexity of the overall interpolation, intermediate results can be stored and shared. Nevertheless, the storage requires large memory, which accounts for a significant portion of the overall hardware requirement of the interpolator. In this paper, we propose a novel interpolation procedure, in which the 2ηtest vectors are mapped to the vertices of a dimension-η hypercube and the vectors mapped to adjacent vertices have only one different entry. In addition, a backward interpolation is proposed to support the traversal from one vertex to its neighbors. Traveling through the entire hypercube, the interpolation over each test vector can be done one after another and the memory requirement is reduced by a factor of 2η-1. Efficient architectures are also developed for the proposed interpolation procedure. With about the same latency and the same number of gates as in prior efforts, our architecture can reduce the memory size to 25% and the number of registers to 57% for a (255, 239) RS code with η = 3. The saving further increases with η.

A practical low-complexity decoding of low-density parity-check codes is studied. A fast decoding scheme for weighted bit-flipping (WBF) based algorithms is first proposed. Then, an optimised 2 bit decoding scheme and its VLSI architecture are presented. It is shown that the new approach has significantly better decoding performance while having comparable hardware complexity compared with WBF-based algorithms.

Algebraic soft-decision decoding is a recent break-through in decoding of Reed-Solomon codes and significant decoding gain can be achieved over conventional hard-decision decoding. Bivariate polynomial factorization is an important step of the new decoding algorithm and contributes to a significant portion of the overall decoding latency. In this paper, a novel architecture based on direct root computation is proposed to greatly reduce the factorization latency. Direct root computation is feasible because in most practical applications of algebraic soft-decision decoding of RS codes, sufficient decoding gain can be achieved with a relatively low interpolation cost, which results in bivariate polynomial of small Y-degree. Compared with existing works, not only does our new architecture have a significantly smaller worst-case decoding latency, but it is also more area efficient.

This paper presents an FPGA implementation of a high-speed interpolation processor for algebraic soft-decision decoding of Reed-Solomon codes. In the design, pipelining and parallel processing techniques are exploited to increase the decoding throughput. In addition, different parts of the interpolation processor are properly scheduled to achieve maximum overlap in processing time for the computations occurring at adjacent iterations. Synthesis results show that the FPGA implementation of the interpolation architecture can achieve a throughput of 149Mbps, which is multiple times higher than conventional design.

In this paper, we propose an efficient message passing architecture for permutation matrices based LDPC code decoders. Min-sum algorithm is reformulated to facilitate significant reduction of routing complexity and memory usage. For a (2048, 1723) (6, 32) LDPC code with 4-bit quantization, 54% outgoing wires per variable node unit and 90% outgoing wires per check node unit can be saved. To further reduce hardware complexity, an optimized nonuniform quantization scheme using only 3 bits to represent each message has been investigated. The simulation result shows that it has only 0.25dB performance loss from the floating-point SPA

Algebraic soft-decision decoding (Koetter and Vardy, 2003) is a recent breakthrough in decoding of Reed-Solomon codes and it achieves significant decoding gain over conventional hard-decision decoding. In the bivariate polynomial factorization step of the new decoding algorithm, solving polynomial equations is required and it may contribute to a significant portion of the overall decoding latency. This paper presents a low-latency direct root computation architecture, which should lead to a factorization architecture that is of lower latency and more area efficient

Bivariate polynomial factorization is an important stage of algebraic soft-decision decoding of Reed-Solomon (RS) codes and contributes to a significant portion of the overall decoding latency. With the exhaustive search-based root computation method, factorization latency is dominated by the root computation step, especially for RS codes defined over very large finite fields. The root-order prediction method proposed by Zhang and Parhi only improves average latency, but does not have any effect on the worst-case latency of the factorization procedure. Thus, neither approach is well-suited for delay-sensitive applications. In this paper, a novel architecture based on direct root computation is proposed to greatly reduce the factorization latency. Direct root computation is feasible because in most practical applications of algebraic soft-decision decoding of RS codes, enough decoding gain can be achieved with a relatively low interpolation cost, which results in a bivariate polynomial with low Y-degree. Compared with existing works, not only does the new architecture have a significantly smaller worst-case decoding latency, but it is also more area efficient since the corresponding hardware for routing polynomial coefficients is eliminated.

The maximum a posterior probability (MAP) algorithm has been widely used in Turbo decoding for its outstanding performance. However, it is very challenging to design high-speed MAP decoders because of inherent recursive computations. This paper presents two novel high-speed recursion architectures for MAP-based Turbo decoders. Algorithmic transformation, approximation, and architectural optimization are incorporated in the proposed designs to reduce the critical path. Simulations show that neither of the proposed designs has observable decoding performance loss compared to the true MAP algorithm when applied in Turbo decoding. Synthesis results show that the proposed Radix-2 recursion architecture can achieve comparable processing speed to that of the state-of-the-art recursion (Radix-4) architecture with significantly lower complexity while the proposed Radix-4 architecture is 32% faster than the best existing design

This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations

This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems

This paper presents a systematic study of early stopping criteria for Turbo decoding. First, statistical analysis is carried out on numerous hard/ soft variables that may be used in an early stopping criterion. Desirable variables are suggested based on their statistical properties. Simulation results show that any stopping criteria based on a single variable will have BER/FER performance loss. Two criteria, each of which uses two variables, are recommended in this paper and neither of them will result in any performance loss. It is also shown in this paper that the thresholds for these variables should be set to be proportional to the logarithm of the block size instead of being proportional to the block size.

This paper presents a low-complexity, high-speed VLSI decoder architecture and its FPGA implementation for Euclidian geometry (EG) based quasi-cyclic (QC) low-density parity-check (LDPC) codes. In the design, various optimizations are employed to increase the clock speed. More parallelism is enabled for the partially parallel decoding architecture through the introduction of small hardware overhead. An efficient non-uniform quantization scheme is proposed to reduce the size of soft message memories without sacrificing the decoding performance. Synthesis results show that the proposed decoder for a (8176, 7156) EG-LDPC code can achieve a maximum (information) decoding throughput over 170 Mbps on Xilinx Virtex II FPGA when performing 15 iterations.

In this paper, an area efficient partially parallel decoder architecture suited for (modified) min-sum decoding algorithm for general high rate quasi-cyclic low-density parity-check (QC-LDPC) codes is proposed. To reduce the hardware complexity for parallel processing, an efficient data scheduling unit is presented. The optimized partially parallel decoder architecture can linearly increase the decoding throughput with small hardware overhead. Typically, over 30% of memory can be saved with the architecture presented in this paper. Consequently, the proposed approach facilitates the applications of LDPC codes in area/power sensitive high speed communication systems.

Multiple-input multiple-output (MIMO) technique is a key enabling technology for today's high-rate wireless communications. The sphere decoding algorithm (SDA) has been used for maximum likelihood (ML) detection in MIMO systems. However, it suffers from variable computation complexity and non-fixed throughput. Therefore, the k-best sphere decoding algorithm is proposed for MIMO detections for its less complexity and fixed throughput. The disadvantage for k-best SDA is that it has performance loss due to the reason that ML detection is not guaranteed. In this paper, we propose some improved k-best sphere decoding algorithms which improve the MIMO detection performance. Simulation results show that by applying sorted QR decomposition for the channel matrix, and/or introducing dynamic K values for different layers, our improved algorithms can achieve 1-2 dB detection performance gain for 4 /spl times/ 4 64QAM MIMO systems over the traditional k-best SDA without introducing extra computational complexity.

The most computationally demanding step in soft-decision decoding of RS codes is bivariate polynomial interpolation. The reencoding and coordinate transformation based technique can significantly reduce the computation complexity of the original interpolation problem, thus making the algebraic soft-decision decoder practically feasible. In this paper, an implementation of the reencoding and coordinate transformation procedure is presented. The novelties of our design include a fast algorithm to determine the reencoding points, an area efficient erasure-only RS decoding architecture, and an overlapped scheduling of the various procedures required for the reencoding process to reduce the overall latency. The synthesis result shows that the proposed design is sufficiently fast for any existing or developing interpolation architecture.

Algebraic soft-decision decoding of Reed-Solomon (RS) codes delivers promising coding gains over conventional hard-decision decoding. The most computationally demanding step in the soft-decision decoding is bivariate polynomial interpolation. In this paper, we present a very efficient high speed interpolation architecture based on hybrid data representation. It is shown that the proposed architecture is inherently scalable and can be extensively pipelined to achieve very high clock speed. By further incorporating the maximum overlapping for computations at adjacent iterations, the proposed architecture demonstrates significant advantages over conventional designs. It is estimated that over 1 Gbps data rate can be achieved using the presented work with moderate complexity.

Algebraic soft-decision decoding of Reed-Solomon (RS) codes delivers promising coding gains over conventional hard-decision decoding. The most computationally demanding step in soft-decision decoding of RS codes is bivariate polynomial interpolation. In this paper, we present a hybrid data format-based interpolation architecture that is well suited for high-speed implementation of the soft-decision decoders. It will be shown that this architecture is highly scalable and can be extensively pipelined. It also enables maximum overlap in time for computations at adjacent iterations. It is estimated that the proposed architecture can achieve significantly higher throughput than conventional designs with equivalent or lower hardware complexity

This paper exploits the similarity between the two stages of belief propagation decoding algorithm for low density parity check codes to derive an area efficient design that re-maps the check node functional units and variable node functional units into the same hardware. Consequently, the novel approach could reduce the logic core size by approximately 21% without any performance degradation. In addition, the proposed approach improves the hardware utilization efficiency as well.

Protecting short data frames by turbo coding is a challenging task because of the small interleaver size and the need for transmission efficiency. In this letter, turbo-decoding-metrics aided short cyclic redundancy check codes are applied to novel tailbiting encoded trellis codes with a twofold purpose: to stop the iterative decoding processes to achieve low-power design and to reduce fractional coding-rate loss. Significant coding gains can be achieved by actually increasing the transmission rate with a negligible increase in power consumption. Performance improvement is demonstrated over additive white Gaussian noise channels. The savings is up to 21.4% for the transmission throughput and 21.5% for the energy consumption of the turbo decoder when frame size 49 is used.

A practical turbo decoder is usually implemented with a serial decoding architecture for low complexity, where the extrinsic information symbols are stored in the so-called interleaver memory for the next decoding. Either a dual-port (or two ping-pong memories) or a single-port memory can be employed for this memory. The first approach achieves twice the throughput as the second one while spending approximately twice the hardware on the interleaver memory. In this work, two novel architectures are proposed for the interleaver memory design. Both proposed architectures work for any type of random interleavers. Compared with the traditional single-port approach, twice the throughput can be obtained with less than 1% area overhead when applied in third generation CDMA systems. On the other hand, more than 25% area of an entire turbo decoder can be saved compared with the traditional dual-port solution.

Two efficient approaches are proposed to improve the performance of soft-output Viterbi (1998) algorithm (SOVA)-based turbo decoders. In the first approach, an easily obtainable variable and a simple mapping function are used to compute a target scaling factor to normalize the extrinsic information output from turbo decoders. An extra coding gain of 0.5 dB can be obtained with additive white Gaussian noise channels. This approach does not introduce extra latency and the hardware overhead is negligible. In the second approach, an adaptive upper bound based on the channel reliability is set for computing the metric difference between competing paths. By combining the two approaches, we show that the new SOVA-based turbo decoders can approach maximum a posteriori probability (MAP)-based turbo decoders within 0.1 dB when the target bit-error rate (BER) is moderately low (e.g., BER<10/sup -4/ for 1/2 rate codes). Following this, practical implementation issues are discussed and finite precision simulation results are provided. An area-efficient parallel decoding architecture is presented in this paper as an effective approach to design high-throughput turbo/SOVA decoders. With the efficient parallel architecture, multiple times throughput of a conventional serial decoder can be obtained by increasing the overall hardware by a small percentage. To resolve the problem of multiple memory accesses per cycle for the efficient parallel architecture, a novel two-level hierarchical interleaver architecture is proposed. Simulation results show that the proposed interleaver architecture performs as well as random interleavers, while requiring much less storage of random patterns.

Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.

Protecting short frames using turbo coding is a challenging task because of the small interleave size and the need for transmission efficiency. We explore possible trade-off between power consumption (estimated by the average number of iterations) and performance of turbo decoders when short frame turbo codes are used. Three encoding/decoding schemes are proposed to improve performance of turbo decoder in terms of frame/bit error rate, and to increase the data transmission efficiency whether ARQ protocols are performed or not. Specifically, turbo decoding metrics aided short CRC codes are applied to terminated trellis codes, tail-biting encoded trellis codes and CRC embedded trellis codes with a two-fold purpose: to stop the iterative decoding processes and to detect decoding errors at the last iteration. We show that significant coding gains can be achieved by actually increasing the coding rate with negligible increase in power consumption. Performance improvement is demonstrated over both AWGN and Rayleigh flat fading channels.

Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes introduce no performance degradation in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented.

Protecting short frames using turbo coding is a challenging problem because of the short frame and the need for efficiency. In this paper, first, a scalable and easily implementable interleaver design is proposed since good random interleavers for long frame turbo codes are not guaranteed to perform well for short frames. Second, an efficient tail-biting encoding/decoding scheme is proposed, which does not sacrifice performance but significantly increases the throughput of the decoding process compared with existing methods. Finally, a novel error detection method, taking advantage a set of decoding metrics (DMs), is developed to reduce the number of cyclic redundancy check (CRC) bits used for error detection. The total savings is up to 12% for the transmission throughput and 21.5% for the energy consumption of the turbo decoder when a frame size of 49 is used.

In this paper, a set of variables which can be easily computed in the course of iterative decoding of turbo decoders called decoding metrics (DMs) are introduced. According to the measured DMs after each iteration, a lot of information other than signal-to-noise ratio (SNR) in the received bits, such as how good/bad the current block is and how close the current iteration of decoding is to convergence, can be obtained. Detailed discussions are provided regarding why these variables are chosen. Based on the measured DMs after the first iteration, an approximate SNR-related variable L/sub c/ can be obtained for MAP-based turbo decoders. Simulation results show that there is almost no performance degradation if approximated L/sub c/ values are used instead of exact values. It is also shown that adaptive decoding using DMs is more efficient than existing methods both in terms of hardware and latency. Other applications of DMs are pointed out at last.

In this paper, we propose two VLSI applicable approaches to improving performance of soft-output Viterbi algorithm (SOVA)-based turbo decoders. In the first approach, a pseudo-median filter is employed to modify the soft outputs of each SOVA-based constituent decoder. Compared with conventional SOVA-based turbo decoders, an extra coding gain of 0.2 dB can be achieved for a wide range of target bit-error-rate (BER). In the second approach, an easily obtainable variable and a simple mapping function are used to avoid the complex computation of the scaling factor for extrinsic information in SOVA-based turbo decoders. An extra coding gain of 0.3 to 0.5 dB can be obtained in general. This approach does not require signal-to-noise ratio (SNR) related information while the original method does. The hardware overhead and the extra latency for both approaches are negligible.