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VLDB 2026 Research / reviewers in the wild / expert

Yoshi Sugiyama

dblp:67/5388 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 66% Parallel and multicore computing · 34%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.021987
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
A new routing algorithm and its hardware implementation · DAC 1986
Electronic design automation › physical design
routing		 0.021987
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
A new routing algorithm and its hardware implementation · DAC 1986
Electronic design automation › physical design › routing
steiner tree construction		 0.011987
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Parallel and multicore computing
array processor		 0.011986
Pseudo MIMD Array Processor - AAP2 · ISCA 1986
Parallel and multicore computing › parallel architecture
SIMD/MIMD execution		 0.011986
Pseudo MIMD Array Processor - AAP2 · ISCA 1986
Parallel and multicore computing › parallel computing
parallel implementation		 0.011987
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987
Parallel and multicore computing
parallel algorithms		 0.011986
A new routing algorithm and its hardware implementation · DAC 1986
Parallel and multicore computing
pipelined processing		 0.011986
Pseudo MIMD Array Processor - AAP2 · ISCA 1986
Electronic design automation › physical design › routing
steiner tree		 0.011986
A new routing algorithm and its hardware implementation · DAC 1986

Methods — techniques the papers use, named apart from their topics

parallel rip-up and reroute · 0.0parallel array processor · 0.0lee's maze algorithm · 0.0array processor · 0.0LSI integration · 0.0
YearPublicationVenuePosition
1987 A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor
abstract
A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of the parallel algorithm are the control of the path quality and the finding of a quasi-minimum Steiner tree. Both Lee's maze algorithm and the proposed algorithm are implemented on an AAP-1 two-dimensional array processor, and the performance is compared to that of software programming on a general-purpose computer. It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid.
Takumi Watanabe, Hitoshi Kitazawa, Yoshi Sugiyama
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
1986 A new routing algorithm and its hardware implementation
abstract
Presented is a new parallel processing wire routing algorithm that can control path quality in two point connections and find a quasi-minimum Steiner tree for multi-point connections. A parallel rip-up technique for finding a candidate path which blocks an unconnected net is also presented. These routing algorithms are implemented on a two-dimensional array processor, the AAP-1. It is experimentally shown that the average AAP-1 execution time per net using the routing algorithm is 100 msec in a 256X256 grid.
Takumi Watanabe, Yoshi Sugiyama
 DAC2
1986 Pseudo MIMD Array Processor - AAP2
abstract
A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications. A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications.
Toshio Kondo, Toshio Tsuchiya, Yoshihiro Kitamura, Yoshi Sugiyama, Takashi Kimura, Takayoshi Nakashima
 ISCA4