Thanks to the probabilistic message passing performed between its component decoders, a turbo decoder is able to provide strong error correction close to the theoretical limit. However, the minimum Hamming distance (dmin) of a turbo code may not be sufficiently large to ensure large asymptotic gains at very low error rates (the so-called flattening effect). Increasing the dminof a turbo code may involve using component encoders with a large number of states, devising more sophisticated internal permutations, or increasing the number of component encoders. This paper addresses the latter option and proposes a modified turbo code in which a fraction of the parity bits are encoded by a rate-1, third encoder. The result is a noticeably increased dmin, which improves turbo decoder performance at low error rates. Performance comparisons with turbo codes and serially concatenated convolutional codes are given.

The design of the turbo code internal permutation is crucial regarding the minimum Hamming distance (MHD) and the related achievable asymptotic gain. After having set down the permutation issues in a synthetic way, this paper presents a generic model which allows us to obtain large MHDs for turbo codes and also offers large possibilities of natural parallelism in the decoder architecture.

A joint effort by several researchers has led to the derivation of a maximum a posteriori decoding algorithm for classical binary turbo codes by the dual method. This algorithm leads to reduced complexity with regard to the classical MAP algorithm for high-rate binary turbo codes. We extend the result to duo-binary turbo codes and, more generally, to any M-binary turbo codes.

Synthesis of systolic arrays, from formal specifications down to a chip, can be done using recurrence equations. The Alpha du Centaur environment that the authors present implements such a design trajectory. Programs, written in Alpha language, are rewritten Ising formal transformations (space-time reindexing, pipelining, control signal generation, etc.), and finally translated into a form suited to conventional VLSI design tools. The authors present the principle of systolic synthesis using Alpha du Centaur, and describe a systolic correlator that has been completely designed following this method.>

The authors present new scheduling techniques for systems of affine recurrence equations. They show that it is possible to extend earlier results on affine scheduling to the case when each variable of the system is scheduled independently of the others by an affine timing-function. This new technique makes it possible to analyze systems of recurrence equations with variables in different index spaces, and multi-step systolic algorithms. This theory applies directly to many problems, such as dynamic programming, LU decomposition, and 2-D convolution, and it avoids in particular preliminary heuristic rewriting of the equations.>

This paper deals with the integration of a VLSI chip dedicated to ray tracing bicubic patches. A recursive subdivision algorithm is embedded in this chip. The recursion stops when the termination conditions are met. A software implementation allowed for the determination of key parameters which influenced the choice of the proposed chip' architecture. Only some modules of the chip are, at the present time, simulated and laid out, the rest is being implemented. A detailed description of the chip' modules is given.

We describe Alpha du Centaur (ADC), a prototype environment for the design of parallel regular algorithms. In ADC, a program is specified using the Alpha language, using system of parameterized linear recurrence equations. The goal of ADC is to make it possible to transform the initial specifications into a parallel algorithm, that is to say, another system of recurrence equations, in which the time and the space index are separated.