Retail robots have increasingly become popular in retail stores, serving as collaborative assistants by completing tedious and repetitive tasks. As key participants in a retail environment, understanding how these robots influence the movements and behaviors of nearby customers can provide valuable insights to improve robot ergonomics. This article examined neuromuscular information changes with and without the presence of a retail robot. Sixteen participants were recruited to perform item picking and sorting tasks in a high-fidelity retail setting. Surface electromyography (EMG) signals were collected from four muscles—biceps brachii, brachioradialis, upper trapezius and erector spinae (ES), to measure muscle activity and EMG-EMG coherence. A global decrease in power spectral density (PSD) was observed across all monitored muscles with the robot's presence, indicating a reduction in overall muscular energy expenditure. The introduction of the retail robot also led to a significant reduction in the peak values and waveform length of the ES muscle. These findings not only highlight the potential of retail robots to enhance the overall shopping experience but also provide crucial insights for enhancing ergonomics during robotic design.

The Ising annealing processor has emerged as a promising approach to accelerate the discovery of the optimal solutions for a wide range of combinatorial optimization problems (COPs), by mapping various COPs into a unified Ising model. However, fixed computational strategies and inflexible architectures make previous designs suffer from a low hardware resource utilization rate when the numbers of the total required and real-time flipped spins vary across different COPs and iteration steps. In this paper, a novel spin scale-aware self-adaptive Ising annealing processing architecture (AIAPA) is proposed to address this problem, with an adaptive computational strategy, a custom instruction set, multi-traffic mode routers, and a fully-pipelined computing array. It can dynamically adapt to the varying scenarios during the Ising annealing process to maximize the performance of limited hardware resources. Its prototype, supporting 65k fully-connected spins, is implemented on an FPGA platform, operates at a clock frequency of 188 MHz. The AIAPA achieves up to a 24.22 times faster annealing speed compared to the state-of-the-art FPGA design on the max-cut optimization problem while maintaining a high convergence accuracy.

Combinatorial optimization problems (COPs) are notoriously difficult to solve for classic Von-Neumann computers, which are ubiquitous in various domains. As a state-of-the-art hardware acceleration scheme for COPs, Ising machines are one of the promising research directions for the next generation of computing, but still suffer from the low solution accuracy and speed due to the high complexity of the fully-connected Ising model. In this work, a novel parallel tempering processing architecture (PTPA) is proposed with the modified parallel tempering algorithm, aimed at reducing search time and improving the solution quality. Several techniques are developed to further reduce hardware overhead and enhance parallelism, including the independent pipelined spin update architecture, approximated probability equations, and compact random number generators. Its prototype is implemented on FPGA with eight replicas, each replica containing 1,024 fully-connected spins and at most 64 concurrent update spins. The proposed design achieves an average cut accuracy of 99.43% within 1ms solution time on various G-set problems. Compared with the CPU-based parallel tempering implementation, it enhances the speed of solving the max-cut problems by 5,160 times.

Combinatorial optimization problems (COPs) are prevalent in various domains and present formidable challenges for modern computers. Searching for the ground state of the Ising model emerges as a promising approach to solve these problems. Recent studies have proposed some annealing processing architectures based on the Ising model, aimed at accelerating the solution of COPs. However, most of them suffer from low solution accuracy and inefficient parallel processing. This article presents a novel parallel tempering processing architecture (PTPA) based on the fully-connected Ising model to address these issues. The proposed modified parallel tempering algorithm supports multi-spin concurrent updates per replica and employs an efficient multi-replica swap scheme, with fast speed and high accuracy. Furthermore, an independent pipelined spin update architecture is designed for each replica, which supports replica scalability while enabling efficient parallel processing. The PTPA prototype is implemented on FPGA with 8 replicas, each with 1,024 fully-connected spins. It supports up to 64 spins for concurrent updates per replica and operates at 200 MHz. Different concurrency strategies are considered to further improve the efficiency of solving COPs. In the test of various G-set problems, PTPA achieves 3.2× faster solution speed along with 0.27% better average cut accuracy compared to a state-of-the-art FPGA-based Ising machine.

The Traveling Salesman Problem (TSP) is one of the most well-known NP-hard combinatorial optimization problems (COPs). Many social production problems can be effectively represented as instances of TSPs. However, solving large-scale TSPs remains a significant challenge for conventional Von Neumann computers. Many studies have proposed annealing processors to address large-scale COPs, but most of them focus on unconstrained problems, such as the Maxcut problem. In this paper, a scalable decoupled-clustering annealng processor (DCAP) for efficiently handling large-scale TSPs is presented. A decoupled hierarchical clustering algorithm is proposed for higher convergence speed and improved scalability. Several techniques have been developed in hardware to minimize area overhead and processing time, including a modified spin connection topology for the Ising model, an area-efficient random threshold generator, a one-step spin update scheme and a dynamic prediction method. The DCAP prototype is implemented on FPGA with an operating frequency of 125MHz. We tested our design on various TSP instances from the TSPLIB. Results show that our design outperforms the CPU- and GPU-based Neuro-Ising scheme by achieving maximum speedups of$780\times $and a 42% improvement in accuracy. With multi-chip interconnection, DCAP is able to handle problems of scale up to 85900 cities.

Combinatorial optimization problems (COPs) find extensive applications in industrial and social scenarios such as transportation and communication. As the size of NP-hard COPs increases, it becomes impossible to obtain the optimal solution using an enumerative method. Recently, Ising model based annealing processors have received increasing attention due to their potential for rapidly converging to the near-optimal solutions after mapping the problem to them. This paper presents a novel annealing processor (AP) with 1024 fully-connected spins based on a modified Ising model annealing algorithm, which is more suitable for hardware implementation compared to conventional simulated annealing (SA) algorithm. The prototype is implemented using FPGA with the operation frequency up to 100MHz. We tested our design on various G-set problems with an average cut accuracy of 99.19% achieved. The proposed design outperforms the conventional CPU-based method by achieving a max speedup of 2204x for G51.

Combinational Optimization Problems (COPs) are prevalent in many different fields. Most of these problems are NP-hard and challenging for computers with conventional Von-Neumann architecture. Ising machines with numerous spins have the potential to solve these problems by emulating the natural annealing process of solid matter. Recent research has explored the hardware implementation of Ising machines to accelerate the convergence process of such problems at room temperature. However, most of them are suffering from low scalability and low parallel processing capability due to the huge hardware cost and high complexity. In this paper, a scalable annealing processing architecture for Ising processor is described to address these issues with a NoC computing paradigm, a distributed storage scheme, and a fully pipelined structure design. The prototype is synthesized using FPGA with the maximum operation frequency of 270MHz, achieving about 32 times faster than conventional simulated annealing method when solving the max-cut problem.

Combinatorial optimization problems are prevalent in many different fields. Most of these problems are NP-hard and challenging for computers with conventional Von-Neumann architecture. Ising machines with a number of spins have the potential to solve these problems by emulating the natural annealing process of solid matter. Recent research has explored some hardware implementation methods of Ising machines to accelerate the convergence process of such problems at room temperature. However, most of them are suffering from low scalability and low parallel processing capability due to the huge hardware cost and high complexity. In this paper, a novel network-on-chip-based annealing processing architecture (NoCAPA) for a large-scale Ising processor is described to address these issues with a NoC computing paradigm, a distributed storage scheme, and a fully pipelined structure design. Several techniques are developed to further increase convergence speed and reduce hardware resource consumption, including a dynamic multithread parallel update algorithm, a router with merge and deflection abilities, and a unique multiply-accumulate operation. The prototype is implemented in FPGA with the maximum operation frequency of 200MHz, achieving up to$120.5\times $faster than conventional simulated annealing method when solving the max-cut problem while supporting high scalability.

Learning of (context-free) grammar rules that are based on alignment between texts of a given collection of sentences has attracted the attention of many researchers. We define and study the alignment profile and formulate fuzzy similarity of alignment profiles for a given collection of sentences. Using the fuzzy-similarity-based profile alignment, we give a methodology to formulate stochastic context-free grammar (CFG) rules. We introduce profile-alignment-based dynamic sentence similarity threshold to formulate the rules of stochastic CFG. The proposed methodology is tested using Child Language Data Exchange System (CHILDES) dataset of sentences. The benefits of our approach are experimentally demonstrated. Since our approach does not make use of any domain knowledge, it is expected to be useful in wide variety of applications requiring model construction.

We introduce a similarity measure, called alignment profile similarity, for the learning of context-free grammar from given language samples. Based on the alignment profile similarity, an alignment learning framework for grammatical inference is proposed. Alignment profile similarity is used to improve alignments, and therefore increase the quality of the rules identified. The experiments show that the proposed methods improve performance in terms of the percentage of correctly generated grammar rules.