Efficient utilization of restrained memory resources is of paramount importance in CPU-FPGA heterogeneous multiprocessor system-on-chip (HMPSoC)-based system design for memory-intensive applications. State-of-the-art high level synthesis (HLS) tools rely on the system programmers to manually determine the data placement within the complex memory hierarchy. Different data placement policies may lead to different system performance, and finding an optimal data placement policy is a nontrivial problem. For instance, we show counter-intuitive results that traditional frequency and locality-based data placement strategy designed for CPU architecture leads to nonoptimal system performance in CPU-FPGA HMPSoCs. In this work, we first propose an automatic data placement framework for field programmable gate array (FPGA) kernels to determine whether each array object should be accessed via the on-chip BRAM, shared CPU L2-cache, or DDR memory to achieve the optimal performance. Moreover, we find that when the CPU kernel and the FPGA kernel are executed in parallel, memory contentions may degrade the performance and the optimal data placement policy designed for the FPGA kernel alone will not achieve the optimal overall system performance. In this article, we proposed to use cache partitioning to alleviate the impact brought by memory contentions. We extend the framework designed for FPGA by adding the cross-layer memory contentions analysis to automatically generate an optimal data placement policy and cache partitioning mechanism for the parallel executing kernels. The proposed data placement framework can be seamlessly integrated with the commercial Vivado HLS. The experimental results on the Zedboard platform show an average$1.5\times $performance speedup for FPGA kernels compared with a greedy-based allocation strategy. When FPGA kernels and CPU kernels are executed in parallel, the FPGA kernel and the CPU kernel have a performance speedup of$1.62\times $and$1.10\times $on average, respectively.

Energy harvesting promises to power billions of Internet of Things devices without being restricted by battery life. Since the energy harvester generally outputs weak and unstable energy, the system may suffer frequent and unpredictable power failures, thus falling into cyclically reboots without forward progress. The task-based intermittent computing system which periodically backs up system states into nonvolatile memory (NVM) is proposed to solve the nonprogress problem, with the nontrivial cost of frequent backups. How to reduce the backup overhead becomes a major research problem for intermittent computing. This article, for the first time, proposes to parallelize state backup and program execution with asynchronous direct memory access (DMA) to hide the backup latency into the program’s execution. But, straightforwardly executing the state backup and the program in parallel may cause an inconsistent system state. In specific, the system state may be modified by the program during backup, and therefore may be backed up incorrectly and further cause the system to deliver an incorrect computation result. We make a deep analysis on the system behavior and observe that, although the system state may be backed up incorrectly, the incorrect backup will be covered by the subsequent correct backups soon as the backup operations are performed frequently. In addition, only a small part of variables among all the program states may cause incorrect computation result. So, in this article, we aggressively allow incorrect backups to occur and propose a backup error detection method and a fault-tolerant backup management to guarantee the correctness of the system’s execution. To augment the parallel backup method, an adaptive execution method is further proposed to reduce the number of backups and balance the ratio between task execution time and backup latency. We design a run-time system to implement the proposed approach, and experimental results conducted on an STM32F7-based platform show that the proposed method can achieve a$2.6\times $average speedup.

This paper proposed a high-radix scalable Montgomery multiplier with the efficient data-path and half latency. By using new algorithm proposed by this paper, it achieves shorter critical path by calculating coefficient qYand qMin parallel. The algorithm can also provide half latency by changing pipeline dataflow through operands dynamic extending during calculation. This design can be used to accept any input precision up to the size of the on-chip memory. An ASIC implementation in 0.25 mun CMOS technology can perform 1024-bit RSA encryption with 390k bps under 180MHz frequency

A DVB-C/ITU J.83-A compliant QAM (Quadrature Amplitude Modulation) demodulator suitable for digital cable TV is proposed, which can support 4~256QAM with variable bit rate up to 80Mbps. It integrates a 10-bit 40MSPS ADC, (204,188) Reed-Solomon decoder as well as a convolutional interleaver. The chip is implemented in SMIC 0.25um CMOS technology with die size of 3.5x3.5 mm2. It features wide carrier offset acquisition range, robust demodulation algorithm and small circuit area.

Abstract Current-mode approach in register file has the great advantage of high operation speed with low power consumption. Under 0.35- m m CMOS technology, we present a 1.85-ns read access, 32 · 32-bit, five-port register file in which a modified current-sense amplifier is used. The delay match circuit and TSPC-FF are also used to improve speed. Energy saving is achieved by current mode and other key ideas. Simulation results show it consumes 640mW at 500MHz 3.3V. It can still work at 2.3V with 350MHz 300mW. I.

This paper studies the steady-state analysis of a system of ODE-AE-CGE arising from simulation of MOS RF autonomous circuits in which the transistor plays as current generator and its current equations could adequately represent the transistor large-signal dynamic behavior. Gauss-Seidel relaxation is applied to decouple the system so that shooting method, which is used to find the periodic steady-state response, can be performed with low-order sensitivity matrix. This simplifies the solution process and results in a fast algorithm. We illustrate the new algorithm with the simulation of a typically voltage-controlled oscillator (VCO), the simulation results show good agreement with those obtained by MEDICI, a device simulator.

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The discrete wavelet transform (DWT) has received considerable attention in the context of image processing due to its temporal and frequency characteristics. A specific VLSI architecture for the forward/inverse DWT is presented. The characteristics of the structure and coefficients are utilized to reduce the circuit area. In addition, the Booth algorithm and balanced pipelines have been adopted which result in a high throughput at 2 outputs per clock and 5 clocks' pipeline latency. This design described and verified by the VHDL is synthesized by the Synopsys synthesizer. The synthesis results show that the gate-level circuit contains 5058 gates and the throughput can reach 110 M points/s when LSI 10 K CMOS technology is used.