The state-of-the-art design practice for complex SoCs employs multiple models of hardware components with different use cases. The cost of building and maintaining those models is high, and verifying the consistency among those models is time consuming. This paper highlights needs and issues of creating these models, and presents emerging approaches for developing solutions to address the issues.

The SystemC language has established itself as a popular choice for both modeling and verification at the system level. A well known deficiency in SystemC is the lack of process control constructs - e.g., suspend-resume, kill, reset - that are necessary in many applications domains. This paper identifies and describes a fundamental set of general purpose SystemC kernel extensions that fulfills this deficiency. Effective application of our language extensions are demonstrated in testbench and abstract hardware modeling scenarios.

This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving to eliminate fragmentation within their design and verification flows by leveraging SystemC transaction level models.

SystemC, users and tool providers are at a crossroads. More and more companies are using SystemC; however EDA companies are hesitant to give a full commitment to SystemC tools, especially at system-level. There are several reasons for this dichotomy. While users seem excited about SystemC for its technical qualities for system-level design, tool providers may not share this excitement because of the current small market for such tools. Are the existing (free) reference implementation and the current small market for system level tools to blame, or are there any technical issues impeding the fast development of SystemC tools? Among the SystemC users from industry and academia there is currently some uncertainty about the future availability of state of the art EDA tools supporting SystemC. This panel brings together industrial SystemC users as well as EDA companies to discuss these issues. The industrial panellists will present the current situation regarding the use of SystemC in industry, its importance (or lack thereof) for system design and future needs for such tools. The tool providers will explain their current position regarding the commitment to SystemC and clarify their future plans for supporting it.

Summary form only given. With the ever increasing growth of size and complexity of digital designs, tools have just kept pace. Design engineers bare the brunt of the problem. To make use of dynamic verification, designers invest as much or more time into their testbenches as they do in the design they are creating. For static or formal verification, large designs with complex state spaces have challenged even the most powerful formal tools. What changes are coming in the design and EDA spaces that will improve this situation? What is the right mix of dynamic and static verification for the future?.

There is tremendous interest in design languages these days - and more particularly, SystemC and SystemVerilog. Sometimes the truth about design languages can be obscured by marketing and the press. This panel is meant to deepen the technical understanding of the DATE audience on the issue of design languages. It contains five technical experts - an academic expert in design languages and SystemC and SystemVerilog in particular; a language expert for each of SystemC and SystemVerilog; and a user expert for these two languages. The language experts have been heavily involved in the specification and evolution of their respective languages. The user experts have been heavily involved in developing use methodologies for these languages within their own design communities, and in applying them to real design problems. The panellists will consider the questions: 1) what are the key capabilities of these languages and what do they offer to users?; 2) which design problems are they best used for? what is their scope?; 3) how has application of these languages to real design problems improved the productivity of designers and the quality of the design results?; and 4) where should the languages develop further capabilities?.