VLDB 2026 Research / reviewers in the wild / expert
Marc L. Corliss
dblp:67/6979
· DBLP profile ↗
6ranked-venue papers
6as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-authorHuman-computer interaction and ubiquitous computing · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 84% Reconfigurable computing and FPGAs · 16% | |
| Software engineering, system software, and programming languages
2 papers |
Program analysis · 82% Compilers and program optimization · 18% | |
| Network and information security
1 paper |
Systems and software security · 100% |
Topics — the 3 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Program analysis › dynamic analysis
dynamic instrumentation |
0.1 | 1 | 2005 | Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE · HPCA 2005 |
Processor architecture and microarchitecture › instruction set architecture
instruction set customization |
0.0 | 1 | 2003 | DISE: A Programmable Macro Engine for Customizing Applications · ISCA 2003 |
Reconfigurable computing and FPGAs
programmable devices |
0.0 | 1 | 2005 | Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE · HPCA 2005 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.1dynamic instruction macro-expansion · 0.1cycle-level simulation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | VIREOS: an integrated, bottom-up, educational operating systems project with FPGA supportabstractIn this paper, we present the VIREOS project, a new operating system designed specifically for the classroom. VIREOS is a simple, Unix-like, operating system, which runs on the Larc educational architecture. A VIREOS/Larc system can either be simulated or run on a pre-configured FPGA. The VIREOS project is well integrated with an introductory computer architecture course using Larc and the assignments are structured in a similar fashion: using a bottom-up approach. We have several resources available on the Web, which help reduce the overhead of adopting VIREOS. Finally, VIREOS has been used in one operating systems course already, and the feedback from students was generally favorable. Marc L. Corliss, Marcela Melara |
SIGCSE | 1 |
| 2008 | Bantam: a customizable, java-based, classroom compilerabstractThis paper introduces the Bantam Java compiler project, a new language and compiler designed specifically for the classroom Bantam Java, the source programming language, is a small subset of the Java language, which is a commonly-used language in introductory programming courses. Because Bantam Java is similar to Java, it leverages the student's existing intuition and the student can automatically apply what they learn in the course directly to Java. The Bantam Java project is also customizable (it supports several tools and targets), which gives instructors flexibility in designing course assignments. Finally, the Bantam Java compiler project includes a free, comprehensive, student manual which can be used in conjunction with any compiler textbook. Marc L. Corliss, E. Christopher Lewis |
SIGCSE | 1 |
| 2005 | Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISEabstractBreakpoints, watchpoints, and conditional variants of both are essential debugging primitives, but their natural implementations often degrade performance significantly. Slowdown arises because the debugger - the tool implementing the breakpoint/watchpoint interface - is implemented in a process separate from the debugged application. Since the debugger evaluates the watchpoint expressions and conditional predicates to determine whether to invoke the user, a debugging session typically requires many expensive application-debugger context switches, resulting in slowdowns of 40,000 times or more in current commercial and open-source debuggers! In this paper, we present an effective and efficient implementation of (conditional) breakpoints and watchpoints that uses DISE to dynamically embed debugger logic into the running application. DISE (dynamic instruction stream editing) is a previously proposed, programmable hardware facility for dynamically customizing applications by transforming the instruction stream as it is decoded. DISE embedding preserves the logical separation of application and debugger nstructions are added dynamically and transparently, existing application code and data are not statically modified - and has little startup cost. Cycle-level simulation on the SPEC 2000 integer benchmarks shows that the DISE approach eliminates all unnecessary context switching, typically limits debugging overhead to 25% or less for a wide range of watch-points, and outperforms alternative implementations. Marc L. Corliss, E. Christopher Lewis, Amir Roth |
HPCA | 1 |
| 2005 | The implementation and evaluation of dynamic code decompression using DISEabstractCode compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. Postfetch decompression , in which decompression is performed after the compressed instructions have been fetched, allows the instruction cache to store compressed code but requires a highly efficient decompression implementation. We propose implementing postfetch decompression using a new hardware facility called dynamic instruction stream editing (DISE). DISE provides a programmable decoder---similar in structure to those in many IA-32 processors---that is used to add functionality to an application by injecting custom code snippets into its fetched instruction stream. We present a DISE-based implementation of postfetch decompression and show that it naturally supports customized program-specific decompression dictionaries, enables parameterized decompression allowing similar-but-not-identical instruction sequences to share dictionary entries, and uses no decompression-specific hardware. We present extensive experimental results showing the virtue of this approach and evaluating the factors that impact its efficacy. We also present implementation-neutral results that give insight into the characteristics of any postfetch decompression technique. Our experiments not only demonstrate significant reduction in code size (up to 35%) but also significant improvements in performance (up to 20%) and energy (up to 10%). Marc L. Corliss, E. Christopher Lewis, Amir Roth |
ACM Trans. Embed. Comput. Syst. | 1 |
| 2003 | DISE: A Programmable Macro Engine for Customizing ApplicationsabstractDynamic instruction stream editing (DISE) is a cooperative software-hardware scheme for efficiently adding customization functionality $e.g, safety/security checking, profiling, dynamic code decompression, and dynamic optimization - to an application. In DISE, application customization functions (ACFs) are formulated as rules for macro-expanding certain instructions into parameterized instruction sequences. The processor executes the rules on the fetched instructions, feeding the execution engine an instruction stream that contains ACF code. Dynamic instruction macro-expansion is widely used in many of today's processors to convert a complex ISA to an easier-to-execute, finer-grained internal form. DISE coopts this technology and adds a programming interface to it. DISE unifies the implementation of a large class of ACFs that would otherwise require either special-purpose hardware widgets or static binary rewriting. We show DISE implementations of two ACFs - memory fault isolation and dynamic code decompression - and their composition. Simulation shows that DISE ACFs have better performance than their software counterparts, and more flexibility (which sometimes translates into performance) than hardware implementations. Marc L. Corliss, E. Christopher Lewis, Amir Roth |
ISCA | 1 |
| 2003 | A DISE implementation of dynamic code decompressionabstractCode compression coupled with dynamic decompression is an important technique for both embedded and general-purpose microprocessors. Post-fetch decompression, in which decompression is performed after the compressed instructions have been fetched, allows the instruction cache to store compressed code but requires a highly efficient decompression implementation. We propose implementing post-fetch decompression using dynamic instruction stream editing (DISE), a programmable decoder---similar in structure to those in many IA32 processors---that is used to add functionality to an application by injecting custom code snippets into its fetched instruction stream. A DISE implementation of post-fetch decompression naturally supports customized program-specific decompression dictionaries, enables parameterized decompression allowing similar instruction sequences to share dictionary entries, and uses no decompression-specific hardware. Cycle-level simulation of DISE decompression shows that it can reduce static program size by 35% and execution time by 20%. Parameterized decompression, a feature unique to DISE, accounts for 20% of the code size reduction by making more effective use of the dictionary and allowing PC-relative branches to be included in compressed sequences. DISE-based compression can reduce total energy consumption by 10% and the energy-delay product by as much as 20%. Marc L. Corliss, E. Christopher Lewis, Amir Roth |
LCTES | 1 |