In this article, a compact differential data transfer link architecture for isolated sensor interfaces (SIs) and immune to common mode transients (CMTs) is presented. The proposed architecture shows low latency supporting high-speed transmission with a low bit error rate (BER) in the presence of CMT noise for applications, such as data acquisition, biomedical equipment, and communication networks. In transportation applications, motors and actuators are subjected to harsh environmental conditions, e.g., lightning strikes and abnormal voltage operations. These conditions introduce noise and can cause damage to small electronics due to high-voltage power surges. To ensure human safety and circuitry protection, a data transfer system must be implemented between high-voltage and low-voltage domains. The proposed design has been simulated using Cadence tools, and a prototype has been manufactured in a 0.18-$\mu $m CMOS process. The fabricated prototype consumes an effective silicon area of$37.2\times 10^{3}~\mu $m2and can sustain a breakdown voltage of 710 Vrms. Experimental results show that the proposed solution achieves a CMT immunity (CMTI) of 2.5 kV/$\mu $s at a data rate of 480 Mb/s with a BER of$10^{-12}$. The propagation delay is 3.9ns with a 4 ps/°C variation rate over temperatures ranging from$- 31~^{\circ }$C to$100~^{\circ }$C. Under typical test conditions, the BER reaches$10^{-15}$with a peak-to-peak data dependent jitter (DDJ) of 29.8ps.

In this brief, we present a data communication system for the capacitive digital isolator capable of sustaining a breakdown voltage of 1.27 kVrms. A pulse amplitude modulation (PAM) strategy is implemented as a signal transmission scheme for capacitive coupling for the first time. It enables a data rate of 0.68 Gbps using a smaller number of ON-chip isolation elements and physical links compared with other circuits. In addition, this scheme allows our design to work at low-frequency operations without the need of additional large-area capacitors. Moreover, a propagation delay of 1.9 ns has been measured with a total jitter (TJ) of 333 ps, and a 46.8-pJ/bit energy consumption at 1 Mbps is obtained. The achieved performance ensures the design integration capability with a wide range of power control applications, particularly industrial sensor interfaces.

The Design of efficient, safe, and reliable circuits is a prime objective in high-voltage (HV) electronic systems, such as switched-mode power amplifiers (PAs). One of the main causes of efficiency degradation and reliability problems, in these amplifiers, is the shoot-through current from the HV power supply to the ground. To eliminate such current, a dead time generator (DTG) is used to modify the signals propagating through the high-side and low-side gate drivers by adding a fixed dead time between them. However, any delay mismatch between these gate drivers can reduce the dead time to the point that it becomes negative. In this paper, an HV-DTG architecture is introduced. The architecture mitigates the effects of delay mismatch variations in gate drivers, which can result from parameters mismatch, fabrication process variations, and temperature variations. An HV switched-mode class-D power amplifier is used to illustrate the performance of the DTG. The amplifier is implemented in a low-cost$0.35~\mu m$HV CMOS process. The total area of the PA is$0.5~mm^{2}$, where the DTG covers an area of$0.066~mm^{2}$. A measured system’s efficiency of 95.14% is achieved with the shortest dead time of 10.8 ns, which is 1.38x smaller than the generated dead time in comparable state-of-the-art HV dead time generators.

We present in this paper a high-precision voltage-controlled oscillators (VCO)-based time-domain (TD) comparator. It involves two identical and linear VCOs to convert the input voltage difference of the comparator into the time/frequency difference. Also, it includes a novel low-power phase frequency detector (PFD) to compare the output frequencies of the VCOs. The proposed PFD technique reduces the problematic effects of missing edges and phase ambiguity in conventional circuits by minimizing dead-zone (DZ)/blind-zone (BZ) and suppressing unwanted output glitches. The TD-comparator prototype is fabricated in a 350 -nm CMOS process having an active area of 0.01 mm2. The comparator consumes 93.65 μ W power from a 3.3 -V supply and provides a conversion rate of 2.7 MHz with 148$\boldsymbol {\mu }\mathbf {V_{rms}}$input-referred noise. Measurement results of 5 fabricated chips show an input-referred offset standard deviation of 81.14${\mu }\text{V}$. Stand-alone characteristics measurements of the proposed PFD show a minimized DZ and BZ of less than 12 and 22.7 ps, respectively. With an almost${\pm 2\pi }$input phase range, the maximum operating frequency of the PFD is 1.32 GHz.

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ($\text{C}_{\mathrm {L}}$) and operating frequencies (${f}_{\mathrm {s}}$). The circuit consumed a power between 610$\mu \text{W}$and$850~\mu \text{W}$across the measured deadtime ranges while$\text{C}_{\mathrm {L}} =12$pF,$\text{V}_{\mathrm {dd}} =3.3$V, and$\text{f}_{\mathrm {s}}=200$kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of$150\mu $m$\times 260\mu \text{m}$. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum$\text{T}_{\mathrm {DLH}}$and optimal$\text{T}_{\mathrm {DHL}}$at$\text{I}_{\mathrm {Load}} =25$mA is improved by 12% compared to a converter with a fixed deadtime of$\text{T}_{\mathrm {DLH}} =\,\,\text{T}_{\mathrm {DHL}} =12$ns.

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of half-bridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35$\mu \text{m}$technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of$70\,\,\mu \text{m}\,\,\times 180\,\,\mu \text{m}$. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

This paper presents the design and analysis of combining input-voltage feedforward and proportional-integral (PI) controllers to regulate the output voltage of DC-DC Buck converter subject to input line disturbances. Non-idealities of the Buck converter such as passive and active components parasitics are included in the mathematical model obtained by the statespace averaging (SSA) technique for accurate control. The stability boundary locus approach is used to graphically analyze the system stability. It guides the design of the PI controller gains and the feedforward scaling factor to achieve desired phase and gain margins. Analysis shows that the feedforward scaling factor affects the stability regions of the closed-loop system and can limit the possible PI controller gains for certain phase and gain margins; 75oand 9.54 dB in our case. The results are verified by a Simulink model developed for the Buck converter system.

A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35μm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diode- supercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 μmx100 μm.

In this paper, we propose a novel design methodology for a deadtime generator for high-efficiency power amplifiers. It consists of a two-phase non-overlapping clock circuit and level down shifters. A 3% improvement in efficiency is achieved with a maximum efficiency of 94% in a class-D power amplifier circuit. The proposed design generates a deadtime as low as 16.7ns and eliminates the problem of propagation delay mismatch between high side and low side gate drivers. The circuit is implemented in 50V AMS 0.35 μm CMOS technology. The deadtime generator consumes 16.5 mW, while occupying a total area of 0.068 mm2.

In this paper, a wide range, area efficient, and high-precision pulse generator is presented. The proposed architecture exploits a CMOS thyristor delay element, and benefits from its decent advantages. The proposed circuit generates an input-independent, stable, and accurate pulse width signal. The pulse-width can be tuned continuously in the range of 1.5 ns to 45 ms. This novel structure is a part of a control circuit intended for recognizing the eventual faults and errors in industrial sensor interfaces. The presented circuits have been implemented in 0.35 μm standard CMOS process. It consumes 0.11 to 7.42 mW power from a 3.3 V supply. The total occupied area is about 0.018 mm2and the maximum operation frequency of the proposed pulse generator is 331 MHz.

A novel non-overlapping signal generator intended for power-converters operation is presented. This switched capacitor circuit architecture-based sensor and actuator interface is implemented in AMS-H35B4D3 technology and consumes a power of 51.8 mW from a 3.3V-supply at 1 Mbps. Two-sided wide swing current source, two capacitors, Schmitt triggers and three transmission gates are employed on each side of the current source for implementing this versatile building block. The circuit provides needed dead-time to the power amplifier for high and low voltage applications. The time period of the master CLK is 1μs. The proposed circuit successfully generates two outputs with 0.4813 μs (~half of period) non-overlapping delay between the phases. It occupies an area of 70 μm×180 μm from the total half bridge area of 800 μm×1370 μm.

This paper presents a front-end amplifier with a novel isolation technique. The proposed isolation technique employs a single on chip stacked spiral coils to generate a signal dependent magnetic field. Also, an integrated Hall effect sensor implemented under the coil detects the generated magnetic field, while achieving a minimum isolation working voltage of 430 V. In this configuration, no signal modulation is required and frequencies from DC to 50 kHz are transmitted over the isolation barrier. On the high voltage side, a single bit programmable gain instrumentation amplifier increases the 3-dB frequency of the common mode rejection ratio and supports input differential voltage ranging from -2.5 to 2.5 V. Also, on the low voltage side, a dB-linear PGA with 6 bits of gain setting adapt the signal to the input dynamic range of an ADC. Finally, a programmable second order Butterworth Anti-Aliasing Filter conditioned the signal before conversion.

This paper describes an implementation of low power frequency modulated ultra-wideband (FM-UWB) transmitter in standard 130nm CMOS technology. The transmitter is designed to operate in the range of 3.328-4.608 GHz. A relaxation oscillator is used to generate the subcarrier signal which is calibrated by a phase-locked loop (PLL). The RF carrier is generated using a voltage-controlled oscillator (VCO). A proposed calibration scheme based on a PLL is utilized to calibrate both the upper and the lower frequencies of the operation band. The proposed FM-UWB transmitter consumes 835μW from a 1.2V supply at 500kbps achieving an energy efficiency of 1.67nJ/bit.