Internet of Things (IoT) devices need to continuously adapt their wireless receiver based on the varying communication conditions to achieve the right trade-off between system-level performance and energy efficiency. Even though the environmentadaptability functions are developed in the back end of receiver chains, existing front-ends are designed for a fixed communication standard. The only adaptive wireless systems equipped with tunable front-ends use traditional optimization methods to reconfigure their circuit. The first issue is that these methods require a significant time to converge to the optimal configuration. The second limitation is that they cannot generalize to unseen propagation environments and operational conditions. In this paper, we propose Front-End Adaptation with Reinforcement Learning (FEARL) to dynamically optimize front-end circuits considering the ongoing distortion and interference levels with the aim to achieve optimal wireless system-level performance. FEARL characterizes the wireless link quality using the received baseband samples and reconfigures the front-end in real-time to realize an end-to-end optimized energy-efficient receiver. We developed a framework with the circuit simulator-in-the-loop, which is further utilized to train and evaluate the FEARL policy. The results show that FEARL is$7.8 x$times faster in responding to variations in the wireless environment, and is able to find a satisfactory circuit configuration even in unseen conditions.

Reconfigurability and self-optimization have become essential during radio frequency integrated circuit (RFIC) design to support the growing number of devices and fast changes in the surrounding wireless spectrum. This has created the need to develop new design approaches for RFICs based on end-to-end wireless system-level performance metrics during operation in dynamically changing communication environments. This paper introduces a CMOS mixer with a wide range of digitally tunable bias current for machine learning (ML) based adaptation. The mixer is designed to become part of a self-adaptive receiver (RX) architecture that is capable of optimizing its performance in accordance to wireless channel conditions by evaluating systemlevel parameters. The proposed mixer topology has digitally tunable bias current and a programmable helper current (PHC) circuit to maintain the voltage headroom during operation with a wide tuning range. It is capable of dynamically minimizing power consumption based on performance and wireless network requirements. Post-layout simulation results show that the power consumption can be reduced up to 8x depending on momentary performance needs, while maintaining an IIP3 greater than -2.4 dBm for the entire range of operation.

Cognitive communication utilizes transient openings in the spectrum to communicate opportunistically, which is a promising technique to enable more efficient spectrum usage in an increasingly congested spectrum environment. We aim to address two main challenges associated with cognitive communication: (i) spectrum sensing should be fast and energy efficient for processing a large bandwidth in a short time; (ii) the spectrum sensing approach should be able to simultaneously recognize multiple signals that are present. In this paper, we propose to address these challenges with a novel design framework that consists of a fast on-chip spectrum sensing in conjunction with a novel learning-based spectrum analysis model at the edge to enhance the optimizations for spectrum agility. We first utilize a model of a programmable analog-based high-quality factor (Q) on-chip spectrum sensor that is capable of scanning the sub-6 GHz band to detect the spectrum usage in less than 1μs. The proposed spectrum sensor also enhances the energy efficiency of the sensing. To complement the onchip spectrum sensor, a deep learning (DL) model is deployed for a fine-grained signal detection between channels in the 400 MHz to 6 GHz range, which is intended to be executed on edge devices. Simulation results show that the DL model can detect multiple different modulated signals with a mean Intersection-over-Union (IoU) of 86.8% in highly-variable bandwidth and center frequency scenarios. Finally, we present a system-level model of our framework to demonstrate the spectrum sensing and classification in the sub-6 GHz frequency band.

This paper presents a chopper instrumentation amplifier (IA) architecture with two symmetric differential negative capacitance generation feedback (NCGFB) loops. The NCGFB design technique enables to cancel parasitic capacitances of cables and electrodes at the IA input in order to boost the input impedance. The negative capacitance is generated through feedback loops containing digitally programmable capacitor banks that can compensate for an extra input capacitance of up to 100 pF. A chopping technique is also introduced to enhance the noise performance of NCGFB IAs with input impedance boosting. The proposed amplifier is based on the capacitively-coupled IA (CCIA) architecture with additional circuit-level innovations to increase input impedance and improve noise performance. Two NCGFB loops have been added to further boost the input impedance. These NCGFB loops include a low-pass filter (LPF) to suppress ripples from the chopping prior to feeding the signal back to nodes at which capacitances are cancelled. We present an analysis to verify the stability of the loops as well as their effects on boosting the input impedance. The full symmetry of the NCGFB loops enables the use of identical capacitor banks to maintain a high common-mode rejection ratio (CMRR). The IA was designed and fabricated in 65-nm CMOS technology with a 1.2V supply and consumes$2.46~\mu $W. Chip measurements show that the IA has a 44-dB gain, 40-Hz bandwidth, a total harmonic distortion (THD) of −44.3 dB with 35 mVpp sinusoidal output at 10 Hz, CMRR >90.9 dB, a 92.3 dB power supply rejection ratio (PSRR), 0.54-$\mu $V integrated input-referred noise over a bandwidth of 0.5 - 40 Hz with a noise efficiency factor of 4.75, and an input impedance of 1.9 G$\Omega $at 10 Hz even with an extra input capacitance of 100 pF.

This article presents a design approach for the modeling and simulation of ultralow power (ULP) analog computing machine learning (ML) circuits for seizure detection using electroencephalography (EEG) signals in wearable health monitoring applications. In this article, we describe a new analog system modeling and simulation technique to associate power consumption, noise, linearity, and other critical performance parameters of analog circuits with the classification accuracy of a given ML network, which allows to realize a power and performance optimized analog ML hardware implementation based on diverse application-specific needs. We carried out circuit simulations to obtain nonidealities, which are then mathematically modeled for an accurate mapping. We have modeled noise, nonlinearity, resolution, and process variations such that the model can accurately obtain the classification accuracy of the analog computing-based seizure detection system. Noise has been modeled as an input-referred white noise that can be directly added at the input. Device process and temperature variations were modeled as random fluctuations in circuit parameters, such as gain and cut-off frequency. Nonlinearity was mathematically modeled as a power series. The combined system level model was then simulated for classification accuracy assessments. The design approach helps to optimize power and area during the development of tailored analog circuits for ML networks with the ability to potentially trade power and performance goals while still ensuring the required classification accuracy. The simulation technique also enables to determine target specifications for each circuit block in the analog computing hardware. This is achieved by developing the ML hardware model, and investigating the effect of circuit nonidealities on classification accuracy. Simulation of an analog computing EEG seizure detection block shows a classification accuracy of 91%. The proposed modeling approach will significantly reduce design time and complexity of large analog computing systems. Two feature extraction approaches are also compared for an analog computing architecture.

This paper introduces an on-chip current-driven CMOS parametric frequency divider (PFD) that provides 2:1 frequency division with an output frequency of 2.4 GHz. A custom input driver stage with a buffer enables to generate the input current of the PFD core from a digital clock signal or sinusoidal source, and a band-pass filter (BPF) stage suppresses undesirable harmonics at the output. Analyses and discussions of design considerations provide insights into the PFD’s input driving conditions, filtering characteristics of the output driver, as well as the effects of the limited quality (Q) factor of passive components and layout parasitics. A prototype chip was fabricated in standard 65-nm CMOS technology and tested. The minimum required supply voltage for the PFD driver is 1.4 V with an input frequency of 4.8 GHz, whereas the PFD has an operating frequency range from 4.5 GHz to 5.1 GHz with a supply voltage of 1.5 V. To the best of the authors’ knowledge, the proposed PFD is the first on-chip implementation of a current-driven parametric frequency divider in a standard CMOS process with sub-6 GHz operation, which demonstrates the feasibility of on-chip integration into RF systems.

Teaching analog circuits courses in the current digital era is a significant challenge for instructors. The mathematics needed for the first course on electronics is basic and the analyses are not complicated either. However, it typically requires conceptual understanding and intuition that has to be conveyed in order to avoid frustration during the assembly and testing of amplifiers in the lab, especially when students design them from scratch. A number of excellent textbooks are available that cover the theory, but it is difficult to find compelling literature that extends this knowledge to practical applications. In this paper, basic amplifier theory is revisited and with attention to considerations related to non-idealities and variations. The concept of sensitivity and its use is emphasized as well as, using the benefits of source/emitter degeneration as an example. It is shown that this degeneration indeed corresponds to an effective negative feedback mechanism that improves linearity and accuracy in addition to increasing the amplifier input impedance, all at the expense of reduced voltage gain.

This paper presents a CMOS 2:1 differential parametric frequency divider (PFD) design with an output frequency of 2.4 GHz and an input voltage range of 450~890 mV at 4.8 GHz. The topology is suitable for integration into RF Systems-on-a-Chip (SoCs), and has been constructed for sub-6 GHz applications. A design and optimization methodology for this on-chip PFD is also described in this paper. The simulation results show a performance improvement of the proposed differential PFD compared to a single-ended PFD designed for the same output frequency in the same 65nm CMOS technology.

This paper introduces the utilization of two different input-referred offset voltage correction methods applied to multiple amplifiers within a front-end sensing circuit of a buck regulator for the first time. The multi-amplifier system under investigation contains an instrumentation amplifier consisting of three folded cascode stages and an additional amplifier configured as a unity-gain buffer for a reference voltage. The first method in this work alleviates voltage offsets in this 4-amplifier system based on a shared auxiliary amplifier correction circuit that switches between different target amplifiers; whereas the second method applies a chopping-based auto-zero procedure to cancel the input-referred offset voltage of the same amplifiers. Since the instrumentation amplifier is designed for feedback sensing in integrated power management applications, it has a relatively high bandwidth requirement. For this reason, the chopping technique does not involve a low-pass or band-pass filter. Instead, a successive approximation register (SAR) analog-to-digital converter is used to sense the output. Measurements of the amplifiers fabricated in a 130nm CMOS technology demonstrate that the auxiliary auto-zero offset cancellation method leads to lower input-referred offset voltage standard deviation ($\sigma = 1.31\,\,\mu \text{V}$) compared to the chopping technique ($\sigma = 184.67\,\,\mu \text{V}$), and that the die area requirement and power consumption with the auxiliary amplifier-based offset cancellation (0.105 mm2, 1.32 mW) are lower than with the chopping method (0.25 mm2, 1.72 mW).

This paper describes a hybrid binary frequency-phase shift keying (BF-PSK) receiver architecture designed with a technique involving both the received signal frequency and phase for low-power operation with relatively high data rate. The method enables the demodulation of the incoming signal without synchronization requirements, which reduces the design complexity and power consumption. The architecture allows programmable data rates and channel bandwidths according to application-specific needs. A novel low-noise amplifier architecture is introduced in this paper as well. The Medical Implant Communication System (MICS) band receiver was designed and fabricated in a standard 65nm CMOS technology, and the measurement results demonstrate the feasibility of this architecture. As a proof-of-concept, it operates with a 416 MHz carrier frequency at a state-of-the-art data rate for sub-milliwatt receivers of 10 Mbps, while consuming$610~\mu \text{W}$from a 1 V supply.

This paper introduces an accurate frequency regulation method based on a constant on-time (COT) buck regulator designed for point-of-load (POL) regulation with a fast load transient requirement and wide load range. Traditional COT regulators suffer from frequency shift due to load variations. The proposed frequency adjustment circuit helps the COT control engine to reach its target frequency of operation by adjusting the on-time pulse under varying conditions. This circuit includes a phase detector and a voltage-to-current converter block. The phase error between the target clock signal and the PWM is directly used to adjust the width of the on-time pulse. This will fine-tune the bandwidth of the frequency regulation loop, which can help to improve the transient performance of the COT as well. The fabricated chip has been tested under 20A/$\mu \text{s}$load transient speed with a 10A load step condition. The measured silicon performance shows that the error of the switching frequency is less than 0.16% in the 400kHz to 1MHz range during steady-state operation.

This article introduces an on-chip anomaly monitoring system design approach that is based on thermal profiling and side-channel analysis. The strategy aims at the realization of nonintrusive hardware Trojan (HT) detection over the lifetime of the circuit under test (CUT). To evaluate the capability of the proposed HT detection system, the on-chip electrothermal coupling is modeled as part of the simulation technique, which associates local thermal activities with circuit-level power consumption using a standard electrical simulator. To monitor the thermal profiles on chips with high sensitivity to local temperature changes and the resilience to flicker noise, the sensor architecture described in this article is the first differential temperature sensor equipped with a chopping mechanism. A methodology is described to utilize principal component analysis (PCA) to extract critical information from the quantized output of the system for effective HT detection in the presence of noise. The complete sensor signal path of the system was designed and simulated with foundry-supplied device models (130-nm CMOS technology), and the impact due to process variations have been considered via Monte Carlo simulations. The results indicate that small Trojans with approximately 2 μW of power can be detected within the thermal profile of a CUT consuming more than 500 μW. As the first step to prove the feasibility of on-chip quantization in the HT detection system, a prototype 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) was fabricated with 130-nm CMOS technology.

This paper presents a high efficiency DC-DC converter architecture with adjustable switching frequency to suppress the baseband noise from a power supply for an RF receiver front-end. The system is composed of a boost converter operating in a discontinuous conduction mode (DCM), an analog frequency-to-voltage converter (FVC), and a digital control loop. To prevent the switching noise of the power supply from mixing into the intermediate frequency (IF) signal band of the mixer, the FVC senses the switching frequency of a boost converter and compares it with a reference baseband frequency. The digital control scheme changes the switching frequency of the boost converter if it is close to the baseband frequency by increasing the bias current of the regulating comparator. The complete system has been designed in a 0.13 μm CMOS process. The simulated efficiency of the boost converter is 84.5% with a 300mV input level. Its peak inductor current control has been designed for different input voltage conditions ranging from 50mV to 300mV. The output voltage of the boost converter is 1V with a 1.35% ripple. The converter was simulated with an RF mixer circuit as load, where the mixer achieved an SFDR of 60.3 dB.

Advances of machine learning algorithms have led to improvements of seizure detection capabilities in monitoring systems based on electroencephalography (EEG). Seizure detection hardware requires accurate feature extraction, which is conventionally done in the digital domain by extracting power in different EEG frequency bands over a particular time window. This paper presents an analog counterpart to digital feature extraction. A received signal strength indicator (RSSI) circuit is used for extracting EEG power features in the analog domain. A high-precision RSSI circuit was designed in the sub-threshold domain with ultra-low power consumption and low sensitivity to process-voltage-temperature variations with CMOS technology. Simulation results show that the RSSI circuit consumes 24 nW power, and has a dynamic range of 53 dB with a linearity error of ± 0.5 dB, sufficient to accurately extract features for seizure classification. The analysis of 16 hours of patient EEG data indicates a seizure classification accuracy of 94%, and a non-seizure classification of 86%.

This paper introduces a sinusoidal signal generation technique using successive integration of a digital square wave. It utilizes operational transconductance amplifiers (OTAs) and capacitors to realize the required integrators. To provide an example, the technique has been implemented in 130 nm CMOS technology with a supply voltage of 1 V and a power consumption of 325 μW. In this design, the input square wave and the sinusoidal output signals are both at 10 MHz. The output signal THD is -51 dBc, and the SFDR is 51 dB at 200 mVP-P.

This paper describes a foreground offset calibration scheme for a 3-bit flash analog-to-digital converter (ADC), which is integrated as a coarse ADC within an 8-bit two-step time-interleaved (TI) hybrid ADC architecture. The calibration path emulates the ADC's normal operation to establish realistic loading and transient effects. Analog circuitry for input generation in the calibration path was designed to pass a specific reference for each comparator. A digital-to-analog converter (DAC) generates the calibration voltages. The presented design approach also addresses integration challenges within the hybrid ADC, such as kickback noise and common-mode variations. Simulation techniques were developed to assess the calibration effectiveness in the hybrid ADC system and to determine the standard deviations of the offsets. A prototype chip was fabricated in 130nm CMOS technology for experimental verification of the calibration method. Evaluations of operation with 6-bit resolution at 500MS/s and 10.28MHz input frequency demonstrate a measured ENOB of 5.24 bits after automatic calibration with 500MS/s and an ENOB of 4.93 bits using a 1GS/s clock.

This paper studies the effects of DC-DC switching converters on RF and analog baseband circuits. Simulations of a low-noise amplifier, mixer, and lowpass filter have shown that the impact of switching supply noise can be kept to small levels by design. For the case of loads with frequency conversion, a boost converter design technique to shift the switching frequency of the converter out of the band of interest is proposed.

This paper presents a first-order complex bandpass filter designed with a large-signal linearization technique. A novel adaptive biasing circuit is proposed to extend the linear range of the filter, which was designed in 130nm CMOS technology with a power consumption of 26.1 μW from a 0.6 V supply. The simulated center frequency and bandwidth of the filter are 2 MHz and 600 KHz respectively. It has an image rejection ratio of 22 dB per pole and an out-of-band spurious-free dynamic range of 56.0 dB.

A low-power 1GS/s hybrid analog-to-digital converter (ADC) for portable wireless applications is described. The first stage of the subranging architecture contains a 3-bit flash ADC with offset calibration. Its second stage employs a 5-bit 4-channel time-interleaved (TI) comparator-based asynchronous binary search (CABS) ADC. A merged sample-and-hold and capacitive digital-to-analog converter (SHDAC) samples the input, and generates the residue voltage for the subranging operation in each channel. The error on the residue voltage from the parasitic capacitances is cancelled through a linearity correction method. Design considerations of the amplifier in the unity-gain buffer and bandwidth mismatches between TI channels are studied and exemplified with simulation results. A prototype ADC chip was fabricated in 130nm CMOS technology for experimental verification of the concepts. Evaluations of operation with 6-bit resolution at 1GS/s demonstrate a measured ENOB above 5.26 up to the Nyquist frequency with a power consumption of 10.5mW from a 1.2V supply.

This paper presents a linearity analysis to give insights into the impact of the cascode stage in a common-source low-noise amplifier (LNA) that is designed with subthreshold biasing and a linearity enhancement technique. It is shown how the third-order intermodulation intercept point (IIP3) of the subthreshold LNA improves through addition of an inductor and a digitally programmable capacitor at the gate of the cascode transistor. A 1.8 GHz LNA was fabricated in 0.11μm CMOS technology to demonstrate the linearization approach with chip measurements. The linearized low-power LNA has a 14.8 dB voltage gain, a 3.7 dB noise figure, and a -3.7 dBm IIP3 with a power consumption of 0.336 mW.

A second-order Gm-C low-pass filter with a novel large-signal linearization method for operational transconductance amplifiers having low supply voltages is presented. The design technique uses a combination of unbalanced resistively degenerated differential pairs and adaptive biasing to extend the linear range. The presented unity-gain biquad filter cell is intended to be used as a building block in the baseband section of a low-power receiver, and it has been designed in a standard 0.13-μm CMOS technology with a cutoff frequency of 500 KHz. The power consumption of the filter is 39 μW with a supply voltage of 0.6 V. Simulation results show a total harmonic distortion of -40 dB for a 5 KHz input tone with 614 mV peak-to-peak differential swing in the passband of the filter.

A clock generation system for a 1GS/s 8-bit subranging time-interleaved analog-to-digital converter (ADC) is introduced. General timing considerations for time-interleaved ADCs are reviewed prior to describing the design methodology for a prototype ADC. This hybrid ADC architecture contains four time-interleaved combined sample-and-hold and capacitive digital-to-analog converter (SHDAC) circuits as front-end sample-and-hold for a flash stage and for a time-interleaved successive approximation stage, which minimizes the errors due to sampling time mismatches between the two stages. The associated clock signal generation techniques that enable this hybrid ADC design approach are presented in this paper, which range from particular non-overlapping clocks and extensive buffering to synchronous resetting for adjusting the order of the clock signals in each time-interleaved channel. The transistor-level and layout-level clock generation circuits were designed and simulated in 130nm CMOS technology, and consume 3.88mW from a 1.2V supply. The standard deviation of the timing skews between time-interleaved channels is less than 1ps based on Monte Carlo simulations. To evaluate the feasibility of the clock generation approach, post-layout simulations were conducted with the interconnected ADC core layout and routed clock generation circuits. The hybrid ADC achieved an effective number of bits (ENOB) of 7.39 with a sampling frequency of 1GHz and an input frequency close to the Nyquist rate.

An 8-bit 1-GS/s hybrid analog-to-digital converter (ADC) for high-speed low-power applications is introduced. It has a subranging architecture with a 3-bit flash ADC as a first stage and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. In each channel, a merged sample-and-hold and capacitive digital-to-analog converter (SHDAC) performs the sampling and residue generation for the subranging operation. The effects of the parasitic capacitances on the SHDAC linearity are analyzed, and a linearity correction method is introduced to enable power-efficient high-speed operation in the presence of parasitics because the design approach allows reducing the sampling capacitance in the SHDAC. Furthermore, the sampling network configuration incorporates an error reduction technique to alleviate the clock feedthrough of bootstrap switches. The offsets of the comparators in the flash ADC are calibrated using a built-in reference signal via an extra sampling channel. According to postlayout simulations at 1 GS/s in 130-nm CMOS, the ADC has an effective number of bits higher than 7.37 bits up to the Nyquist frequency while consuming 13.3 mW from a 1.2-V supply.

Nowadays, radio frequency (RF) circuits have to be optimized by design for reliable high performance with minimal power consumption to reach complete system-on-chip solutions that meet end user demands in diverse emerging applications. This paper reviews several recently developed design approaches and verification/simulation methods for performance improvements of RF integrated circuits. After the overview, the augmentation of an RF power amplifier with digital predistortion for enhanced linearity is discussed in more detail as an example.

A high linearity subthreshold mixer with negative impedance generation is presented. The mixer configuration was formed by adding two cross-coupling capacitors to a conventional structure. Since the internal negative impedance generation of this construction cancels parasitic capacitances, the conversion gain loss due to the parasitic capacitances is alleviated and the linearity is improved. Small-signal model calculations with Volterra series are presented to analyze the effects of cross-coupling capacitors on IIP3 and conversion gain, confirming that this design approach can improve the IIP3. The mixer was designed in 130nm CMOS technology and simulated with extracted layout parasitics. Having a power consumption of 0.373mW and a layout area of 0.0323mm2, it achieves more than 9dB conversion gain and 14dBm IIP3 from 2.4GHz to 11.4GHz.

A 3-bit current-mode flash quantizer with current summing stage in a commercial 90-nm CMOS technology is presented. The topology is intended for low-power feed-forward continuous-time sigma-delta modulators. Current summation is realized using a common-gate structure. Replicas of the input signal current are compared with the reference currents through high-impedance nodes that ease the signal quantization. The comparison stage employs reset switches to enable fast comparisons. The proposed approach involves zero crossing comparators, and it employs current references instead of voltage references that demand a power-hungry resistive ladder. Results show that the proposed current-mode approach is faster than the conventional voltage-mode flash approach, and it requires a smaller input capacitance while consuming 53% less power. A 3-bit prototype design has a measured effective number of bits over 2.6 bits up to 2-GHz clock frequency with 10-MHz full-scale input signal. At 1.48-GHz clock frequency, the static differential nonlinearity (DNL) and integral nonlinearity (INL) errors are within -0.206 least significant bit (LSB) and 0.206 LSB, respectively. The proposed current-mode flash analog-to-digital converter (ADC) core dissipates 3.34-mW analog power from a 1.2 V supply while operating at 1.48 GHz. The core area of the ADC including the biasing circuitry is 0.0276 mm2.

The fast Fourier transform (FFT) algorithm is widely used as a standard tool to carry out spectral analysis because of its computational efficiency. However, the presence of multiple tones frequently requires a fine frequency resolution to achieve sufficient accuracy, which imposes the use of a large number of FFT points that results in large area and power overheads. In this paper, an FFT method is proposed for on-chip spectral analysis of multi-tone signals with particular harmonic and intermodulation components. This accurate FFT analysis approach is based on coherent sampling, but it requires a significantly smaller number of points to make the FFT realization more suitable for on-chip built-in testing and calibration applications that require area and power efficiency. The technique was assessed by comparing the simulation results from the proposed method of single and multiple tones with the simulation results obtained from the FFT of coherently sampled tones. The results indicate that the proper selection of test tone frequencies can avoid spectral leakage even with multiple narrowly spaced tones. When low-frequency signals are captured with an analog-to-digital converter (ADC) for on-chip analysis, the overall accuracy is limited by the ADC's resolution, linearity, noise, and bandwidth limitations. Post-layout simulations of a 16-point FFT showed that third-order intermodulation (IM3) testing with two tones can be performed with 1.5-dB accuracy for IM3 levels of up to 50 dB below the fundamental tones that are quantized with a 10-bit resolution. In a 45-nm CMOS technology, the layout area of the 16-point FFT for on-chip built-in testing is 0.073 mm2, and its estimated power consumption is 6.47 mW.

Despite the advantages offered by field-programmable gate arrays (FPGAs) for low-power systems requiring flexible computing resources, applications with the lowest power budgets still favor microprocessors and application-specific integrated circuits (ASICs). In order for such systems to exploit FPGAs, an FPGA achieving minimum energy operation is needed. Minimum energy points have been found for ASICs and microprocessors to occur at operating voltages that are typically below the transistor threshold voltage. This paper presents two clustered island-style test chips capable of operating with a single supply voltage as low as 260 mV. This supply voltage represents the lowest voltage at which an FPGA has been successfully programmed. Test chip measurements show that the minimum energy point of both circuits is at or below this minimum operating voltage. Operation at 260 mV leads to a 40X power-delay product reduction vs. 1.5V operation. The results demonstrate a clear path forward for fabricating low voltage FPGAs that are fully compatible with existing tool flows.

This paper presents a subthreshold cascode low-noise amplifier (LNA) with inductive source degeneration and third-order linearity enhancement. The LNA architecture includes an inductor and a capacitor at the gate of the cascode transistor for partial cancellation of third-order distortion components. This design method enables third-order intermodulation intercept point (IIP3) and 1dB compression point (P1dB) improvements of 4.8-11.2 dB and 7.1-11.6 dB respectively (depending on the process corner case) compared to a commensurate LNA without the linearization method. A 2.4 GHz LNA was designed and simulated using 0.13 μm CMOS technology. In the typical corner case, the linearized LNA achieves -2.0 dBm IIP3, -13.5 dBm P1dB, 18.2 dB power gain, and 4.54 dB noise figure with a power consumption of 0.24 mW.

A current-mode flash analog-to-digital converter (ADC) with current summing stage was designed and evaluated. The topology is intended for low-power feed-forward continuous-time sigma delta (CTSD) modulators and was fabricated in a commercial 90nm CMOS technology. A 3-bit prototype has an effective number of bits (ENOB) of 2.87 bits at 2GS/s with 12MHz full-range input power. The static DNL and INL errors are both in the range of 0.24 LSB. The ADC achieves an SNDR of 15dB with a 1GHz input signal and an SNDR above 19dB for input signals below 300MHz. A major advantage of this architecture is its voltage scalability as well as the reduced input capacitance. The proposed ADC core dissipates 3.1mW power from a 1.2V supply while operating at 2GHz.

This poster shows how to efficiently observe high-frequency figures of merit in RF circuits by measuring DC temperature with CMOS-compatible built-in sensors.