Naveen Neelakantam

dblp:68/1404 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-authorSoftware engineering, systems software and programming languages · 4 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Parallel and multicore computing · 61% Processor architecture and microarchitecture · 33% Memory systems · 6%
Software engineering, system software, and programming languages
3 papers
Compilers and program optimization · 57% Runtime systems and virtual machines · 35% Concurrent programming · 8%

Topics — the 9 heaviest of 11, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Runtime systems and virtual machines
binary translation
0.112010
A real system evaluation of hardware atomicity for software speculation · ASPLOS 2010
Compilers and program optimization
dynamic optimization
0.112010
A real system evaluation of hardware atomicity for software speculation · ASPLOS 2010
Parallel and multicore computing › transactional memory
hardware transactional memory
0.112010
A real system evaluation of hardware atomicity for software speculation · ASPLOS 2010
Processor architecture and microarchitecture
speculative execution
0.122010
Hardware atomicity for reliable software speculation · ISCA 2007
A real system evaluation of hardware atomicity for software speculation · ASPLOS 2010
Parallel and multicore computing › transactional memory
hybrid transactional memory
0.112008
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory · ISCA 2008
Parallel and multicore computing
transactional memory
0.112008
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory · ISCA 2008
Concurrent programming
transactional memory
0.012008
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory · ISCA 2008
Processor architecture and microarchitecture
atomic operations
0.012007
Hardware atomicity for reliable software speculation · ISCA 2007
Processor architecture and microarchitecture
instruction set architecture
0.012007
Hardware atomicity for reliable software speculation · ISCA 2007

Methods — techniques the papers use, named apart from their topics

atomic region compiler abstraction · 0.2
YearPublicationVenuePosition
2010 A real system evaluation of hardware atomicity for software speculation
abstract
In this paper we evaluate the atomic region compiler abstraction by incorporating it into a commercial system. We find that atomic regions are simple and intuitive to integrate into an x86 binary-translation system. Furthermore, doing so trivially enables additional optimization opportunities beyond that achievable by a high-performance dynamic optimizer, which already implements superblocks.
Naveen Neelakantam, David R. Ditzel, Craig B. Zilles
ASPLOS1
2008 Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
abstract
We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be made strongly atomic by using memory protection on transactionally-held state, then showing how such a strongly-atomic STM can be used with a bounded hardware TM system to build a hybrid TM system in which zero-overhead hardware transactions may safely run concurrently with potentially-conflicting software transactions. We experimentally demonstrate how this hybrid TM organization avoids the common-case overheads associated with previous hybrid TM proposals, achieving performance rivaling an unbounded HTM system without the hardware complexity of ensuring completion of arbitrary transactions in hardware. As part of our findings, we identify key policies regarding contention management within and across the hardware and software TM components that are key to achieving robust performance with a hybrid TM.
Lee Baugh, Naveen Neelakantam, Craig B. Zilles
ISCA2
2007 Hardware atomicity for reliable software speculation
abstract
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant complexity, which can limit their adoption, limit their optimization scope, and negatively impact the reliability of the compilers that implement them. To eliminate much of this complexity, as well as increase the effectiveness of these optimizations, we propose that microprocessors provide architecturally-visible hardware primitives for atomic execution. These primitives provide to the compiler the ability to optimize the program's hot path in isolation, allowing the use of non-speculative formulations of optimization passes to perform speculative optimizations. Atomic execution guarantees that if a speculation invariant does not hold, the speculative updates are discarded, the register state is restored, and control is transferred to a non-speculative version of the code, thereby relieving the compiler from the responsibility of generating compensation code.
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, Uma Srinivasan 0003, Craig B. Zilles
ISCA1
2005 Reactive Techniques for Controlling Software Speculation
abstract
Aggressive software speculation holds significant potential, because it enables program transformations to reduce the program's critical path. Like any form of speculation, however, the key to software speculation is employing it only where it is likely to succeed. While mechanisms for controlling hardware speculation (e.g., saturating counters updated after each instance) are well understood, these techniques do not translate directly to software techniques because changing a speculation requires changing the code. As it stands, the dominant software speculation control technique, non-reactive profile-guided optimization, lacks the robustness to support aggressive speculation. The primary thesis of this paper is that software speculation can be made to be robust by adding a reactive controller that can dynamically adjust the speculation. We make two primary observations about such systems: 1) reactive control systems can select behaviors on which to speculate with performance that equals or exceeds self-training, and 2) such control systems are remarkably latency tolerant. Although reactivity is required, it can be done at a low frequency; latencies of hundreds of thousands, or even millions of cycles, can be tolerated for most actions. Together these two characteristics imply that robust aggressive software speculation is a realistic goal.
Craig B. Zilles, Naveen Neelakantam
CGO2