The report, Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering (CE2016), developed by the Association for Computing Machinery and the IEEE Computer Society, was released in December of 2016. This is one volume of a series of reports covering curricula for a variety of computing fields; it is a significant update of the previous version, CE2004. This paper discusses significant aspects of CE2016, with a focus on how the report might be used in reviewing, updating, and creating computer engineering programs.

ACM and the IEEE Computer Society plan to re-lease their computer engineering curriculum guidelines at the end of this calendar year. The curricular report, tagged CE2016, reflects the state-of-the-art in computer engineering education and practice that would be relevant for the coming decade. This panel presentation provides an overview of the report and it also provides unique perspectives from some steering committee members and other interested parties. The authors and participants will en-gage in discussions on ways to implement the guidelines to form new programs or to modify existing programs. The authors wel-come all audience participation including overall comments and targeted editing assistance from the computer engineering education and industry communities.

Joint ACM/IEEE Computer Society undergraduate computer engineering curriculum guidelines are slated for release in 2016. These update the 2004 guidelines commonly known as CE2004. The presenters are part of the task group leading the revisions and will give an overview of the latest draft. Participants will engage in discussions on potential improvements to the guidelines to ensure that they are useful to programs as they work to ensure their curricula reflect the state-of-the-art in computer engineering education and practice and are relevant for the coming decade.

This paper first presents a Markov chain that exactly models an optical shared-memory packet switch. Without loss in model accuracy, this Markov chain state size is greatly reduced to form a reduced Markov chain (RMC). A simplified construction method is given to make the RMC tractable. Throughput and probability of packet loss derived using the RMC are also presented.

Performance of shared memory architectures for optical switching is typically obtained by simulation, and in low packet loss regions is subject to statistical error or excessive computer run times. To obtain a reliable measure of performance, a Markov chain with a small number of states has been developed to model the switch's behavior. This reduced chain is derived from a full Markov chain which more directly models the switch. Equations to count the number of states for both Markov chains are derived. Packet loss results derived from the reduced Markov chain are compared with simulation results.

This paper addresses the issue of testing MCMs on large-area substrates. The cost of testing each MCM may be as high as 40% of the total manufacturing cost. It is critical that the test process be parallelized in order that multiple MCMs may be tested for the cost of testing one MCM. With this objective in mind, we propose a distributed probabilistic diagnosis algorithm for MCMs on large-area substrates. Our algorithm performs better than the existing diagnosis algorithms and can correctly identify almost all MCMs even when the yield is very low (35%). Further it provides upto an order of magnitude reduction in test application time as opposed to serial MCM probe test.

A simulation study of the 74LS181 4-b ALU (arithmetic logic unit) using 16 complete single stuck-at fault test sets demonstrated significantly higher multiple stuck-at fault coverage than predicted by previous theoretical studies. Analysis of the undetected multiple faults shows the effect of circuit and test set characteristics on fault coverage. A fault masking property, defined as self-masking, is observed for the undetected faults in the simulation study. A heuristic is described for evaluating the multiple fault coverage of single stuck-at fault test sets. A second heuristic generates augmented test sets, providing improved multiple stuck-at fault coverage with a minimal increase in test set development cost.>

Two new general designs for totally self-checking (TSC) comparators with an arbitrary number of input vectors are presented. The multipattern comparator combines modified TSC 2-input comparators and a TSC two-rail checker that requires only four patterns for self-testing. The counter-driven comparator adds circuitry to generate an exhaustive set of test patterns. The designs are compared on the basis of input limitations, circuit complexity, and gate delays. It is shown that TSC comparators cannot exist under two sets of conditions associated with 1-bit input vectors and two-level circuit realizations.