VLDB 2026 Research / reviewers in the wild / expert
Jeremy Wong
dblp:68/3690
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 62% Processor architecture and microarchitecture · 38% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization
parallelizing compiler |
0.0 | 1 | 2002 | A stream compiler for communication-exposed architectures · ASPLOS 2002 |
Compilers and program optimization › domain-specific compilation
stream compiler |
0.0 | 1 | 2002 | A stream compiler for communication-exposed architectures · ASPLOS 2002 |
Parallel and multicore computing › parallel programming models
stream programming |
0.0 | 1 | 2002 | A stream compiler for communication-exposed architectures · ASPLOS 2002 |
Processor architecture and microarchitecture
chip multiprocessor |
0.0 | 1 | 2002 | A stream compiler for communication-exposed architectures · ASPLOS 2002 |
Processor architecture and microarchitecture
tiled architecture |
0.0 | 1 | 2002 | A stream compiler for communication-exposed architectures · ASPLOS 2002 |
Methods — techniques the papers use, named apart from their topics
static scheduling · 0.1graph layout · 0.1fission and fusion transformations · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | A stream compiler for communication-exposed architecturesabstractWith the increasing miniaturization of transistors, wire delays are becoming a dominant factor in microprocessor performance. To address this issue, a number of emerging architectures contain replicated processing units with software-exposed communication between one unit and another (e.g., Raw, SmartMemories, TRIPS). However, for their use to be widespread, it will be necessary to develop compiler technology that enables a portable, high-level language to execute efficiently across a range of wire-exposed architectures.In this paper, we describe our compiler for StreamIt: a high-level, architecture-independent language for streaming applications. We focus on our backend for the Raw processor. Though StreamIt exposes the parallelism and communication patterns of stream programs, some analysis is needed to adapt a stream program to a software-exposed processor. We describe a partitioning algorithm that employs fission and fusion transformations to adjust the granularity of a stream graph, a layout algorithm that maps a stream graph to a given network topology, and a scheduling strategy that generates a fine-grained static communication pattern for each computational element.We have implemented a fully functional compiler that parallelizes StreamIt applications for Raw, including several load-balancing transformations. Using the cycle-accurate Raw simulator, we demonstrate that the StreamIt compiler can automatically map a high-level stream abstraction to Raw without losing performance. We consider this work to be a first step towards a portable programming model for communication-exposed architectures. Michael I. Gordon, William Thies, Michal Karczmarek, Jasper Lin, Ali S. Meli, Andrew A. Lamb, Chris Leger, Jeremy Wong, Henry Hoffmann, David Maze, Saman P. Amarasinghe |
ASPLOS | 8 |