This paper presents a technology mapper that optimizes the average performance of asynchronous burst-mode control circuits. More specifically, the mapper can be directed to minimize either the average latency or the average cycle time of the circuit. The input to the mapper is a burst-mode specification and its NAND-decomposed unmapped network. The mapper preprocesses the circuit's specification using stochastic techniques to determine the relative frequency of occurrence of each state transition. Then, it maps the NAND-decomposed network using a given library of gates. Of many possible mappings, the mapper selects a solution that minimizes the sum of the delays (latency or cycle time) of all state transitions, weighted by their relative frequencies, thereby optimizing for average performance. We present experimental results on a large set of benchmark circuits, which demonstrate that our mapped circuits have significantly lower average latency and cycle time than comparable circuits mapped with a leading conventional mapping technique which minimizes the worst case delay. Moreover, these performance improvements can be achieved with manageable run-times and significantly smaller area.