VLDB 2026 Research / reviewers in the wild / expert
Aly M. H. Ahmed
dblp:68/416
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
functional testing |
0.0 | 1 | 1989 | Microprocessors functional testing techniques · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1989 | Microprocessors functional testing techniques · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 |
Electronic design automation › hardware verification and test › VLSI testing
microprocessor testing |
0.0 | 1 | 1989 | Microprocessors functional testing techniques · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989 |
Methods — techniques the papers use, named apart from their topics
instruction set reduction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | Microprocessors functional testing techniquesabstractThe authors address the functional testing of microprocessors. A method is introduced for obtaining a minimum set of instructions that replaces the whole instruction set during testing procedure. The method is illustrated on the digital signal processor TM32010.> El-Sayed A. Talkhan, Aly M. H. Ahmed, Aly E. Salama |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |