In conventional paradigms of machine learning (ML) and deep learning (DL), models are trained as ’black boxes’ on task-specific datasets prior to deployment. This poses various challenges to the application of AI for spectral adaptation. First, we cannot ensure the reliability of the model, since we do not know how they correlate signal features with their recognition target. We need a method to explain the final stage of decision-making. To address the first challenge, we propose a zero-bias neural network where we replace the penultimate layer of a specific DNN or CNN model with an extended Cosine Similarity Matching layer, called the zero-bias dense layer. This adaptation has been proven not to affect the learning and inferential capabilities of AI models. In this research study, we used the zero-bias neural network (ZBNN) for spectral sensing on the RADIOML 2016.10A dataset, which consists of 11 different modulation types, consisting of both analog and digital signals having varying Signal-to-noise ratio (SNR). To compare the ZBNN accuracy, we used the CNN model having identical hyperparameters. The proposed ZBNN for spectral sensing has the potential to become the fundamental building block for explainable AI, especially in remote spectral sensing.

Discrete Fourier Transform (DFT) based beam-formers provide N beams with a uniform linear array having N antennas. Despite low-complexity, DFT beamformers cannot generate deep nulls at arbitrary directions of arrivals (DOAs) in the beam pattern to attenuate interferences. On the other hand, data-dependent adaptive beamformers can achieve deep nulls at arbitrary DOAs, however, at higher complexity due to an inversion of a matrix in deriving optimum weights. In this paper, we propose a combined approximate DFT (ADFT) and adaptive beamformer for a uniform linear array consisting of P subarrays, each consisting of M antennas. Here, we first employ P ADFT beamformers to process signals received by subarrays, and the P outputs of these subarrays are then processed by an adaptive beamformer. Simulation results confirm that the proposed beamformer provides the benefits of both DFT and adaptive beamformers. Furthermore, we present preliminary results of an experimental antenna array operating at 5.75 GHz, where a Howells-Applebaum beamformer is employed as the adaptive beamformer.

Multifunctional and waveform agnostic antenna apertures having multiple simultaneous RF beams are necessary for emerging electromagnetic situational awareness applications. A multibeam aperture operating across the entire 1-6 GHz band is crucial for both military and commercial wireless applications. Spectrum perception refers to the application of artificial intelligence (AI) and machine learning (ML) to wireless applications to extract intelligence on spectral activity as a function of both direction and waveform parameters (frequency, modulation, and waveform shape). Efficient and accurate RF sensing is a necessary precursor to higher level AI/ML spectral perception algorithms for detecting particular waveforms, behaviors, or signatures. This paper explores multibeam beamforming for RF sensing as a joint analog-digital hybrid approximate computing problem that can be efficiently implemented using multiple chiplets. The first chiplet includes both a multiport LNA with Δ-Σ spatial noise shaping to improve resilience to high power jammers, and an approximate DFT (ADFT) based analog multi-beamformer with reduced circuit complexity. The second chiplet includes ADCs and ADFT-based digital beamformers with reduced computational complexity compared to conventional DFT-based designs. Initial results on the design of both chiplets are presented.

The combined use of algorithms for approximate discrete cosine transform (DCT) with approximate computing is examined toward area-efficient field programmable gate array (FPGA) hardware architectures. The performance of previously reported, multiplierless approximate DCT transforms are explored in the presence of non-exact hardware adders which provide better utilisation of FPGA resources in terms of look-up-tables (LUTs). In the context of 2D image compression, provided examples are demonstrating a 20% LUT reduction in FPGA utilization compared to accurate adders, with a corresponding image quality degradation of 0.6 dB in terms of PSNR. The potential benefit of such area-efficient FPGA hardware designs is explored on 3D (video compression), 4D (static light field compression), and 5D (light field video compression) cases where significant FPGA resource savings are obtained at the cost of marginal degradation of output quality.

The radio spectrum in the sub-6 GHz (FR1) band is crowded and contested, and is sought after by commercial, scientific and defense users. Situational awareness through spectrum sensing, and AI/ML-enabled perception that recognizes behaviors, patterns, modulations, devices and waveforms is a crucial need for emerging autonomous/cognitive radio systems. This work describes measurable progress in the use of extremely low complexity approximate DFT algorithms as multi-beam beamformers in the digital domain for multibeam spatial RF beamforming. The paper begins with a longterm vision for intelligent spectrum awareness across wide bands and multi-directions with multi-chiplet system in package hardware acceleration of both beamforming, Fourier and AI/ML algorithms, followed by a focus account of specific progress with digital architectures and real-time prototype implementations across the 5.7–5.8 GHz band for 32 RF beams. A real-time temporal frequency resolution of 100 kHz across 100 MHz of baseband bandwidth is achieved, across 32 simultaneous fully-digital RF-beams, using a Xilinx Sx475 FPGA implementation. Details of multiplierless approximate DFT beamformers, automated modulation recognition algorithms using AI/ML, analog channelization, spectrum sensing and perception architectures are also discussed. Over-the-air experiments using the RadioML.2018.a dataset confirmed both single source accuracy (better than 97%) and impact of multi-beams on AI/ML performance for multiple strong RFI sources.

The power of logarithmic quantizations and computations has been recognized as a useful tool in optimizing the performance of large ML models. In this article, we provide results that demonstrate significantly better quantization signal-to-noise ratio performance thanks to multiple-base logarithmic number systems (MDLNS) in comparison with the floatingpoint quantizations that use the same number of bits. On a hardware level, we present details about our Xilinx VCU-128 FPGA design for dot product and matrixvector computations. The MDLNS matrix-vector design significantly outperforms equivalent fixed-point binary designs in terms of area (A) and time (T) complexity and power consumption as evidenced by a 4× scaling of AT2metric for VLSI performance, and 57% increase in computational throughput per watt compared to fixed-point arithmetic.

We propose a minimax design method for multi-dimensional (M-D) interpolated finite-support impulse response (IFIR) filters. As a result of the cascade structure of an MD IFIR filter, the optimization problem of the minimax design is nonconvex. In order to solve this nonconvex optimization problem, we employ a convex-concave procedure, where each iteration solves a convex constrained optimization problem. We present experimental results to confirm the effectiveness and the superior performance of the proposed method compared to previously proposed minimax designs of M-D IFIR filters. Furthermore, we present an implementation of M-D IFIR filter on the Xilinx Kintex UltraScale KCU105 field-programmable gate array, where a quantization error of −60.59 dB is achieved with the coefficient word length of 24 bits.

This paper describes an analog CMOS IC for fast and fully-parallel finite-difference time-domain (FDTD) simulations of 2D electromagnetic (EM) problems. The chip uses discrete-time switched-current (SI) networks to model Maxwell's equations in 2D while minimizing the effects of device mismatch on solver accuracy. A prototype design in 180 nm technology implements a$16\times 16$solver grid within an active area of 44.5 mm2while consuming 345 mW at a clock frequency of 20 MHz.

Two-dimensional (2-D) infinite-extent impulse response (IIR) filter design is a challenging problem due to the difficulty in verifying stability. optimization methods proposed so far predominantly consider the design of 2-D IIR filters having quadrantally-symmetric frequency responses, where the transfer functions have separable denominators. In this paper, we propose a weighted least-squares (WLS) design method for 2-D IIR filters having arbitrary frequency response and stable in the practical bounded-input bounded-output (P-BIBO) sense. Our design considers transfer functions with nonseparable numerators and denominators having complex-and real-valued coefficients, respectively. We formulate the WLS design as an iterative second-order cone programming problem, which includes constraints to guarantee the P-BIBO stability. Design examples confirm that the proposed WLS method leads to P-BIBO stable 2-D IIR filters.

Mostly-online teaching experiences in circuits and systems (CAS) during 2020-2021 COVID-19 pandemic are presented. Three case studies are shared summarizing course details, tools and platforms, best practices and limitations across three universities representing different continents. The presented approaches attempt to address several limitations of passive online delivery of CAS courses via interactive simulations, formative assessments via interactive web content and slide-embedded polls, at-home labs with student acquired hardware and instructor-lead and student-centered activity based learning.

The ever increasing technological demand for the DFT computation poses several challenges both to theory and hardware realization. The design of usual fast Fourier transform (FFT) algorithms seems to have reached a stage of diminishing returns in terms of performance. Alternatively, approximate transform methods have been demonstrated to provide substantial gains in terms of energy-efficiency and performance by tolerating small inaccuracies in the results. In this paper, we present a transform scaling method variant of the Cooley-Tukey algorithm to obtain DFT approximations of large blocksize. The proposed method scales up a givenN-point transformation to anN2-point transformation. Such scaling can be successively applied leading to$\mathop {{N}^2}\nolimits^n $-point transformations. We have fully presented the 324-point DFT approximation which stems from a multiplierless 32-point DFT approximation. The proposed approximation is equipped with a fast algorithm; we also supply the arithmetic complexity assessment and an error analysis.

Optimal use of scarce radio spectrum is essential in the proliferation of beyond 5G networks, and promising blockchain technology offers various benefits for the spectrum management. However, existing blockchain-based solutions are expensive, nonoptimized, and lack spectrum fraud detection. This article proposes a novel consensus mechanism for a blockchain-based dynamic spectrum access (DSA) system. The proposed “Proof-of-Sense” consensus mechanism operates based on spectrum sensing procedures rather than cryptographic calculations. It is specially designed to address fraudulent/unauthorized access to the spectrum by analyzing the sensed spectrum data. The core of the consensus mechanism is a cryptographic key sharing mechanism inspired by Shamir’s secret sharing scheme. Moreover, the proposed DSA system can enable different microservices, such as automated spectrum auctions, payment and penalty handling, and spectrum fraud detection. A proof of concept based on experimental approaches coupled with Matlab simulations is presented to analyze the performance of the proposed consensus mechanism.

Large antenna arrays enable directional precoding for Millimeter-Wave (mmWave) systems and provide sufficient link budget to combat the high path-loss at these frequencies. Due to atmospheric conditions and hardware malfunction, outdoor mmWave antenna arrays are prone to blockages or complete failures. This results in a modified array geometry, distorted far-field radiation pattern, and system performance degradation. Recent remote array diagnostic techniques have emerged as an effective way to detect defective antenna elements in large antenna arrays with few diagnostic measurements. These techniques, however, are dependent on full and perfect channel state information (CSI), which can be challenging to acquire in the presence of antenna faults. This paper proposes a new remote array diagnosis technique that relaxes the need for full CSI and only requires knowledge of the incident angles-of-arrival, i.e. partial channel knowledge. Numerical results demonstrate the effectiveness of the proposed technique and show that fault detection can be achieved with comparable number of diagnostic measurements required by diagnostic techniques based on full channel knowledge. In presence of channel estimation errors, the proposed technique is shown to out-perform recently proposed array diagnostic techniques.

This paper describes a circuit theoretic formulation for simulating the Schrödinger equation using classical analog circuits. Update equations for a finite difference time domain (FDTD) Schrödinger equation solver with absorbing boundary conditions (ABCs) are used to derive signal flow graphs that naturally map to switched capacitor (SC) circuits. A prototype implementation of a fully-parallel SC FDTD solver with 128 spatial points and a clock frequency of 2 MHz is analyzed and simulated using a standard 180 nm CMOS process.

We propose a weighted least-squares (WLS) design method for multi-dimensional (M-D) complex-coefficient finite- extent impulse response (FIR) filters. We consider the general form of M-D FIR filters having arbitrary frequency responses and low group delays. We formulate the proposed WLS design as a second-order cone programming problem. Design examples confirm that the proposed method provides the state-of-the-art M-D FIR filter designs with almost constant group delay.

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between -7 and -30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205× and 140×, respectively.

Network transmission over millimeter-wave (mmW) bands has a big potential to provide orders of higher bandwidth. However, beamforming is generally needed to compensate for the high path loss. As mmW antennas have a potentially large number of candidate beamforming directions, to achieve high network throughput, the finding of a high gain direction between a base station and each mobile in the mmW network may involve a large overhead if training signals are directly sent along all possible directions or according to a large volume of codebook. Taking advantage of the block sparse characteristics of the mmW channel and coexistence of legacy antennas, we propose a comprehensive design for more efficient beam direction finding. Different from existing compressive-sensing-based schemes which just take a random subset of directions to measure, taking advantage of the path clustering feature of the mmW channel, we develop a self-adaptive block sparse algorithm which can benefit from preliminary channel estimation during each iteration of the problem solving to significantly improve the overall channel estimation accuracy thus the beam alignment gain. We also explore two methods to exploit co-located legacy antennas to provide further guidance for transmission direction finding. Simulation results indicate that our proposed beam alignment scheme outperforms the baseline and peer schemes in terms of the beamforming gain and training cost. By taking advantage of the block sparse properties of mmW channel, our proposed design is able to achieve the transmission throughput comparable with the exhaustive direction search at much lower overhead.

A minimax design for 2-D complex-coefficient FIR filters having asymmetric frequency responses is proposed in this paper. We consider the general form of 2-D FIR filters with low group delay and formulate the minimax design as a semidefinite programming problem. The 2-D linear-phase FIR filters with conjugate-symmetric coefficients are a special case of the proposed design. Example filter designs having near-equiripple magnitude responses are presented to verify the effectiveness of the proposed design method.

This paper describes a single-chip analog computer for solving the one dimensional (1-D) wave equation. The chip integrates a 16-point discrete-time but continuous-valued finite-difference solver with spatially-programmable wave velocity, selectable boundary conditions, and arbitrary input excitation waveforms. Built-in Δ-Σ analog-to-digital converters (ADCs) allow the solution results to be easily read out by a digital processor. The design was realized in TSMC 180 nm CMOS and has an active area of 2.81 mm × 2.64 mm. Experimental results prove the functionality of the proposed analog solver.

A low-complexity codec and a hardware architecture are proposed for achieving real-time compression of four-dimensional (4-D) light field (LF) signals captured from camera/lenslet arrays. The proposed system employs the 4-D extension of the two-dimensional (2-D) 8×8 approximate discrete cosine transform (ADCT) that has recently appeared in the literature. Motivated by the partial separability of the multidimensional spectrum of LFs, the proposed 4-D ADCT is obtained by cascading 2-D inter-view and 2-D intra-view transform stages. Software simulations are provided to confirm the performance of the 4-D ADCT based compression and comparisons are made with respect to 2-D inter-view only and 2-D intra-view only ADCT-based compression. Proposed digital architectures are validated using stepped hardware co-simulation on a Xilinx Virtex-7 VC-707 FPGA platform verifying 597 MHz maximum possible clock frequency, implying an ideal throughput of 18×103LFs/sec for performing 4-D ADCT on (8× 8×432×624×3) size LFs. When 10% of the ADCT coefficients per each (8×8×8×8) hypercube are retained sub aperture images show 38 dB average PSNR and 0.95 average SSIM.

A multi-port spatio-temporal noise-shaping ADC is proposed to process plane waves received by spatially-oversampled antenna arrays. In the proposed multi-port ADC, the desired plane waves are processed with a spatial low-pass frequency response whereas the noise and distortion are shaped with a spatial high-pass frequency response. By employing a first-order Butterworth filter, approximately circular passbands and stopbands are achieved for the signal and the noise transfer functions, respectively. The proposed noise-shaping system is designed in the TSMC 180 nm CMOS process, with ADCs and DACs modeled as noise sources. Circuit simulation results show that the proposed system can achieve a bandwidth of 50 MHz.

The superior performance of deep learning (DL) has sent shock waves in the machine learning community. The high adoption rate of DL has set new demands on computational throughput, latency, and power efficiency of the computing infrastructure. In addition to conventional approaches to acceleration of the inference component of DL systems based on GPUs, cloud computing, ASIC/FPGAs and custom vector processors (such as tensor processing units), there is renewed interest in high-frequency analog circuits for DL inference. Analog computing is a potential candidate for meeting challenging requirements in throughput, latency and power efficiency. Because DL inference has superior noise resilience and relatively low accuracy needs (typically less than 8 bits), analog circuits can provide a promising alternative to all-digital accelerators. This paper presents early work on the design of an analog CMOS accelerator that performs analog convolution and decision operations in parallel and in real-time by pairing a high-frequency operational amplifier-based CNN filtering kernel with a rectified linear unit (ReLu) non-linearity based on an active precision rectifier circuit. The analog accelerator was designed in a 45 nm CMOS process and simulated in Cadence Spectre. Image convolution results are presented and compared with MATLAB simulations. The proposed solution also employs Xilinx RF System-on-Chip (SoC) devices based on the Xilinx ZCU1285 RFSoC platform to interface digital inputs and outputs with the proposed RF-rate analog inference accelerator.

In this paper, we propose solutions to Maxwell's equations that can be computed using analog computers. Spatially-discrete time-continuous (SDTC) algorithms running on analog computers can be potentially faster and more energy-efficient than fully-discrete numerical solvers. The implementations of fully-discrete partial differential equation (PDE) solvers on high speed digital processors, such as graphics processing units (GPUs), take many clock cycles to compute a single temporal frame of the update equation and thus have relatively low equivalent bandwidths. Our approach is to directly implement temporal recursions in continuous-time by using analog circuits. Such circuits can have bandwidths that greatly exceed the equivalent bandwidths of GPUs. In particular, we propose two analog computing methods that compute the SDTC solutions to Maxwell's equations. In addition to Maxwell's equations, such platforms can be used to accelerate other hard computational problems that involve PDEs derived from continuous-time systems. In continuous-time in Laplace domain (CTLD) method (first approach), the spatial domain partial derivatives in the governing PDE are approximated using discrete finite differences, while applying the Laplace transformation along the time dimension. The resulting spatially-discrete time-continuous update equation is utilized to design an analog circuit that can compute the continuous-time solution. The all-pass delay approximate (APDA) method (second approach) replaces the discrete-time difference operators in the standard finite difference time domain (FDTD) cell (Yee cell) using continuous-time delay operators, which can be realized using analog all-pass filters. Both methods have been simulated using ideal analog circuits in Cadence Spectre for the Dirichlet, Neumann, and radiation boundary conditions. The performance of the proposed methods have been quantified using i) mean squared differences between the results and fully-discrete FDTD simulations, and ii) the noise to signal energy ratio. The CTLD and APDA methods are able to compute the solutions to Maxwell's equations with a noise energy to signal energy ratio γ better than -26 dB and -19 dB, respectively. Both methods have been extended to design analog circuits that compute the continuous-time solution of the 1-D and 2-D wave equations. The CTLD-based 1-D and 2-D analog wave equation solvers are able to compute the solutions with γ better than -72 dB and -60 dB, respectively. The APDA-based 1-D wave equation solver is simulated with a dominant-pole model (which better approximates the non-ideal circuit behavior) along with a propagation delay compensation technique. The non-ideal analog models compute the solution with a difference smaller than -13 dB (in terms of γ). Experimental results from a simplified board-level low-frequency implementation are also presented. The key challenges toward CMOS implementations of the proposed solvers are identified and briefly discussed with possible solutions.

A low-complexity wideband transmit beamformer is proposed using a digitally-fed uniform linear array of broadband Vivaldi antennas operating in the S-band. The proposed transmit beamformer employs a novel DSP feeding network based on a transmit-mode 2-D sparse finite-extent impulse response (FIR) filter having a planar passband in the 2-D frequency-wavenumber space. Electronic beam steering is achieved by changing the filter coefficients defined in closed-form and hard-thresholding (HT) is employed to obtain a sparse 2-D impulse responses of the filter. Full-wave electromagnetic simulations are used to obtain the far-field beam patterns produced by the 2-D sparse FIR filter in the frequency range 2-2.8 GHz for wideband signals with 33% fractional bandwidth. Computational complexity, beam directionality and side-lobe performance are investigated with varying HT along with quantitative comparisons with an equally selective wideband frequency-domain phased array.

Although a massive amount of bandwidth is available at mm-waves, physics dictates the use of legacy frequencies in the sub 6-GHz range. This necessitates dynamic spectrum access in the face of exponentially growing spectral demands. However, disorganized spectrum sharing causes interference, leads to a chaotic situation, and loss of capacity. Moreover, it is difficult to ensure that the primary users are compensated for sharing their licensed bands. We propose a Blockchain-based platform to address these limitations. A digital token, called spectral token, is introduced to validate and track the use of a licensed frequency band while enforcing sequential access to spectrum by secondary users to avoid interference. The proposed platform enables both advertising and sensing based spectrum sharing under different leasing policies. Such sharing and leasing policies are coded into smart contracts, which digitally enforce the contractual clauses of the leasing agreement. When a deal is made, the smart contract automatically transfers the spectral token between primary and secondary users within the agreed time frame while paying the primary user in cryptocurrency. We developed a proof of concept solution using the Ethereum Blockchain to demonstrate the utility of the proposed platform and its throughput and latency characteristics.

The need of highly directional communications at mmWave frequencies introduces high overhead for beam training and alignment, which makes the medium access control (MAC) a grand challenge. To harvest the gain for high performance transmissions in mmWave networks, we propose an efficient and integrated MAC design with the concurrent support of three closely interactive components: 1) an accurate and low-cost beam training methodology with a) multiuser, multi-level, bi-directional coarse training for fast user association and beam alignment and b) adaptive fine beam training with compressed channel measurement and multi-resolution block-sparse channel estimation in response to the channel condition and the learning from past measurements; 2) an elastic virtual resource scheduling scheme that jointly considers beam training, beam tracking and data transmissions while enabling burst data transmissions with the concurrent allocation of transmission rate and duration; and 3) a flexible and efficient beam tracking strategy to enable stable beam alignment with beamwidth adaptation and mobility estimation. Compared with literature studies, our performance results demonstrate that our design can effectively reduce the training overhead and thus significantly improve the throughput. Compared to 802.11ad, the training overhead can be reduced more than 60%, and the throughput can be more than 75% higher. In low SNR case, the throughput gain can be more than 90%. Our scheme can also achieve about 50% higher throughput in the presence of user mobility.

This paper proposes an architecture that reduces the complexity of traditional N-bit ADCs used in focal plane array (FPA) dish receivers by replacing them with multiport ADCs. The proposed ADC architecture uses a multi-dimensional (MD) noise-shaping method based on a Δ-Σ architecture for wideband RF signals that are received on the focal region of a parabolic dish/lens antenna. In the M-port noise shaping technique, the N-bit quantizers of conventional ADCs are replaced by 1-bit quantizers followed by a spatial feedback system based on a Δ-Σ architecture with spatial oversampling, which shapes the quantization noise out of the region of support (ROS) of the electromagnetic (EM) waves received from the dish. The paper discusses the case of a prime-axis pencil beam in detail for the simplified case of a linear FPA. Simulations for 2.1-5.1 GHz wideband dish signals show 16-element FPAs with oversampling ×l, ×2, and ×4 shows ADC effective number of bits (ENoB) improvements of 2.5 bits, 3.2 bits and 4.2 bits, respectively. Extensions to off-axis pencil-beams and rectangular FPAs will be considered in future work. Potential applications exist across microwave and mm-wave bands, for radio astronomy, radar, and wireless communications.

Light field signal processing allows manipulation of a rich set of information captured from a scene to achieve real-time depth filtering and occlusion suppression. Low-complexity four-dimensional infinite impulse response digital filters for simultaneous depth filtering and occlusion suppression over multiple depths in light fields are proposed. A low-complexity two-dimensional separable approach is employed to design the proposed filters having multiple frequency-planar pass-bands/stopbands in the four-dimensional spatial frequency domain, that can be electronically tuned to enhance/reject planar objects at multiple depths in a light field. Filter synthesis details are provided with specific design examples corresponding to 2-passband and 1-stopband cases. Numerically generated and Lytro camera captured light fields are used to verify the effectiveness of the proposed multi-depth-pass and multi-depth-reject filters. For synthetic light field inputs these filters confirm an average denoising, depth filtering and occlusion suppression performance of 20 dB, 20 dB, and 30 dB, respectively.

Two continuous-time mathematical computing methods are proposed for solving the multidimensional wave equation leading to realizable analog computing circuits. The proposed analog computing processors will potentially be able to solve a certain special classes of computational problems involving partial differential equations, which are defined from continuous-time systems. The new analog computing methods are first derived and physically implemented for the first-time using low-frequency operational amplifier circuits in order to experimentally verify the correctness of the proposed methods. Both algorithms approximate the spatial domain partial derivatives using discrete finite differences. The first method performs a direct Laplace transform (with respect to the time variable) on the resulting expression. The second method applies the finite difference along the time dimension and then replaces the discrete time difference with a continuous-time delay operator, which in turn, can be realized as an analog all-pass filter. Analog circuit architectures are introduced for different boundary conditions relevant to common electromagnetic simulation problems. A low frequency prototype of the analog wave equation solver (based on method 1) has been designed, realized and tested using board-level operational amplifier circuits. Test results and measurements are provided to demonstrate the wave propagation in the space-time domain.

We describe a current-mode multi-beam beamforming approach for 5G wireless applications based on a low-complexity approximate-DFT (a-DFT). Dynamic current mirrors are used to cancel errors in the current copying and scaling operations required to realize a-DFT matrices, thus resulting in an accurate and scalable architecture. The circuit design for the case of 8-point a-DFT has been validated with transistor-level simulations in the UMC 0.18 μm CMOS process.

This paper proposes a computational method for 2D 8×8 DCT based on algebraic integers. The proposed algorithm is based on the Loeffler 1D DCT algorithm, and it is shown to operate with exact computation—i.e., error-free arithmetic—up to the final reconstruction step (FRS). The proposed algebraic integer architecture maintains error-free computations until an entire block of DCT coefficients having size 8×8 is computed, unlike algorithms in the literature which claim to be error-free but in fact introduce arithmetic errors between the column- and row-wise 1D DCT stages in a 2D DCT operation. Fast algorithms are proposed for the final reconstruction step employing two approaches, namely, the expansion factor and dyadic approximation. A digital architecture is also proposed for a particular FRS algorithm, and is implemented on an FPGA platform for on-chip verification. The FPGA implementation operates at 360 MHz, and is capable of a real-time throughput of$3.6\cdot 10^8$2D DCTs of size 8×8 every second, with corresponding pixel rate of$2.3\cdot 10^{10}$pixels per second. The digital architecture is synthesized using 180 nm CMOS standard cells and shows a chip area of 7.41 mm$^2$. The CMOS design is predicted to operate at 893 MHz clock frequency, at a dynamic power consumption 13.22 mW/MHz$\cdot$V$_{sup}^2$.

This paper introduces a new method for computing matrix exponential based on truncated Neumann series. The efficiency of the method is based on smart factorizations for evaluation of several Neumann series that can be done in parallel and divided across different processors with low communication overhead. A physical realization on FPGA is provided for proof-of-concept. The method is verified to be advantageous over the usual Horner's rule approach for polynomial evaluation. The hardware verification shows a reduction of 62% in time required for processing for series approximations with 9 terms. Software verification demonstrates a 30% reduction in time compared to Horner's rule and the trade-offs between using a higher precision approach is illustrated.

An analog all-pass filter based transfer function synthesis method is proposed for realizing multifunctional microwave active circuits. An analog realization is obtained by replacing unit sample delays in an existing digital prototype with a second-order all-pass analog filter. A novel space time array processor (STAP) and a frequency and bandwidth agile multi-band filter have been simulated using the proposed transfer function synthesis method using measured S- parameters of a fabricated 130 nm second-order CMOS all- pass filter. Simulated array patterns of the STAP beamformer show improved side-lobe performance for better interference suppression and noise rejection. The tunability of the multi-band analog filter, in terms of the center frequency and the quality factor, is verified up to 8 GHz, which has potential applications in analog microwave front-ends.

A joint numerical representation based on both Gaussian and Eisenstein integers is proposed. This Gauss-Eisenstein representation maps complex numbers into four-tuples of integers with arbitrarily high precision. The representation furnishes the computation of the 3-, 6-, and 12-point discrete Fourier transform (DFT) at any desired accuracy. The associated fast algorithms based on the Gauss-Eisenstein integers are error-free up to the final reconstruction step, which can be realized in hardware as a multiplierless implementation. The introduced methods are compared with competing algorithms in terms of arithmetic complexity. We propose three FRS architectures based on the following methods: Dempster-McLeod representation, expansion factor, and addition aware quantization. The Gauss-Eisenstein 12-point DFT is physically realized on a Xilinx Virtex 6 FPGA device with maximum clock frequency of 302 MHz for the expansion factor FRS with real-time throughput of 3:62 × 109 coefficients/s. The FPGA verified digital designs were synthesized, mapped, placed and finally routed for 0:18mm CMOS technology assuming a 1.8 V DC supply employing Austria Micro Systems (AMS) standard-cell library (hitkit version 4.11). The routed ASIC is predicted to operate at a maximum frequency of 505 MHz for the expansion factor FRS with potential real-time throughput of 6:06 × 109coefficients/s.

The usage of linear transformations has great relevance for data decorrelation applications, like image and video compression. In that sense, the discrete Tchebichef transform (DTT) possesses useful coding and decorrelation properties. The DTT transform kernel does not depend on the input data and fast algorithms can be developed to real-time applications. However, the DTT fast algorithm presented in literature possess high computational complexity. In this paper, we introduce a new low-complexity approximation for the DTT. The fast algorithm of the proposed transform is multiplication free and requires a reduced number of additions and bit-shifting operations. Image and video compression simulations in popular standards show good performance of the proposed transform. Regarding hardware resource consumption for FPGA shows a 43.1% reduction in configurable logic blocks and ASIC place and route realization shows a 57.7% reduction in the area-time figure compared with the 2D version of the exact DTT.

Design approaches for radio frequency (RF) analog realization of two-dimensional (2-D) network-resonant plane-wave filters are discussed. The plane-wave filters having potential applications in electronically scanned wideband beamforming scenarios operate in spatially-discrete temporally-continuous 2-D mixed-domain as described by their recursive input-output relationships. The proposed approaches imply analog array processing architectures consisting of identical interconnected analog modules (AMs). A 65 nm CMOS circuit simulation of a single AM operating at 700 MHz is used to verify the 2-D plane-wave filter response and array pattern in the first approach. An all-pass filter based time delay approximation is used to design the AMs in the second approach, where a prototype CMOS all-pass filter operating at 5.6 GHz is simulated to verify the 2-D plan-wave filter frequency response and array pattern in closed-form.

An 8‐point discrete cosine transform (DCT) fast algorithm based on the Loeffler DCT factorisation and algebraic integer (AI) representation is proposed. The proposed algorithm is an error‐free implementation of the Loeffler algorithm and it is capable of computing the 8‐point DCT multiplierlessly. Decoding architectures are also proposed for mapping AI encoded quantities back to usual fixed point arithmetic using canonical signed digit representation and the expansion factor method. The proposed algorithm is mapped into systolic‐array digital architectures and physically realised as digital prototype circuits using field‐programmable gate array technology on a Reconfigurable Open Architecture Computing Hardware board and mapped to 0.18 μm complementary metal–oxide–semiconductor technology using AMS Encounter Digital Implementation libraries at 1.8 V supply.

In this paper, we present an overview of recent advances in multidimensional (MD) systems and signal processing. We focus on topics closely related to the four papers selected into the special session of “recent advances in multidimensional systems and signal processing” at ISCAS 2015. The paper starts with an overview of the theory of MD IIR digital filters and its applications ranging from image/videos of light-fields to microwave and mm-wave antenna array processing. State-space formulation for the realization of MD IIR notch filters is also discussed as applicable to image processing scenarios. Thereafter, new developments in visual tomography-based imaging systems that exploit MD signal processing towards safety and health applications are discussed. The paper also reviews new theoretical developments in modeling of physical systems. Recent advances in MD Kirchhoff circuit realizations for some physical systems including finite speed heat diffusion are reviewed.

RF-FPGAs and field-programmable filter arrays require tunable analog filters that can be digitally reconfigured in real-time to have several user-selected passbands and stopband notches. Such reconfigurable analog filters must operate in the microwave frequencies up to several GHz in order to meet the needs of emerging cognitive radio and reconfigurable radar front-ends. Tunable passive filters based on RF-MEMS, surface acoustic wave- and planar-technologies have been explored in the recent past to achieve this goal. In this paper, a novel RF-IC approach to design microwave filterbanks having multiple bands, each having independently tunable center frequency and quality factors, is proposed. The proposed technique is based on transfer function synthesis using first-order all-pass filters as a building block. Using measured data from a current-mode 130-nm CMOS allpass filter implementation, the feasibility of multi-band tunable filter arrays is simulated with a tuning range of 4 GHz.

The authors apply two approaches to reduce the computation time of the residual complexity similarity metric employed in image registration applications aimed at hardware‐based implementations with low‐complexity transforms. First, the similarity metric is computed in image sub‐blocks, which are subsequently combined into a global metric value. Second, the discrete cosine transform (DCT) needed in the computation of the similarity measure is replaced with multiplier‐free low‐complexity approximate transforms. The authors propose a new low‐complexity transform requiring only 18 additions in an 8 × 8 block and compare it to: the round DCT, the signed DCT, the Hadamard transform and the Walsh‐Hadamard transform. Detailed computational complexity analysis reveals that block‐wise processing alone reduces computational cost by a factor of 8‐9 for original DCT composed of multiplications and additions, and up to ≃4.90 when the proposed DCT is utilised; being the computation performed with additions only. Results obtained from computer simulated and realistic X‐ray images demonstrate block‐wise processing and approximate transforms result in successful image registration, making residual complexity similarity measure available to hardware‐accelerated fast image registration applications.

In this letter, we introduce a low-complexity approximation for the discrete Tchebichef transform (DTT). The proposed forward and inverse transforms are multiplication-free and require a reduced number of additions and bit-shifting operations. Numerical compression simulations demonstrate the efficiency of the proposed transform for image and video coding. Furthermore, Xilinx Virtex-6 FPGA based hardware realization shows 44.9% reduction in dynamic power consumption and 64.7% lower area when compared to the literature.

The discrete cosine transform (DCT) is a widely-used and important signal processing tool employed in a plethora of applications. Typical fast algorithms for nearly-exact computation of DCT require floating point arithmetic, are multiplier intensive, and accumulate round-off errors. Recently proposed fast algorithm arithmetic cosine transform (ACT) calculates the DCT exactly using only additions and integer constant multiplications, with very low area complexity, for null mean input sequences. The ACT can also be computed non-exactly for any input sequence, with low area complexity and low power consumption, utilizing the novel architecture described. However, as a trade-off, the ACT algorithm requires 10 non-uniformly sampled data points to calculate the eight-point DCT. This requirement can easily be satisfied for applications dealing with spatial signals such as image sensors and biomedical sensor arrays, by placing sensor elements in a non-uniform grid. In this work, a hardware architecture for the computation of the null mean ACT is proposed, followed by a novel architectures that extend the ACT for non-null mean signals. All circuits are physically implemented and tested using the Xilinx XC6VLX240T FPGA device and synthesized for 45 nm TSMC standard-cell library for performance assessment.

A CMOS wide-bandwidth first-order current-mode all-pass filter (APF) is discussed. The circuit consists of one transistor, a resistor, a grounded inductor, and a load. When used with a current mirror as the load, the current-mode filter exhibits a high output impedance, which is advantageous from an integration point of view and enables this configuration to be cascaded with current-mode circuits. The operation of the proposed circuit is experimentally validated. The APF implemented in IBM 0.13-μm CMOS was measured to have the pole-zero pair located at 8.32 GHz and to achieve a 55 ps group delay while consuming 19 mW from a 1.5-V supply. This paper experimentally demonstrates a CMOS APF that operates at multi-GHz frequencies and achieves the highest delay-bandwidth products of the published CMOS first-order APFs known to the authors.

Cognitive radio relies on accurate spectrum sensing for increasing the spectral efficiency of wireless networks. A novel array processing scheme is proposed based on a uniform linear array (ULA) of circularly-polarized spiral antennas having frequency range 2–6 GHz, which is used in conjunction with digital beam filters having 2-D IIR transfer functions for accurately and efficiently placing radio sources in wireless environment. Algorithms such as cyclostationary feature extraction is employed at beamformer to measure energy and realize feature/modulation detection, which in turn allows classification of a wireless environment. Simulation examples are provided for demonstrating the low-complexity directional feature detector with applications towards enhancing access to radio spectrum. Examples showing classification of sources by direction, frequency channels and modulation type in the 2–4 GHz band at SNR=6 dB are given.

A spatially discrete temporally continuous antenna array analog signal processing scheme that can produce highly selective hexagonal beams is proposed. A three dimensional (3-D) infinite impulse response (IIR) filter transfer function having hexagonal beam shaped passbands in the 3-D space-time frequency domain ω is introduced. A hexagonal beam passband in ω produces a hexagonal radio beam in the array pattern, and having closely packed multiple hexagonal beams, one can optimally sense a given sky area in a typical radar/microwave imaging application. The proposed array processing scheme employs analog RF circuits for achieving scaling, summing and time delay as building blocks for the signal processing operation. The 3-D IIR filter transfer function is derived by considering an example 10th-order 1-D Butterworth prototype polynomial.

The application of multi-dimensional (MD) infinite impulse response (IIR) space-time beam filters in radio source localization in cognitive radio (CR) environments is investigated. Knowledge of the position of radio sources in a CR network leads to the detection of white spaces in the MD frequency domain, thereby creating more opportunistic links for the secondary users. The use of MD IIR beam filters is motivated by their very low computational complexity and small side lobe levels compared to digital phased arrays. As a proof-of-concept, the two dimensional (2-D) propagation scenario including at least two receiver stations and a data fusion station, which combines the direction of arrival (DOA) estimates from the two receiver stations, to yield a position estimate, is considered. Each receiver station employs a uniform linear array (ULA) of antennas and a steerable 2-D IIR beam filter and provides information pertaining to peak energy directions. First order 2-D IIR beam filters are shown to provide acceptable DOA estimates with a SNR of 6 dB. The peak energy direction information leads to both position and MD white space detection.

An electronically steerable broadband radio frequency (RF) filter-sum beamforming filter using 1st-order all-pass filters is proposed. The beamforming filter has the 2-D transfer function Ha (zx, sct), which uses M-section cascaded 1st-order all-pass filters and analog combiners as building blocks. Beam steering is achieved by tuning the group delay of the all-pass filters via a control voltage. For beam directions ψ ≤ 20ofrom array broadside, M = 1 provides close to ideal broadband response, and 120°. The array factor of the beamformer is evaluated using 65 nm CMOS BSIM 4 simulations of the all-pass filters and a 4-channel RF combiner for a linear antenna array of 4 antennas and is shown to provide steerable beams at 1 GHz. The CMOS simulations verify a broadband response from DC to 1 GHz.

An area efficient row-parallel architecture is proposed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) for image and video processing. The proposed architecture computes 8 × 8 2-D DCT transform based on the Arai DCT algorithm. An improved fast algorithm for AI-based 1-D DCT computation is proposed along with a single channel 2-D DCT architecture. The design improves on the four-channel AI DCT architecture that was published recently by reducing the number of integer channels to one and the number of eight-point 1-D DCT cores from five down to two. The architecture offers exact computation of 8 × 8 blocks of the 2-D DCT coefficients up to the FRS, which converts the coefficients from the AI representation to fixed-point format using the method of expansion factors. Prototype circuits corresponding to FRS blocks based on two expansion factors are realized, tested, and verified on FPGA-chip, using a Xilinx Virtex-6 XC6VLX240T device. Post place-and-route results show a 20% reduction in terms of area compared to the 2-D DCT architecture requiring five 1-D AI cores. The area-time and area-time2complexity metrics are also reduced by 23% and 22% respectively for designs with eight-bit input word length. The digital realizations are simulated up to place and route for ASICs using 45 nm CMOS standard cells. The maximum estimated clock rate is 951 MHz for the CMOS realizations indicating 7.608·109pixels/s and a 8 × 8 block rate of 118.875 MHz.

Multidimensional signal processing (MDSP) is the extension to conventional signals and systems to multiple dimensions. The theoretical treatment of multidimensional systems is important for broad areas such as image/video processing, array processing, biomedical imaging, radio-astronomy, space imaging, radar imaging, and multimedia signal processing. MDSP is typically realized in circuitry using analog, digital and mixed-signal devices. The teaching of MDSP theory is typically attempted at the graduate level where students build on fundamentals of digital and analog signal processing and filter design, which they learn as part of standard undergraduate material. An advanced graduate course is described that covers both theory and circuit realization of MDSP algorithms, aimed at the entry-level graduate student audience. The course overview and summarized inventory of concepts is provided. The teaching philosophy and our vision of combined approach to research and teaching and the transfer of scientific findings from research program to mainstream education is discussed. Our combined experience at the University of Akron and University of Calgary is shared for benefit of the circuits and systems community.

Industry demand for highly-skilled digital VLSI and embedded systems engineers has made the teaching of design a challenging task for undergraduate educators. Increasingly challenging electronic design automation (EDA) environments call for a variety of skills in engineering graduates which necessitate not only industrial skills but also fundementals in basic science and digital design. These urgent needs are addressed by creating a digital logic design course taught at the freshman level that introduces students to VHDL design of digital VLSI systems while including core concepts. Critical thinking, logic synthesis and circuit innovation take priority over conventional analysis techniques. This case study includes example design projects that have been successfully implemented at The University of Akron.

In this paper, a multi-encoding approach using wavelet based subband coding is proposed to accomplish error free calculations from exact representation of Daubechies 4-tap wavelet filter coefficients using the algebraic integer (AI) representation. By mapping the irrational coefficients to a convenient AI basis, the proposed architecture is designed employing a parallel channel model having two data paths carrying integer sequences. The computations done in the AI architecture are exactly accurate and are done entirely in a multiplier-free circuit. The design is implemented on a Xilinx Virtex-6 device at 172 MHz and hardware co-simulated with an ML605 board at 100 MHz. AI mapping facilitates simplicity and error-free calculations. The proposed architecture has a single final reconstruction step (FRS). Booth encoding has been adopted at the FRS to minimize the error which can be incurred at this point. This paper provides a hardware and power analysis for different bit lengths. An example output image sequence for the mandrill image is also provided.

A two-dimensional (2D) space-time (ST) delay operator D2DST[·] and a novel discrete-space-continuous-time (DSCT) CMOS VLSI implementation at radio frequency (RF) is proposed. The proposed delay operator is able to delay 2D ST antenna array signals along space and time and can be used as a building block in 2D ST array processing algorithms. A 2D non-separable DSCT transfer function (TF), ΦApp(zx, sct) is used to approximate the ideal 2D ST delay represented by the 2D TF equation. A passive frequency planar transformation followed by bilinear transform along spatial dimension is used to derive ΦApp(zx, sct) starting from a 1D passive all-pass prototype. The 2D delay D2DST[·] is proposed to be realized using an array of identical analog modules (AMs). A CMOS VLSI circuit operating at RF is proposed for each AM. Magnitude and phase frequency responses of a single AM operating at 1 GHz is obtained using 65 nm TSMC CMOS simulations in Cadence and compared with the theoretical responses. The 2D phase frequency response of D2DST[·] is obtained using the CMOS simulated response of a single AM.

A novel parallel semi-systolic semi-scanned array architecture is proposed for the implementation of four-dimensional (4-D) IIR filters. These filters have emerging applications in computed tomography (CT), volumetric ultrasound, and light field processing for computer vision. The proposed architecture can be applied to a broad class of 4-D IIR filters, and we show results for a frequency-planar depth-selective filter. Our implementation is on a Xilinx Virtex-6 xc6vsx315t-3ff1156 FPGA, and is suitable for filtering of a N1× N2= 4 × 4 aperture light field camera input. Results compare favourably with ideal and FPGA-hardware measured outputs, with an N1N2factor increase in throughput compared to a corresponding fully raster-scanned design clocked at the same clock frequency.

The potential use of multi-dimensional (MD) signal processing concepts and 1-D tunable bandpass filtering (BPF) for 2-D space-time (ST) spectrum sensing in a cognitive radio environment is proposed. The 2-D ST spectrum sensing allows the secondary users to search and detect white spaces along different spatial directions at a given time instance. This 2-D ST interrogation of the radio environment enables efficient sharing of primary frequency bands over multiple spatial directions in different instances of time. The use of frequency agile antennas is highlighted to mitigate interferences at known frequencies. Broadband/intermediate-frequency (IF) and analog/digital realizations of 2-D ST filters are proposed to perform the directional enhancement of signals. A low complexity highly-selective tunable 1-D digital BPF is proposed to be used with energy detection to perform spectral sensing along the required direction in space. The tunable BPF eliminates the need of computationally intensive high resolution FFT for frequency scanning. A prototype FPGA implementation of the BPF operating at 66 MHz is used to study the effect of finite precision arithmetic with a word length of 8 bits.

An algebraic integer (AI)-based time-multiplexed row-parallel architecture and two final reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row-column transforms, leading to an 8 × 8 2-D DCT that is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on: 1) optimized Dempster-Macleod multipliers, and 2) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on field-programmable gate array (FPGA) chip. Six designs, for 4-bit and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented, and measured. The maximum clock rate and block rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of 8 × 307.787≈2.462 GHz if eventually embedded in a real- time video-processing system. The equivalent frame rate is about 1187.35Hz for the image size of 1920 × 1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.

A broadband digital beamforming algorithm is proposed for directional filtering of temporally-broadband bandpass space-time plane-waves at radio frequencies (RFs). The enhancement of desired waves, as well as rejection of undesired interfering plane-waves, is simulated. A systolic- and wavefront-array architecture is proposed for the real-time implementation of second-order spatially-bandpass (SBP) 2-D infinite impulse response (IIR) beam filters having potential applications in broadband beamforming of temporally down-converted RF signals. The higher speed of operation and potentially reduced power consumption of the asynchronous architecture of wavefront-array processors (WAPs) in comparison to the conventional synchronous hardware has emerging applications in radio-astronomy, radar, navigation, space science, cognitive radio, and wireless communications. Further, the bit error rate (BER) performance improvement along with the reduced computational complexity of the 2-D IIR SBP frequency-planar digital filter over digital phased array feed (PAF) beamformer is provided. A nominal BER versus signal-to-interference ratio (SIR) gain of 10-16 dB compared to case where beamforming is not applied, and a gain of 2-3 dB at approximately half the number of parallel multipliers to digital PAF, are observed. The results of application-specific integrated circuit (ASIC) synthesis of the digital filter designs are also presented.

The application of a 2D IIR digital filter, having a broadband beam-shaped 2D passband, is investigated for beamforming in narrowband wireless communication systems. Specifically, their use for interference rejection in a carrier-modulated communication system is proposed. Monte-Carlo simulations of the bit-error-rate, as a function of the antenna-side signal-to-interference ratio for a 1 GHz BPSK-modulated source operating at 25 Mbps over a 32 element array, confirm a signal-to-noise-plus-interference ratio (SINR) system gain of 10 to 15 dB relative to the non-beamformed case. The proposed method allows a single broadband beamformer to operate over a wide frequency bandwidth containing multiple frequency-agile channels. This particular application is potentially well-suited for cognition-enabled base stations.

A continuous-time discrete-space 2D IIR fan filter is proposed for ultra-wideband beamforming for uniform linear arrays of antennas. The proposed signal-flow-graph replaces sampled unit-delays in a 2D FIR digital prototype fan filter using time-delays of the same duration using an ideal delay line. Thereafter, ideal delays are approximated using an RC-active VLSI circuit consisting of high-order all-pass filters aimed at the 90 nm CMOS technology. The paper covers transfer function design, 2D input spectra in continuous-time, delay approximation, CMOS all-pass circuits and simulation. Finally, a prototype with fan axis directed along θ = 30° (from temporal frequency axis) and half fan angle ε = 6° is simulated and the frequency response from DC to 3.6 GHz is obtained using data from a BSIM4 model of a 10th- order all-pass filter. The proposed novel analog 2D fan filters are free of aliasing, quantization noise, switching power consumption, and do not require an array of high-speed analog-to-digital converters.

A time-multiplexed row-parallel architecture is pro- posed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) of images and video sequences. The architecture is based on the Arai algorithm with AI encoding. This leads to an 8×8 2-D DCT which is entirely free of quantization errors. The error free coefficients may be converted into a regular arithmetic format using a final reconstruction step (FRS) at the output stage. The accuracy of the FRS allows each of the 64 coefficients to have its precision set independent of other coefficients without the leakage of quantization noise between coefficient channels. Our architecture leads to low-noise applications in digital video compression, coding, and other image processing applications that rely on the fast systolic computation of the 2-D DCT. A prototype of the 2-D DCT is physically realized, tested, and verified on chip, using a Xilinx Virtex-4 S×35-10ff668 device. The maximum clock rate was Fclock= 121 MHz, implying an equivalent frame sample rate of 466 Hz, for an image frame size of 1920 × 1080, which is a common high definition video format.

This paper investigates the potential of emerging asynchronous quasi delay insensitive (a-QDI) logic devices for the realization of high-speed low-power 2D infinite impulse response digital beam filters. Recently proposed raster-scanned hardware architectures based on direct-form I and wave-digital realization are extended to clock-free asynchronous logic using state-of-the-art asynchronous field programmable gate arrays from Achronix Semiconductor. For the specific class of 2D IIR beam filters based on raster-scanned hardware, it is shown using extensive experimental work that direct-form I architectures greatly benefit from the adoption of a-QDI logic over standard clocked (synchronous) digital circuits while wave-digital filters show no difference in performance. To the author's knowledge, the proposed 2D IIR hardware circuits are currently the only available realization of 2D IIR filters in the literature based on the new clock-free a-QDI paradigm.

A raster-scanned architecture is proposed for the real-time implementation of 2D/3D wave-digital filters corresponding to doubly(resistively)-terminated LC-ladder frequency-planar networks. Such WDFs have directional filtering applications in space-time in areas such as ultra-wideband acoustical beamforming, video processing, and ultrasonic imaging. The implementation of zero initial conditions for both rectangular/linear arrays is considered. An example of 2nd-order 2D IIR frequency-planar filter design and FPGA-implementation for space-time plane-wave filtering over uniform linear arrays is provided. The proposed FPGA circuit is simulated, using 2D impulse response tests and interference rejection models, to confirm correct operation of the WDF architecture. The FPGA implementation was targeted to a Xilinx Sx35-10ff668 device. Timing analysis shows a critical path delay of 145 ns, implying a real-time clock frequency of 6.9 MHz, and for 32 sensors, a linear-frame sampling frequency of 215 kHz.

A massively-parallel polyphase systolic array processor is proposed for broadband beamforming using a 3D IIR space-time digital frequency-planar filter that is capable of operating at a throughput of M 2D spatial frames every clock cycle, where M is the number of (poly)phases. The method achieves an M-fold increase in throughput relative to previously known architectures, and has the potential to achieve highly-selective broadband radio-frequency (RF) digital beamforming at frame rates that are several times greater than the clock rate of the VLSI system. The practical real-time performance of the processor is demonstrated using a 3×3 section of a systolic array (that is part of a larger systolic N1× N2≈100 × 100 system), consisting of a locally-interconnected matrix of 9 identical fully-pipelined speed-optimized two phase (M=2) parallel processors on a Xilinx Sx35 FPGA device, having a corresponding measured spatial frame-rate of 100 million frames/second, when clocked at 50 MHz.

Broadband space-time spiral-waves have received much attention in bioelectromagnetics and chaotic systems. They occur as propagating waves in non-linear active-media, such as the surface of the heart. A novel first-order 2D IIR practical-BIBO stable non-separable digital filter, based on a 2D signal derived from a circular-array of sampled sensors, is proposed for the real-time broadband highly-selective enhancement of broadband Archimedean spiral-waves and circular-waves in the presence of undesired spiral-waves. The proposed filter employs the spatio-temporal helix-transform, which is a form-preserving transform that converts a noncomputable 2D difference-equation into an equivalent 1D difference-equation. This transformation converts a noncomputable 2D IIR digital filter into a computable, and practically useful, 1D IIR approximate equivalent filter. The selective enhancement of broadband Gaussian spiral-wave and circular-waves are demonstrated where the desired spiral-waves are shown to be enhanced by approximately 22 dB. The computational complexity of the proposed filter is low, employing 3 multiplications and 6 additions/subtractions per output sample.

High-speed radio-frequency (RF) applications of 2D HR real-time spatio-temporal digital filters in smart antenna arrays require architectures that are capable of high throughputs. A novel systolic-array architecture is proposed for such filters that operate at a throughput of one-frame-per-clock-cycle (OFPCC). This architecture uses a 2D extension of a well-known ID look-ahead (LA) speed maximization technique to achieve low critical path delays. A method is proposed, simulated, implemented and tested for the broadband beamforming of temporally down-converted RF signals. Temporal down-conversion is used in direct-conversion receivers, implying potential wireless applications. The prototype is operational on a Xilinx 4vsx35ff668-10 FPGA device at a clock frequency of 100 MHz, thereby achieving the required real-time OFPCC frame rate of 100 Million frames/sec. Implementations using high-speed VLSI technologies are envisaged and will facilitate 2D IIR filtering at GHz frame-rates.

A form-preserving 2D z-domain helix transform is proposed for the synthesis of computable practical-BIBO stable 2D recursive filters computed over uniformly-spaced circular input arrays. The helix transform converts non-computable 2D IIR filters into computable and BIBO stable 1D filters in order to facilitate the required 2D IIR filter transfer function in space-time. Further, a novel scanned-array architecture of the proposed 2D helical circular array processors is proposed that is suitable for VLSI implementation.

A highly-directional FPGA-based broadband beam former is proposed using a novel 3D IIR plane-wave digital filter. This filter acquires the 3D spatio-temporal input signals from spatially-rectangular arrays of sensors that are scanned by only one time-multiplexed A/D converter. The proposed architecture employs a novel scanned-array 3D parallel vector-processor (VP), clocked at 80 MHz, and has the potential to achieve real-time broadband plane-wave filtering on a single low-cost integrated circuit at spatial frame-rates of 19 kHz over a 64 by 64 spatial broadband sensor array.