We propose a method to visualize the measured gaze distribution of observers asked to perceive the dynamism of a subject’s movements in a sports video. This visualization method uses a three-dimensional heatmap on the surface of a human body model. An existing method generates the heatmap using gaze measurements on a body surface in a still image. However, this method does not handle changes over time in a subject’s posture in a video. Furthermore, this method does not visualize gaze in the region surrounding the subject’s body. Our method calculates the angle between the gaze direction and vertex position to visualize the gaze distribution on the body surface and surrounding regions. Experimental results demonstrated that our method visualizes not only the gaze distribution on the surface region but also that in the surrounding region. We also verified that it is possible to visualize the gaze distribution over a subject’s movements in a video without depending on changes in posture using a standard human body model.

The demand for executing neural network (NN) learning and inference on edge devices is increasing. Memristor crossbar (MC) devices in neuromorphic computing (NC) provide a promising solution for accelerating NNs. However, immature fabrication technology makes faulty memristors inevitable, and the presence of stuck-at faults (SAFs) in MC devices substantially reduces the inference accuracy of NC System. The existing fault-resilient methods, which depend on mapping and retraining algorithms, cause costly and time-consuming processes with hardware overhead. This paper proposes a reliability-aware design framework for an NC system utilizing MC devices by combining fault-resilient training and IC-specific mapping. First, we apply fault-resilient training to enhance the robustness of the NN model. SAF-injected training is developed in this phase to mitigate the effects of SAFs. Then we map the weights of the trained model to MCs. The proposed framework preserves the inference accuracy without re-training, even though MCs are suffered from SAFs. Our proposed method is assessed using two different NN applications across two distinct datasets. The experimental results show that the proposed framework achieves high inference accuracy for several differently faulty MCs and enhances the reliability of NC system.

Hyperdimensional computing (HDC) can efficiently perform various cognitive tasks efficiently by mapping data to hyperdimensional vectors with thousands to tens of thousands of dimensions. However, the primary operations of HDC—Bind, Permutation, and Bound—need to be executed more efficiently on a standard CPU platform. This study introduces a novel computational platform, EcoFlex-HDP, specifically designed for HDC. EcoFlex-HDP exploits the parallelism and high memory access efficiency of HDC operations to achieve low computation time and energy consumption, outperforming the CPU. Furthermore, it can work cooperatively with a CPU, enabling integration with existing software, providing flexibility to apply new algorithms, and contributing to the development of an HDC ecosystem. Through experimental evaluations with a Cortex-A9 processor, HDC operations were shown to be accelerated by a maximum of 169 times. Furthermore, EcoFlex-HDP was confirmed to improve the energy-delay product by up to 13,469 times when training an image recognition task. All source codes for our platform and experiments are available at https://github.com/yuya-isaka/EcoFlex-HDP.

Research on dedicated circuits for multiply and accumulate processing, which is vital to machine learning (ML), using memristors has attracted considerable attention. However, memristors have unknown operating principles, making it challenging to create compact models with sufficient accuracy. This study proposes a compact modeling method based on Gaussian process for memristors. Although various ML-based modeling methods have been proposed, only the reproduction accuracy has been evaluated using SPICE circuit simulator, and long learning times have not been sufficiently discussed. The proposed method reduces the learning and inference times using a Gaussian process with considering sparsity. An evaluation using data from memristor devices obtained by actual measurements demonstrates that the proposed method achieves over 2,629 times faster than conventional method using long short-term memory (LSTM). Moreover, inference on a commercial SPICE simulator can be performed with the same accuracy and computation time. All experimental environments, including the source code, are available at https://github.com/sntnmchr/SGPR-memristor/blob/main/README.md.

The population protocol model is a computational model for passive mobile agents. We address the leader election problem, which determines a unique leader on arbitrary communication graphs starting from any configuration. Unfortunately, self-stabilizing leader election is impossible to be solved without knowing the exact number of agents; thus, we consider loosely-stabilizing leader election, which converges to safe configurations in a relatively short time, and holds the specification (maintains a unique leader) for a relatively long time. When agents have unique identifiers, Sudo et al.(2019) proposed a protocol that, given an upper bound $N$ for the number of agents $n$, converges in $O(mN\log n)$ expected steps, where $m$ is the number of edges. When unique identifiers are not required, they also proposed a protocol that, using random numbers and given $N$, converges in $O(mN^2\log{N})$ expected steps. Both protocols have a holding time of $Ω(e^{2N})$ expected steps and use $O(\log{N})$ bits of memory. They also showed that the lower bound of the convergence time is $Ω(mN)$ expected steps for protocols with a holding time of $Ω(e^N)$ expected steps given $N$. In this paper, we propose protocols that do not require unique identifiers. These protocols achieve convergence times close to the lower bound with increasing memory usage. Specifically, given $N$ and an upper bound $Δ$ for the maximum degree, we propose two protocols whose convergence times are $O(mN\log n)$ and $O(mN\log N)$ both in expectation and with high probability. The former protocol uses random numbers, while the latter does not require them. Both protocols utilize $O(Δ\log N)$ bits of memory and hold the specification for $Ω(e^{2N})$ expected steps.

We investigate crash-tolerant perpetual exploration algorithms by myopic luminous robots on ring networks. Myopic robots mean that they can observe nodes only within a certain fixed distance ϕ, and luminous robots mean that they have light devices that can emit a color from a set of colors. The goal of perpetual exploration is to ensure that robots, starting from specific initial positions and colors, move in such a way that every node is visited by at least one robot infinitely often. As a main contribution, we clarify the tight necessary and sufficient number of robots to realize perpetual exploration when at most f robots crash. In the fully synchronous model, we prove that f+2 robots are necessary and sufficient for any ϕ ≥ 1. In the semi-synchronous and asynchronous models, we prove that 3f+3 (resp., 2f+2) robots are necessary and sufficient if ϕ = 1 (resp., ϕ ≥ 2).

Summary In this work, we study the gathering problem to make multiple agents, who are initially scattered in arbitrary networks, meet at the same node. The network has agents with unique identifiers (IDs), and of them are weakly Byzantine agents that behave arbitrarily, except for falsifying their identifiers. These agents behave in synchronous rounds, and they may start an algorithm at different rounds. Each agent cannot leave information at a node. We propose herein a deterministic algorithm that efficiently achieves gathering with a simultaneous termination having a small number of non‐Byzantine agents. The proposed algorithm concretely works in rounds if the agents know the upper bound on the number of nodes, and at least non‐Byzantine agents exist, where is the length of the largest ID among agents, and is the number of rounds required to explore any network composed of nodes. The literature presents two efficient gathering algorithms with a simultaneous termination. The first algorithm assumes that agents know the number of nodes and achieves the gathering in rounds in the presence of any number of Byzantine agents, where is the length of the largest ID among non‐Byzantine agents. The second algorithm assumes both that agents know and that at least non‐Byzantine agents exist, and it achieves the gathering in rounds. The proposed algorithm is faster than the first existing algorithm and requires fewer non‐Byzantine agents than the second existing algorithm if is given to agents. We propose herein a new technique to simulate a Byzantine consensus algorithm for synchronous message‐passing systems on agent systems to reduce the number of agents.

Statistical wafer-level variation modeling is an attractive method for reducing the measurement cost in large-scale integrated circuit (LSI) testing while maintaining the test quality. In this method, the performance of unmeasured LSI circuits manufactured on a wafer is statistically predicted from a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in wafer. However, actual wafers may have discontinuous variations that are systematically caused by the manufacturing environments, such as shot dependence. In this study, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into the systematic discontinuous and global components to improve the estimation accuracy. An evaluation performed using an industrial production test dataset shows that the proposed method reduces the estimation error for an entire wafer by over 33% compared to conventional methods.

Although automotive semiconductors must comply with the standard dynamic part average testing (DPAT) defined by the Automotive Electronics Council, it remains challenging to detect outliers that deviate from the spatial trend within a wafer. Outlier detection using Gaussian process (GP) regression has recently been proposed and outperformed DPAT. However, the detection performance degrades when faulty large-scale integrations are densely included in the regression. Furthermore, the applicable test items are limited because of the long computation time for regression. We propose an outlier detection method by applying ensemble learning to GP regression for simultaneously improving the detection performance and shortening the learning time. Experimental results on industrial production test data demonstrate that the proposed method improves the robustness against latent faulty chip detection by 15.6% while reducing the computation time by 98.6% compared with the conventional GP-based method.

Abstract The distributed ledger or blockchain technologies originated from the Bitcoin have been rapidly widespread in recent years. However, it also gives incentive to malicious users who would like to break the system or take advantage of it (steal money, hide some information stored in the ledger, isolate a particular node from the rest of the network, and so forth). Thus, research focusing on overcoming potential attacks to distributed ledgers is required. In this article, we focus on attacks that damage underlying networks of distributed ledgers. Underlying networks offer useful communication primitives such as an atomic broadcast, however, such attacks may degrade the property of the primitives and make distributed ledgers relying on the primitives no longer work. Hence we should design algorithms to make the distributed ledgers still work even when some attacks degrade the primitives. As the first study for such situations, we consider a problem to implement distributed ledgers tolerating the degradation of an underlying atomic broadcast service that distributed ledgers are relying on. We consider the case where the uniform agreement property of the atomic broadcast is degraded, and propose new algorithms that could ensure to reach eventual consistency despite degraded atomic broadcast.

In this paper, we propose a novel method for predicting the characteristic failure rate from a small amount of data with high accuracy using the posterior distribution of the Gaussian process. In the proposed method, using multiple lots, a local pattern on the wafers is estimated from the measurement results of the target-probe test item for failure-rate prediction. For failure-rate prediction, the global trend of each wafer is predicted by the Gaussian process using WAT data and superimposed on the local pattern. The proposed method derives the failure rate of each die based on the posterior distribution using the Gaussian process in the global trend calculation. Experiments using industrial semiconductor manufacturing data demonstrate that the proposed method can reduce the estimation error by approximately 70% compared to a conventional method.

We study the gathering problem to make multiple agents initially scattered in arbitrary networks gather at a single node. There exist k agents with unique identifiers (IDs) in the network, and f of them are weakly Byzantine agents, which behave arbitrarily except for falsifying their IDs. The agents behave in synchronous rounds, and each node does not have any memory like a whiteboard. In the literature, there exists a gathering algorithm that tolerates any number of Byzantine agents, while the fastest gathering algorithm requires Ω( f 2) non-Byzantine agents.

The matrix-vector product is the most essential operation in the weight calculation of deep learning, and greatly impacts the calculation speed and power consumption of neural network circuits. A memristor is one of the most promising components used to efficiently develop matrix-vector products. However, it has been pointed out that memristors have a severely low write endurance limitation and large variation during operation owing to their manufacturing immaturity. While an algorithm-based fault tolerance method has thus far been proposed to enhance the reliability by applying checksum function and online testing, the effectiveness of such the function remains limited because it can apply only the forward propagation and multiple hard faults cannot be repaired. This paper proposes an extension of the conventional method to achieve a more robust fault-tolerant method for memristor-based neural network circuits. Numerical experiments using the Hopfield network and three-layered neural network demonstrate that the proposed method achieves 5.25% and 1.88% higher classification accuracies compared with a conventional fault-tolerant method, respectively.

With the expansion of the semiconductor supply chain, recycled field-programmable gate arrays (FPGAs) have become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the presence of known fresh FPGAs (KFFs) as the training data used for machine-learning-based classification, which is an impractical assumption. In this study, we propose a novel KFF-free recycled FPGA detection method based on an unsupervised anomaly detection scheme. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes two recycled FPGAs from 10 fresh FPGAs. In contrast, a conventional KFF-free recycled FPGA detection method results in certain misclassification.

This research work presents a novel method for the detection of recycled field-programmable gate arrays (FPGAs). In this method, delay information of all paths in look-up tables (LUTs) of configurable logic blocks in the FPGAs is analyzed exhaustively by employing an advanced ring oscillator (RO) design. Although the proposed X-FP characterization technique can accurately capture the aging degradation of each path of all LUTs in the FPGA, it considerably increases the RO measurement cost. Furthermore, X-FP yields a large amount of measurement data causing the "curse of dimensionality" problem when used as a feature vector in the machine learning (ML) based detection system. To combat these challenges while applying the X-FP characterization, we additionally propose two techniques for realizing accurate and efficient recycled FPGA detection: compressed sensing (CS) based prediction and with-in die (WID) modeling based feature engineering. In CS-based estimation, we incorporate the virtual probe (VP) technique for low-cost RO measurement. The WID modeling properly reflects the process variation of each FPGA, and model parameters extracted by the modeling are utilized as a feature vector in the ML-based detection to classify target FPGAs as either fresh or aged. Through experiments using commercial FPGAs, we demonstrate that the proposed method combining the VP and WID modeling on the X-FP characterization achieves high-accuracy recycled FPGA detection at a low measurement cost.

Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for wafer-level spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.

In this paper, we focus on graph class identification problems in the population protocol model. A graph class identification problem aims to decide whether a given communication graph is in the desired class (e.g. whether the given communication graph is a ring graph). Angluin et al. proposed graph class identification protocols with directed graphs and designated initial states under global fairness [Angluin et al., DCOSS2005]. We consider graph class identification problems for undirected graphs on various assumptions such as initial states of agents, fairness of the execution, and initial knowledge of agents. In particular, we focus on lines, rings, $k$-regular graphs, stars, trees, and bipartite graphs. With designated initial states, we propose graph class identification protocols for $k$-regular graphs, and trees under global fairness, and propose a graph class identification protocol for stars under weak fairness. Moreover, we show that, even if agents know the number of agents $n$, there is no graph class identification protocol for lines, rings, $k$-regular graphs, trees, or bipartite graphs under weak fairness. On the other hand, with arbitrary initial states, we show that there is no graph class identification protocol for lines, rings, $k$-regular graphs, stars, trees, or bipartite graphs.

In this study, a novel method for the detection of recycled field-programmable gate arrays (FPGAs) is proposed. This method is based on with-in die (WID) process variation model over an exhaustive path characterization [referred to as exhaustive-fingerprint (X-FP)]. In the proposed method, X-FP is capable of fully characterizing frequencies on all paths in look-up tables (LUTs) using advanced ring oscillator (RO) design to exhaustively capture deterioration by aging. Although machine learning (ML)-based classification is often used for recycled FPGA detection, X-FP yields a large amount of measurement data, which cannot be appropriately handled by typical ML algorithms, if they are used as a feature vector. The proposed method utilizes the model parameters extracted by WID variation modeling as the feature vector in the ML algorithm. These model parameters simply and accurately represent the process variation for each FPGA. In this way, the ML-based fresh/recycled classification works very well with the simple feature vector. Experiments using 50 commercially available FPGAs reveal that X-FP can capture the degradation effects, which cannot be detected by conventional methods. Moreover, the WID modeling achieves 99.6% feature size reduction per one FPGA. It also demonstrates that the model parameters exhibit good distance properties between fresh and aged FPGAs. Additionally, the ML-based classification which uses a one-class support vector machine can successfully detect 2 aged FPGAs (48 h accelerated aging) without any misclassification and another 4 aged FPGAs (24 h accelerated aging) with a very few misclassifications as fresh FPGAs.

In this paper, we focus on the uniform bipartition problem in the population protocol model. This problem aims to divide a population into two groups of equal size. In particular, we consider the problem in the context of arbitrary communication graphs. As a result, we investigate the solvability of the uniform bipartition problem with arbitrary communication graphs when agents in the population have designated initial states, under various assumptions such as the existence of a base station, symmetry of the protocol, and fairness of the execution. When the problem is solvable, we present protocols for uniform bipartition. When global fairness is assumed, the space complexity of our solutions is tight.

Device identification using challenge-response pairs (CRPs), in which the response is obtained from a physically unclonable function (PUF), is a promising countermeasure for the counterfeit of integrated circuits (ICs). To achieve secure device identification, a large number of CRPs are collected by the manufacturers, thereby increasing the measurement costs. This paper proposes a novel scheme, which employs a logic built-in self-test (LBIST) circuit, to efficiently collect the CRPs during production tests. As a result, no additional measurement is required for the CRP collection. In addition, the proposed technique can counter machine-learning (ML) attacks because of the complicated relationship between challenge and response through the LBIST circuit. Through the proof-of-concept implementation, in which a field-programmable gate array (FPGA) is used, we demonstrate the PUF performance can be evaluated by a test pattern generated by the LBIST circuit. Furthermore, the vulnerability due to ML attacks using a support vector machine (SVM) and random forest (RF) is lowered by more than two times compared to the naive usage of PUF.

While silicon carbide (SiC) MOSFETs can tolerate high-voltage and high-temperature operations with low power loss, long-term reliability of SiC devices is of a concern due to the threshold voltage shift caused by bias temperature instability (BTI). Although the industry-standard BTI characterization method can measure long-term threshold voltage fluctuation, it is hard to quantify the fluctuation under the actual switching operation. In this paper, we propose a long-term BTI characterization method that reflects a realistic switching operation of power devices. We demonstrate the effectiveness of the proposed method using a commercial SiC MOSFET and then discuss the suitable model to represent BTI on the basis of the measurement data.

In this paper, we focus on the uniform bipartition problem in the population protocol model. This problem aims to divide a population into two groups of equal size. In particular, we consider the problem in the context of \emph{arbitrary} communication graphs. As a result, we clarify the solvability of the uniform bipartition problem with arbitrary communication graphs when agents in the population have designated initial states, under various assumptions such as the existence of a base station, symmetry of the protocol, and fairness of the execution. When the problem is solvable, we present protocols for uniform bipartition. When global fairness is assumed, the space complexity of our solutions is tight.

Reliability of embedded memory is critical for system-on-chips (SoCs). Aging-induced faults manifest in field, and they affect the reliability of embedded memories which occupy the most area of an SoC. By performing a proactive approach that repairs aged memory words in use, the probability of fault occurrence should be minimized. In this paper, we proposed an in-field strategy that proactively repairs aged words as well as correctable words. The reliability is enhanced further by combining an aging test, an in-field repair, and an error correction technique. An adaptive reconfiguration of the memory words, including aged words, correctable words, and uncorrectable words, is implemented with small overhead. A 3-state model that identifies memory cells as healthy, aged, or faulty is newly introduced, and the reliability evaluation using this model demonstrates the effectiveness of the proposed strategy.

Hardware Trojan refers to a malicious modification of an integrated circuit (IC). To eliminate the complications arising from designing an IC which includes a Trojan, it is suggested to apply Trojan detection as early as at register-transfer level (RTL). In this paper, we propose a hardware Trojan detection framework which consists of both RTL and gate-level classification using machine learning approaches to detect hardware Trojan inserted at RTL. In the experiment, all Trojan benchmarks were successfully identified without false positive detection on non-Trojan benchmark.

As integrated chip (IC) is one of the most essential components for communication devices, enhancing the integrity of hardware security is essential to prevent any security breach. Implantation of Hardware Trojan (HT) into the IC is one of the most threatening hardware security risks since most of the IC design and fabrication phases are outsourced to third-party foundries. Gate-level netlist inspection is utterly important as HT could be easily hidden among the primitives of the circuit which makes the detection challenging. Previously, HT detection methods for gate-level netlist were mainly based on either net testability or net's structural features. In this paper, we proposed to consolidate these two types of features into a single feature vector to train supervised machine learning classifiers. We also analyzed the performance of the classifiers based on different combinations of features using Minimum Redundancy and Maximum Relevance (mRMR) technique. Using the best feature combination, we achieved a 99.85% True Positive Rate (TPR), 99.95% True Negative Rate (TNR) and 99.90% accuracy (ACC). The results were validated using 10-fold cross-validation.

We propose a novel recycled field programmable gate array (FPGA) detection method based on with-in die (WID) variation modeling. Model parameters extracted by the WID modeling simply but accurately represent the process variation of each FPGA, and thus, by using the model parameters as feature vector, machine learning effectively classifies target FPGAs into fresh or aged. Through experiment on commercial circuit simulator, the proposed method achieves 99.6% feature vector size reduction per FPGA with showing 96.0% detection accuracy; while our silicon result using commercial FPGA demonstrates the model parameters have a good distance properties between fresh and aged.

Recently, the design and manufacturing of ICs are mostly outsourced to third-party design houses and foundries due to the tedious and costly processes. This makes the IC design and manufacturing chain to be vulnerable to hardware Trojan intrusion by third-party vendors with malicious intentions. In design phase, gate-level netlist checking is important to spot the existence of any suspicious nets in the netlist. Thus, highly Trojan-correlated features and efficient learning algorithms are needed to classify each net effectively. Testability measures are proven as efficient features for Trojan net classification, but the problem of imbalanced training data remains. Also, the extracted Sandia Controllability and Observability Analysis Program (SCOAP) values are restricted to a low threshold. In this paper, we extract the SCOAP values without a limited threshold and normalize the extraction data using Adaptive Synthetic Sampling Technique (ADASYN) for better learning in supervised algorithms. Using the best performing classifier which is Bagged Trees, we are able to achieve overall 99.97% True Positive Rate (TPR), 99.81% True Negative Rate (TNR) and 99.9% Accuracy (ACC) with the results validated using 10-fold cross-validation.

Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled fieldprogrammable gate arrays (FPGAs). On the other hand, it requires a large number of measurements of ROs for all FPGAs before shipping, and thus leads to measurement cost inflation. In this research, we propose a low-cost recycled FPGA detection method using a virtual probe (VP) technique based on compressed sensing. The VP technique enables us to accurately predict the spatial process variation on a die from a very small number of sample measurements. Using the estimated process variation as a supervisor, machine-learning algorithm classifies target FPGAs into recycled or fresh. Through experiments using circuit simulation, our method achieves more than 96% detection accuracy using one-class support vector machine where only 20% samples of the frequency are used at the best case. Silicon measurement results on Xilinx Artix-7 FPGAs also demonstrate the efficiencies of the proposed method.

The Asian Test Symposium (ATS) provides an international forum for engineers and researchers from all countries of the world, especially from Asia, to present and discuss various aspects of device, board and system testing with design, manufacturing and field considerations in mind. ATS has been annually held for 27 years at 23 cities (four cities, Beijing, Shanghai, Hiroshima, and Taipei hosted ATS twice). Fig. 1 shows the venues of ATS including three coming ATS. During these years, ATS has been provided the opportunity to deeply discuss test technology and enhance networking in the research and geographical regions. ATS will continuously play this role in the future.

We focus on a uniform partition problem in a population protocol model. The uniform partition problem aims to divide a population into k groups of the same size, where k is a given positive integer. In the case of k=2 (called uniform bipartition), a previous work clarified space complexity under various assumptions: 1) an initialized base station (BS) or no BS, 2) weak or global fairness, 3) designated or arbitrary initial states of agents, and 4) symmetric or asymmetric protocols, except for the setting that agents execute a protocol from arbitrary initial states under weak fairness in the model with an initialized base station. In this paper, we clarify the space complexity for this remaining setting. In this setting, we prove that P states are necessary and sufficient to realize asymmetric protocols, and that P+1 states are necessary and sufficient to realize symmetric protocols, where P is the known upper bound of the number of agents. From these results and the previous work, we have clarified the solvability of the uniform bipartition for each combination of assumptions. Additionally, we newly consider an assumption on a model of a non-initialized BS and clarify solvability and space complexity in the assumption. Moreover, the results in this paper can be applied to the case that k is an arbitrary integer (called uniform k-partition).

Resistive random access memory (ReRAM) has several attractive features such as high-storage-density and high-switching with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance than that of dynamic random access memory (DRAM) or static random access memory (SRAM). Hence, error correction code (ECC) circuit is indispensable for realizing reliable ReRAM storage. For this purpose, in this paper, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with highly frequent write operations are implemented by the conventional CMOS technology and the others are implemented by the memristors to keep a balance between the area overhead and reliablity. Through numerical experiments, we demonstrate that the proposed ECC circuits have less area and high reliability compared to ECC circuits that are fully implemented by memristors, and achieves less area while preserving the reliability compare to ECC circuits that are fully implemented by CMOS technology, where an area reduction of 19.9% is achieved for data words with 1,024 bits and the area reduction is improved as the data bit length increases.

A hardware Trojan (HT) denotes the malicious addition or modification of circuit elements. The purpose of this work is to improve the HT detection sensitivity in ICs using power side-channel analysis. This paper presents three detection techniques in power based side-channel analysis by increasing Trojan-to-circuit power consumption and reducing the variation effect in the detection threshold. Incorporating the three proposed methods has demonstrated that a realistic fine-grain circuit partitioning and an improved pattern set to increase HT activation chances can magnify Trojan detectability.

In test of large scale integration (LSI) circuit, test escape is always regarded as a critical issue since significant cost is imposed to manufacturing cost. In this paper, we propose a novel outlier screening method for test escape. The proposed method exploits variational autoencoder (VAE) that is widely used to design complex generative model in artificial neural network field. While a typical autoencoder (AE) simply extracts features of training data, the VAE does it as probability distribution, and thus it can avoid potential risk of overfitting by using the probability distributions as a regularizer. Moreover, the proposed method effectively detects test escapes by utilizing the probability distributions as likelihood function of good chips. Through experiments using an industrial production test data, we demonstrate that the proposed method detects test escapes more than approximately 8.5 times as compared to that using a conventional AE-based method.

High detection sensitivity in the presence of process variation is a key challenge for hardware Trojan detection through side channel analysis. In this work, we present an efficient Trojan detection approach in the presence of elevated process variations. The detection sensitivity is sharpened by 1) comparing power levels from neighboring regions within the same chip so that the two measured values exhibit a common trend in terms of process variation, and 2) generating test patterns that toggle each cell multiple times to increase Trojan activation probability. Detection sensitivity is analyzed and its effectiveness demonstrated by means of RPD (relative power difference). We evaluate our approach on ISCAS'89 and ITC'99 benchmarks and the AES-128 circuit for both combinational and sequential type Trojans. High detection sensitivity is demonstrated by analysis on RPD under a variety of process variation levels and experiments for Trojan inserted circuits.

The sensitive identification and detection of hardware Trojans in ICs without a golden reference constitutes a key challenge. Traditional circuit partitioning and side-channel analysis techniques fall short of perfect sensitivity and accuracy and rely on golden references. In this work, a novel layout-aware clock tree driven circuit partitioning is coupled with an algorithm that selects transition delay fault test patterns that will deliver equal power on partitions. The circuit partitioning through the clock tree results in minimal hardware additions that can be effected through ECO. The selection of pairs of power uniform small regions results in reduction of inter-die variation effects, thus delivering increased detection sensitivity. The comparison for equal power of numerous pairs thoroughly perturbs the circuit under various activation conditions, resulting in elevated sensitivity and accuracy while obviating the need for reliance on Golden ICs. We evaluate our approach on ISCAS89 and ITC benchmarks and AES circuits for both combinational and sequential type Trojans. Experimental results show that our approach can effectively detect Trojans with ratios to circuit area as low as 0.023%.

In this paper, we consider a uniform bipartition problem in a population protocol model. The goal of the uniform bipartition problem is to divide a population into two groups of the same size. We study the problem under various assumptions: 1) a population with or without a base station, 2) weak or global fairness, 3) symmetric or asymmetric protocols, and 4) designated or arbitrary initial states. As a result, we completely clarify constant-space solvability of the uniform bipartition problem and, if solvable, propose space-optimal protocols.

We present a new self-stabilizing 1-maximal matching algorithm that works under the distributed unfair daemon for arbitrarily shaped networks. Our algorithm is efficient (its stabilization time is O(e) moves, where e denotes the number of edges in the network). Besides, our algorithm is optimal with respect to identifiers locality (we assume node identifiers are distinct up to distance three, a necessary condition to withstand arbitrary networks).

Reliability of memory is crucial to overall reliability of SoCs. In our previous work, we enhanced reliability through an adaptive combination of repair and memory word correction, however, it is restricted to the identification of faulty memory words. In this work, we enhance reliability further by considering identification of not only faulty words, but aged words as well. We propose a novel method that adaptively assigns aged and faulty words to functional repair or correction based on their vulnerabilities.

Embedded memory is extensively being used in SoCs, and is rapidly growing in size and density. To keep up with the development pace of nanoscale devices, enhancement methods for yield and reliability must overcome the barriers set forth by advent of new technology. To address the issue of reliability, periodic online field test and repair are implemented by using synergistic approach of employing redundancy and ECC to repair or correct both hard errors and soft errors. In this paper, an online remap strategy for memory repair, which ensures ‘fresh’ memory words are always used until the spare words run out, is proposed. The improvement of reliability for memory architectures and the area overhead introduced by the proposed scheme is evaluated.

Multi/many-core processors allow to handle path delay faults although the number of paths exponentially grows with the circuit size. This paper proposes an efficient path delay fault simulation that identifies all the robust and non-robust testable path delay faults for each test pattern. The simulation result is expressed by a scalable data structure only proportional to the numbers of gates and test patterns. The proposed simulation uses two types of parallelism, bit- and thread-parallelism, while considering efficient usage of multiple computing units and SIMD units which is resulting in a very fast simulation. Experimental results demonstrate the efficiency of the proposed method identifying all the robust and non-robust testable paths for a large number of test patterns. In addition, the simulation surpasses a commercial logic simulator which just processes a part of the proposed method.

This paper presents a scan-based BIST architecture for FPGAs used as application-specific embedded devices for low-volume products. The proposed architecture efficiently utilizes memory blocks, instead of logic elements, to build up BIST components such as LFSR, MISR and scan chains for test points. It also provides enhanced scan functionality for test points and performs a hybrid test application of LOC and enhanced scan to improve delay test quality. Experimental results show that the proposed BIST architecture achieves high delay test quality with efficient resource utilization.

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.

In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.

This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircrafts, or medical equipments would not allow any interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure prediction technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms and the testing environment of voltage and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement technique considering the variation due to voltage and temperature and 2) an adaptive test scheduling that gives more test chances to more probable degrading parts. Experimental results show the required memory space and area cost for implementing the proposed technique.

For accurate failure prediction, it is important to eliminate the environmental delay variations from the measure delays for capturing the actual delay shift caused by aging. This paper presents a novel test pattern optimization method to reduces spatial and temporal temperature variations during delay test.

Faster-than-at-speed testing is an effective approach to screen small delay defects (SDDs) and increase test quality and in-field reliability. This paper presents a novel framework of faster-than-at-speed test to minimize the slack of the sensitized path for each fault. The basic strategy is to use multiple faster-than-at-speed test timings with endpoint masking for each pattern. By performing a detailed analysis of the sensitized path delay for active faults and active endpoints in each pattern, we can minimize the slack for the detectable faults while preventing a large increase in pattern count. We also present methods to maximize the sensitized path delay and further reduce the pattern count under a constraint on the allowable slack size, instead of minimizing the slack. Experimental results for ITC'99 benchmark circuits show the effectiveness of the proposed methods in terms of slack size and sensitized path delay for detectable faults, statistical delay quality level (SDQL) and pattern count.

A globally-asynchronous and locally-synchronous (GALS) system has been known as a realistic hardware design solution for many difficulties such as global clock network that arise due to the continuous scaling of semiconductor technology. Although a full scan design method for synchronous circuits is applied to asynchronous circuits to achieve the same testability of their combinational parts, the overhead is extremely high. To reduce the overhead, several full scan design methods have been proposed but they cannot guarantee complete test. In this paper, we propose a bipartite full scan design as a new DFT method for asynchronous circuit where we guarantee complete test for both combinational and sequential parts of circuits with area and performance overhead comparable to the previous best method in terms of overhead.

This paper presents a seed ordering and selection method in LFSR-reseeding-based BIST for high quality delay test. The proposed method selects seeds based on the gain in the sum of the longest path lengths sensitized by seeds, which is highly correlated with statistical delay quality level (SDQL). We also evaluate the contributions of pseudo-random patterns in several mixed-mode BIST approaches and the impact of base seed set on the final quality of selected seeds. Experimental results show that the proposed method intelligently selects seeds and obtains significant reduction in seed count under SDQL constraint within a reasonable time.

With the exponential increase of transistor counts, scan design encounters several problems such as large test data volume, long test application time and high test power. In this paper, we propose a new method to reduce test data volume, test application time and also average and peak power during test. The proposed method is based on a scan chain disabling technique where only one internal sub scan chain is active at a time. Though our method makes a sacrifice of test generation time, instead, we can achieve reduction of test data volume, test application time and test power together. Experimental results show the effectiveness of the proposed method.

Timing-aware ATPGs are being developed to detect small delay faults for high defect coverage for current nanometer VLSI design. However, it results in a large test set compared with test generation targeting traditional fault models. This paper proposes a method to get a limited size of test set with high delay test quality based on statistical delay quality level (SDQL).

This paper presents a novel failure prediction testing technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircraft or medical equipments would not allow any interruptive erroneous responses during a system operation, which might result in catastrophe. Therefore, we propose a failure prediction delay testing technique that is applied during the time when the system is not working, such as power-on/-off times. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms. Since the testing environment of voltage and temperature is uncontrollable in the field, an accurate delay measurement considering the variation due to voltage and temperature should be developed. Moreover, we propose an adaptive test scheduling that gives more test chances to more possible degrading parts for improving detecting efficiency.

It is well known that the test mode exceeds the functional mode in power consumption, which is not uniformly distributed within the circuit. The non-uniformity in spatial power distribution may cause localized heating and temperature differences within the circuit. Since gate delay depends on junction temperature, thermal differences within the circuit may lead to erroneous pass or fail in at-speed testing. This paper first discusses the importance of spatial thermal uniformity for high quality and accurate at-speed testing. The paper also presents an X-filling technique that minimizes the spatial temperature variation within the circuit while preserving the overall circuit power consumption at low level. Experimental results show the effectiveness of the proposed method compared to the existing X-filling techniques.

This paper proposes a secure scan design method which protects the circuits containing secret information such as cryptographic circuits from scan-based side channel attacks.The proposed method prevents the leakage of secret information by partial scan design based on a balanced structure. We also guarantee the testability of both the design under test and DFT circuitry, and therefore, realize both security and testability. Experiments for RSA circuit shows the effectiveness of the proposed method.

In this paper, the authors propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency in a sense that the proposed method completely resolves the problem of error masking. Moreover, the proposed method adds only observation points to the original design, and it enables at-speed testing and does not induce delay overhead

Aggressive processor design methodology using high-speed clock and deep submicrometer technology is necessitating the use of at-speed delay fault testing. Although nearly all modern processors use pipelined architecture, no method has been proposed in literature to model these for the purpose of test generation. This paper proposes a graph theoretic model of pipelined processors and develops a systematic approach to path delay fault testing of such processor cores using the processor instruction set. The proposed methodology generates test vectors under the extracted architectural constraints. These test vectors can be applied in functional mode of operation, hence, self-test becomes possible. Self-test in a functional mode can also be used for online periodic testing. Our approach uses a graph model for architectural constraint extraction and path classification. Test vectors are generated using constrained automatic test pattern generation (ATPG) under the extracted constraints. Finally, a test program consisting of an instruction sequence is generated for the application of generated test vectors. We applied our method to two example processors, namely a 16-bit 5-stage VPRO pipelined processor and a 32-bit pipelined DLX processor, to demonstrate the effectiveness of our methodology

This paper presents efficient method to extract constraints from a test program template and synthesize a test program using constraint circuits. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and observation of test responses for a module under test (MUT). The constraint circuit represents a relation between operand values and inputs/output of the MUT, therefore it enables to obtain operand values using a standard automatic test pattern generator. Experimental results show that the proposed method generates accurate and compact constraint circuits, and we obtain high fault efficiency.

This paper introduces a new concept of hierarchical testability called Single-Port-Change (SPC) two-pattern testability. We propose a non-scan design-for-testability (DFT) method which makes each path that needs to be tested in a data path SPC two-pattern testable. An SPC two-pattern test guarantees robust (resp. non-robust) test if the path is robust (resp. non-robust) testable. Since it is easy to find justification paths for SPC two-pattern tests at register-transfer level, the proposed DFT method can reduce hardware overhead compared to that of our previous DFT method for arbitrary two-pattern tests. Furthermore, we propose a method to reduce test generation effort by removing a subset of sequentially untestable paths from targets of test generation. Experimental results show that the proposed method can reduce hardware overhead without losing the quality of test.

This paper presents a methodology for testing a superscalar processor using functional mode of operation for the performance oriented delay faults. The functional mode test issues for superscalar are discussed. A graph based model is developed and used to develop for the generation of test programs.

This paper presents a method of template generation for instruction-based self-test of processor cores. A test program template is an instruction sequence with unspecified operands, and represents paths for justification of test patterns and propagation of test responses for a module under test (MUT). In order to justify value of MUT inputs, we introduce a concept of adjacent registers of the MUT that makes it possible to consider input spaces of the MUT determined by signals from other modules as well as signals directly from registers. We efficiently generate possible templates considering dependence of instructions each of which invokes one or more data transfers between registers. The method also generates multiple templates in effective order to detect faults, which may cover different input spaces, and therefore, different detectable fault sets.

This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm good performance and practicality of our approaches.

This paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-testability while generating control sequences for justification and propagation at register-transfer level. Since the method fully utilizes functions of controllers as well as datapaths, it achieves small area overhead.

This paper presents a software-based self-testing methodology for delay fault testing. Delay faults affect the circuit functionality only when it can be activated in functional mode. A systematic approach or the generation of test vectors, which are applicable in functional mode, is presented. A graph theoretic model (represented by IE-Graph) is developed in order to model the datapath. A finite state machine model is used for the controller. These models are used for constraint extraction so that the generated test can be applied in functional mode.

We introduce a class of sequential circuits with internally switched balanced structure which allows test generation with combinational test generation complexity. The proposed class includes any other known classes with this feature. This paper also considers faults in hold registers and switches regarded as macros, while any related work does not consider faults in such macros. Experimental results show the effectiveness of using combinational test generation for the circuits with internally switched balanced structure.

We show that the test generation problem for all single stuck-at-faults in sequential circuits with internally balanced structures is reduced into the test generation problem for single stuck-at-faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at-faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at-faults on separable primary inputs.

Weak testability is a testability measure for register-transfer level (RTL) data paths. If a data path satisfies weak testability, for each hardware element of the data path, there exist paths from some primary inputs to the element to justify some values on its output and paths from the hardware element to some primary outputs to propagate some values on its output. For a weakly testable data path, a sequential ATPG tool can generate a test sequence with high fault efficiency in a short test generation time. In this paper, we introduce a notion called test knowledge, use of which by commercial ATPG tools can further decrease the test generation time and increase the fault efficiency in weakly testable data paths. This test knowledge is information which is relevant to structure of weakly testable data paths, and also easy to find. Use of this test knowledge to facilitate the test generation and increase the testability of data path is established in experimental results.

We present a high-level synthesis method that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for nonscan design. We introduce a design objective for weak testability that is a condition on resource sharing sufficient for weak testability: We propose a heuristic synthesis algorithm that generates a weakly testable data path while minimizing area under a performance constraint.

We present a new non-scan DFT technique for register-transfer (RT) level data paths. In the technique, we add thru operations to some operational modules to make the data path easily testable. We define a testable measure, weak testability, and consider the problem to make the data path weakly testable with minimum hardware overhead. We also define a measure to estimate the test generation time. Experimental results show the effectiveness of our technique and the proposed measure.

This paper considers distributed algorithms for distributed mobile systems. Many distributed algorithms have been designed for distributed systems consisting of static computers only. But most of them cannot be directly applied to mobile systems. This paper proposes a model of mobile systems. Management of movements of mobile hosts is abstracted in our model to simplify design of algorithms for mobile systems. This paper also defines the snapshot problem, one of the fundamental problems, on the model. The problem requires to find a strongly consistent configuration in which topological consistency is satisfied in addition to causal consistency. Furthermore, this paper presents a snapshot algorithm for mobile systems.