Network functions and service function chaining are prevalent in cloud and ISP networks. In traditional software-based solutions, scaling up the capacity of these functions requires a large number of server cores. However, edge clouds are severely resource-constrained in terms of space, power, and budget, so traditional methods incur a high cost. We present Dejavu, a system that can offload a service chain to a programmable switch to achieve high performance and resource efficiency. Our system can compose multiple network functions into a single program that preserves the original chaining requirements, and exploit features of the switch ASIC to efficiently deploy the composed program on a single switch.

A string similarity measure quantifies the similarity between two text strings for approximate string matching or comparison. For example, the strings "Sam" and "Samuel" can be considered similar. Most existing work that computes the similarity of two strings only considers syntactic similarities, e.g., number of common words or q-grams. While these are indeed indicators of similarity, there are many important cases where syntactically different strings can represent the same real-world object. For example, "Bill" is a short form of "William". Given a collection of predefined synonyms, the purpose of the paper is to explore such existing knowledge to evaluate string similarity measures more effectively and efficiently, thereby boosting the quality of string matching.

To bridge the gap between limited energy supplies of the sensor nodes and the system lifetime, duty-cycle Wireless Sensor Networks (WSNs) with data aggregation are studied in this paper. We proposed a load-balanced and latency-efficient data aggregation scheduling for duty-cycled WSNs. A shortest path tree (SPT) is used as the routing structure for data aggregation scheduling. In SPT, parent-children assignments are well-designed to assign nodes from level h+1 to the parents at level h such that every parent has a balanced load, while reducing the sleep latency which is a period of time for a sender to wait for its parent to be active. Finally, through the simulation and comparisons, we prove the effectiveness of our approach.

This paper presents a fully integrated CMOS IEEE 802.11b/g WLAN radio transceiver chip with a novel local oscillator (LO) leakage auto calibration scheme. The transceiver chip is based on direct-conversion transmitter and receiver architecture and integrated in 0.25mum CMOS process. The noise figure is less than 5dB in a receive path. The inherent LO-leakage of direct-conversion transmitter is cancelled perfectly by using the proposed auto calibration method. The consumption currents of the receiver and transmitter are 120mA and 110mA at 2.5V power supply, respectively. Many kinds of cards and APs, which is made of this radio chip and homemade BB+MAC chip, have come into market.

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18/spl mu/m CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.