Since the end of 2019, the world has been caught in the crisis of the COVID-19 which is a serious epidemic disease. This paper seeks to come up with a fast and efficient COVID-19 detection and monitoring easy to use system which can be used in the facilities of densely populated areas, such as community centers and school clinics, to quickly identify suspected COVID-19 patients. This system could detect the probability of a person getting infected by COVID-19 using an android smartphone and thermal camera. Three types of data are collected from users: breathe sound, thermal video, and health status. Generally, the breathe audio and thermal video are preprocessed into two-time series, which indicate the breath status of the user. Then, the two series are inputted into the Bidirectional Gated Recurrent Unit (BI-GRU) neural network model separately to get the infection rates. Since the real data is difficult to get due to privacy reasons, a synthetic dataset is generated based on mathematical equations to train the model. For health status, the application requires the user to fill a questionnaire and calculates an infection rate through a medical prediction model. Finally, the two values from the machine learning model and the infection rate from the user report are added together with weight to calculate the final predictive infection rate.

This paper numerically investigates the spatial ergodicity of radar scattering from randomly rough ocean surface. Based on the accurate full-wave multi-level steepest decent-sparse matrix canonical grid (MLSD-SMCG) method and Monte Carlo simulation, we simulate the L-band normalized radar scattering coefficients from one-dimensional (I-D) rough ocean surfaces with different radar illumination sizes. According to the simulation results, it is found that: For the scattering angle less than 85°, the normalized bistatic radar scattering coefficient from ocean surface with radar illumination size no less than $16\lambda$ has good spatial ergodicity. Also, the emissivities from ocean surfaces with sizes exceeding $64\lambda$ manifest spatial ergodicity if the measurement accuracy of emissivity is less than the order of magnitude of 10 −4 .

In this paper, we present the statistical characteristics of Non-Gaussian sea surfaces, and find suitable statistical indicators to distinguish the rough surfaces generated by different parameters. Firstly, according to the sea surface height and wave spectrum, the rough sea surface is modeled. Then the non-Gaussian rough sea surface is constructed by using the SAR geometry. Finally, the roughness index is generated according to the SAR imaging results. The method can allow more degrees of freedom when generating a non-Gaussian rough sea surface, rather than just specifying the difference of skewness and kurtosis. Results analysis verifies the effectiveness of the proposed method.

The electromagnetic scattering computation of three-dimensional object located on ocean surface is studied.The electromagnetic scattering of object, sea surface and the interaction between them are computed based on the geometric optic, the physical optic, the shooting and bouncing ray. The scattering from electrically large ship and the coupling scattering between the ship and sea surface is calculated. The method introduced in this paper has important theoretical in realistic ocean remote sensing and detection of military targets located on ocean surface.

Traditional DRAM-based memory systems are facing two major scalability issues. First, the memory wall problem becomes a major performance bottleneck. Second, conventional memory systems consume increasing power as the capacity increases, which could be as much as 40% of the total system power. These issues hinder the scaling of DRAM-based memory systems. Fortunately, emerging memory technologies, such as high bandwidth memory (HBM) and phase change memory (PCM), have the potential to solve these scalability issues. However, there is no single memory technology that can overcome these issues together. Therefore, a hybrid memory system could be a promising way to build a high-performance, large-capacity, and energy-efficient memory system. To achieve this goal, we propose a cost-effective and energy-efficient architecture for HBM/PCM memory systems, called Dual Role HBM (DR-HBM). In DR-HBM, the HBM plays two roles and is divided into two parts. A small portion of which, called HBM cache, is used as a cache for the PCM. The remaining HBM is used as a part of main memory. Furthermore, the HBM cache is also used to track page hotness without additional hardware support. Hot pages will be migrated to HBM when they are evicted from the HBM cache. The experimental results show DR-HBM outperforms two state-of-the-art hybrid memory systems, CAMEO [1] and RaPP [2]. Compared to the baseline in which both HBM and PCM are architected as a part of main memory without page migration, DR-HBM improves the performance by 63% on average.

In this paper, we present a stripmap-mode raw data generator that accounts for trajectory deviations and antenna pointing errors with a nonzero squint angle for an extended scene, which is more realistic for airborne SAR system. The raw data acquired under the acquisition Doppler (AD) geometry rather than a standard cylindrical reference system. The approach utilizes one-dimensional azimuth Fourier domain processing followed by range time-domain integration. It has a higher computationally efficiency than the time domain method. Some simulation results are finally presented to demonstrate the effectiveness of the proposed algorithm.

Die-stacked DRAM (a.k.a., on-chip DRAM) provides much higher bandwidth and lower latency than off-chip DRAM. It is a promising technology to break the "memory wall". Die-stacked DRAM can be used either as a cache (i.e., DRAM cache) or as a part of memory (PoM). A DRAM cache design would suffer from more page faults than a PoM design as the DRAM cache cannot contribute towards capacity of main memory. At the same time, obtaining high performance requires PoM systems to swap requested data to the die-stacked DRAM. Existing PoM designs fall into two categories – line-based and page-based. The former ensures low off-chip bandwidth utilization but suffers from a low hit ratio of on-chip memory due to limited temporal locality. In contrast, page-based designs achieve a high hit ratio of on-chip memory albeit at the cost of moving large amounts of data between on-chip and off-chip memories, leading to increased off-chip bandwidth utilization and significant system performance degradation.To achieve a similar high hit ratio of on-chip memory as page-based designs, and eliminate excessive off-chip traffic involved, we propose SELF, a high performance and bandwidth efficient approach. The key idea is to SElectively swap Lines in a requested page that are likely to be accessed according to page Footprint, instead of blindly swapping an entire page. In doing so, SELF allows incoming requests to be serviced from the on-chip memory as much as possible, while avoiding swapping unused lines to reduce memory bandwidth consumption. We evaluate a memory system which consists of 4GB on-chip DRAM and 12GB off-chip DRAM. Compared to a baseline system that has the same total capacity of 16GB off-chip DRAM, SELF improves the performance in terms of instructions per cycle by 26.9%, and reduces the energy consumption per memory access by 47.9% on average. In contrast, state-of-the-art line-based and page-based PoM designs can only improve the performance by 9.5% and 9.9%, respectively, against the same baseline system.

A stripmap-mode raw data generator of an extended scene taking into consideration trajectory deviation with a non-zero squint angle is proposed. The approach utilizes a new approximation for trajectory deviations in the conical reference system. It relies on one-dimensional azimuth Fourier domain processing followed by range time-domain integration. Several simulation results are finally presented in order to demonstrate the effectiveness of the proposed approach.

In virtualization platforms, host-side storage caches can serve virtual machines (VM) disk I/O requests, which originally target network storage servers. When these requests hit host-side caches, network and disk access latencies are obviated, and thus VMs perceive improved storage performance. VM migration is common in cloud environments, however, VM migration does not transfer host-side cache states. As a result, a newly migrated VM suffers performance degradation until the cache is fully rebuilt. The performance degradation period can be hours long if the cache is naturally warmed up. Employing existing cache warm-up solutions such as migrating host-side cache and Bonfire, VMs may either have a prolonged total migration time or undergo a performance degradation period of tens of minutes due to the warm-up caused storage contention. We propose Successor, which proactively warms up caches of destination hosts before migration completes. Specifically, accessibility of destination hosts during migration enables Successor to parallelize cache warm-up and VM migration. Compared with migrating host-side cache and Bonfire, Successor achieves zero VM-perceived cache warm-up time with low resource costs and performance penalties. We have implemented a prototype of Successor on QEMU/KVM based virtualization platform and verified its efficiency.

DRAM cells leak charge over time, causing stored data to be lost. Therefore, periodic refreshes are required to ensure data integrity. Modern DRAM usually refreshes cells at rank level, resulting in an entire rank being unavailable during a refresh period. As DRAM density keeps increasing, more rows need to be refreshed during a single refresh operation, which causes higher refresh latency and significantly degrades the overall memory system performance. To mitigate DRAM refresh overhead, we propose a caching scheme, called Rank-level Piggyback Caching, or RPC for short, based on the fact that ranks in the same channel are refreshed in a staggered manner. The key idea is to cache the to-be-read data in a rank (e.g. Rank 1) to its adjacent rank (e.g. Rank 2) before Rank 1 is locked for refresh. Each rank reserves or over-provisions a very small area, denoted as a cache region, to store the cached data. The cache regions from all ranks are organized in a rotated fashion. In other words, the cached data for the last rank is stored in the first rank. When a read request arrives at a rank undergoing refresh, the memory controller first checks the cache region in the next rank in the same channel, if the requested data is cached, the memory controller services the request from the cache without waiting for the refresh operation to complete, which reduces memory access latency and improves system performance. Our experimental results show that RPC outperforms existing Fine Granularity Refresh modes. In a single-core and four-rank system, it improves system performance by 8.7% and 10.8% on average for the PARSEC 2.1 and SPLASH-2 benchmark suites, respectively. In a four-core and four-rank system, the improvement of system performance for these two benchmark suites is 8.6% and 12.2%, respectively.

In today's large data centers, hundreds to thousands of nodes are deployed as storage clusters to provide cloud and big data storage service, where failures are not rare. Therefore, efficient data redundancy technologies are needed to ensure data availability and reliability. Compared to traditional technology based on replication, erasure codes which tolerate multiple failures provide availability and reliability at a much lower cost. However, those erasure-coded, particularly XOR-coded storage clusters, suffer from performance problem caused by degraded reads under concurrent node failures. With the traditional centralized decoding method, a large amount of extra data has to be transmitted over the network to service degraded reads. In particular, the degraded reads in XOR-coded stripes with concurrent failures result in notably high network traffic. To address this problem, we propose a novel decoding approach called Local Decoding First or LDF for short. Via exploiting decoding computational locality of XOR-coded storage clusters, LDF significantly reduces the required network traffic and hence reduces the access latency of degraded reads, thus improving I/O throughput. A prototype of LDF with two typical XOR codes has been implemented in the popular distributed file system HDFS on a storage cluster composed of 40 nodes. The experimental results show that LDF dramatically reduces the network traffic under concurrent node failures and thus improves both the I/O throughput and access latency.

When airborne lidar is used to produce digital elevation models, the random error of airborne lidar systems is often the limiting factor. To improve the overall 3-D expected accuracy of airborne lidar systems, we develop random error models of airborne lidar systems. First, we present a footprint geolocation equation for the airborne lidar that describes an ideal system, followed by a modified footprint geolocation equation that contains systematic and random errors. To better constrain these uncertainties, we describe the mathematical characteristics of the random error in detail by modeling it as a stochastic process. The probabilistic random error models are developed by analyzing the differences between the errorless equation and the equation with errors. This paper also addresses the issue of recovering the errors and presents an error recovery model. Finally, based on a linear scanner and a new coordinate system, we simulate the geometric processes of point positioning of airborne lidar systems and study the impacts of the random measurement errors on the 3-D coordinate accuracy of airborne lidar systems.

This paper is devoted to the study of a directional lifting transform for wavelet frames. A nonsubsampled lifting structure is developed to maintain the translation invariance as it is an important property in image denoising. Then, the directionality of the lifting-based tight frame is explicitly discussed, followed by a specific translation invariant directional framelet transform (TIDFT). The TIDFT has two framelets ψ1, ψ2 with vanishing moments of order two and one respectively, which are able to detect singularities in a given direction set. It provides an efficient and sparse representation for images containing rich textures along with properties of fast implementation and perfect reconstruction. In addition, an adaptive block-wise orientation estimation method based on Gabor filters is presented instead of the conventional minimization of residuals. Furthermore, the TIDFT is utilized to exploit the capability of image denoising, incorporating the MAP estimator for multivariate exponential distribution. Consequently, the TIDFT is able to eliminate the noise effectively while preserving the textures simultaneously. Experimental results show that the TIDFT outperforms some other frame-based denoising methods, such as contourlet and shearlet, and is competitive to the state-of-the-art denoising approaches.

Mismatch behavior under packaging-induced die stress is presented. The mobility shift caused by package stress is a dominant source of analog circuit mismatch. Shallow trench isolation (STI) and well proximity effect (WPE) are also significant contributors to the mismatch in deep submicron CMOS technology. The experimental results performed with current steering 12-bit 90-nm CMOS I/Q digital-to-analog converter (I/Q DAC) having 150-mum die thickness well agree to the theory developed in this paper. The theoretical and experimental results also provide design guidance for minimizing the mismatch of analog circuits to packaging-induced die stress.

Electrical stress-relieved analog circuit design techniques using only thin-oxide devices are presented. Level shifters as well as optional diode insertion are carefully used to meet the electrical stress limit rules. The proposed idea was demonstrated with 12-bit I/Q digital-to-analog converter (DAC) in 65-nm CMOS technology and a high-operating temperature life (HTOL) test was performed to review the reliability of the design.