Hardware Trojans are malicious alterations or injections of unwanted circuitry to integrated circuits (ICs) by untrustworthy factories. They render great threat to the security of modern ICs by various unwanted activities such as bypassing or disabling the security fence of a system, leaking confidential information, deranging, or destroying the entire chip. Traditional testing strategies are becoming ineffective since these techniques suffer from decreased sensitivity toward small Trojans because of oversized chip and large amount of process variation present in nanometer technologies. The production volume along with decreased controllability and observability to complex ICs internals make it difficult to efficiently perform Trojan detection using typical structural tests like path latency and leakage power. In this paper, we propose a completely new post-silicon multimodal approach using runtime thermal and power maps for Trojan detection and localization. Utilizing the novel framework, we propose two different Trojan detection methods involving 2-D principal component analysis. First, supervised thresholding in case training data set is available and second, unsupervised clustering which require no prior characterization data of the chip. We introduce 11 regularization in the thermal to power inversion procedure which improves Trojan detection accuracy. To characterize ICs accurately, we perform our experiments in presence of realistic CMOS process variation. Our experimental evaluations reveal that our proposed methodology can detect very small Trojans with 3-4 orders of magnitude smaller power consumptions than the total power usage of the chip, while it scales very well because of the spatial view to ICs internals by the thermal mapping.

Vulnerability of modern integrated circuits (ICs) to hardware Trojans has been increasing considerably due to the globalization of semiconductor design and fabrication processes. The large number of parts and decreased controllability and observability to complex ICs internals make it difficult to efficiently perform Trojan detection using typical structural tests like path latency and leakage power. In this paper, we present new accurate methods for Trojan detection that are based upon post-silicon multimodal thermal and power characterization techniques. Our approach first estimates the detailed post-silicon spatial power consumption using thermal maps of the IC, then applies 2DPCA to extract features of the spatial power consumption, and finally uses statistical tests against the features of authentic ICs to detect the Trojan. To characterize real-world ICs accurately, we perform our experiments in presence of 20% – 40% CMOS process variation. Our results reveal that our new methodology can detect Trojans with 3–4 orders of magnitude smaller power consumptions than the total power usage of the chip, while it scales very well because of the spatial view to the ICs internals by the thermal mapping.

We propose new techniques for post-silicon power mapping and modeling of multi-core processors using infrared imaging and performance counter measurements. An accurate finite-element modeling framework is used to capture the relationship between temperature and power, while compensating for the artifacts introduced from substituting traditional heat removal mechanisms with oil-based infrared-transparent cooling mechanisms. We use thermal conditioning techniques to build leakage power models for the die. Utilizing the power maps identified from infrared mapping, we develop empirical power models for different processor blocks based on the measurements from the performance monitoring counters (PMCs), and utilize the PMC-based models to analyze the transient power consumption. In our experiments, we capture thermal images from a quad-core processor under different workload conditions, and then we reconstruct the dynamic and leakage power maps for different blocks. Our results show good accuracy in mapping and modeling, revealing good insights into the trends of power consumption in multi-core processors.

Post-silicon power validation is an important step in integrated circuit design and fabrication flow. It involves runtime power characterization of a fabricated chip under realistic loadings. The most versatile procedure for post-silicon power characterization involves capturing the thermal emissions from the back of the die and inverting the captured images to get power estimates. This process faces two major challenges: the spatial heat diffusion effect, which blurs the underlying power map, and measurement noise in the thermal imaging system. In this paper, we propose to use ac-based thermography, where ac excitation signals are applied to the chip instead of dc excitation signals, to improve post-silicon power mapping. We show that using ac excitation reduces the impact of flicker noise and spatial heat diffusion, which translates to significant improvements in power mapping accuracy. We perform a number of experiments using a test chip that can be programmed to control spatial and temporal power consumption. We use the test chip to analyze the noise in our thermal imaging system, and to quantify the improvements in power mapping attained from the proposed ac-based methodology. We elucidate the impact of the ac excitation frequency on both the signal-to-noise ratio and power mapping accuracy. We also demonstrate the basic applicability of our technique on a dual-core processor.

The objective of power modeling is to estimate the power consumption of integrated circuits under different workloads and variabilities. Post-silicon power modeling is an essential step for design validation and for building trustable pre-silicon power models and analyses. One popular approach for devising post-silicon power estimates is to translate the thermal emissions from the backside of the die into power estimates. Such approach faces a major physical challenge arising from spatial heat diffusion which blurs the resultant thermal images. The objective of this paper is to improve post-silicon power mapping by utilizing lock-in thermography techniques where AC signals, rather than DC signals, are used to excite the circuit blocks. We prove and demonstrate that using AC excitation sources reduces the extent of spatial heat diffusion. We devise a lock-in based thermal to power inversion methodology that maps spatial power consumption on a real chip. Using a custom test chip, we are to able to scientifically quantify and validate the improvements in power mapping attained from the proposed techniques. We show that our technique reduces the power mapping errors by more than half.

In this paper we propose new techniques for thermal and power characterization of Field Programmable Gate Arrays (FPGAs) using infrared imaging techniques. For thermal characterization, we capture the thermal emissions from the backside of an FPGA chip during operation. We analyze the captured emissions and quantify the extent of thermal gradients and hot spots in FPGAs. Given that FPGAs are fabricated with no knowledge of the potential field designs, we propose soft sensing techniques that can combine the measurements of hard sensors to accurately estimate the temperatures where no sensors are embedded. For power characterization, we propose algorithmic techniques to invert the thermal emissions from FPGAs into spatial power estimates. We demonstrate how this technique can be used to produce spatial power maps of soft processors during operation.

Hot spots are a major concern in high-end processors as they constrain performance and limit the lifetime of semiconductor chips. Using embedded thermal sensors, dynamic thermal management systems track the hot spots during runtime and adjust the performance and the cooling system of the processor when necessary. In many-core processors, the locations of hot spots vary spatially and temporally depending on the configuration of active cores and the workloads running on the cores. Our work includes both theoretical advances in sensor allocation techniques and experimental advances for thermal imaging of real processors. We propose a hard sensor allocation algorithm to determine the sensor locations where hot spots can be tracked accurately given a budget number of sensors. We also propose soft sensor computation techniques to alleviate design constraints on sensor locations and to further improve the resolution of hot spot tracking. The proposed soft sensing technique combines the measurements of the hard sensors in an optimal way to estimate the temperature at any desired location. We use infrared imaging methods to characterize the thermal behavior of a real dual-core processor during operation. We execute large number of workload configurations on the processor and track the locations and temperatures of hot spots during runtime. The thermal characterization data are then used as the input to our sensor allocation techniques. We demonstrate that our sensor allocation techniques improve significantly upon the previous results in the literature and provide accurate tracking of hot spots.

The increased power densities of multi-core processors and the variations within and across workloads lead to runtime thermal hot spots locations of which change across time and space. Thermal hot spots increase leakage, deteriorate timing, and reduce the mean time to failure. To manage runtime thermal variations, circuit designers embed within-die thermal sensors that acquire temperatures at few selected locations. The acquired temperatures are then used to guide runtime thermal management techniques. The capabilities of these techniques are essentially bounded by the spatial thermal resolution of the sensor measurements. In this paper we characterize temperature signals of real processors and demonstrate that on-chip thermal gradients lead to sparse signals in the frequency domain. We exploit this observation to (1) devise thermal sensor allocation techniques, and (2) devise signal reconstruction techniques that fully characterize the thermal status of the processor using the limited number of measurements from the thermal sensors. To verify the accuracy of our methods, we compare our temperature characterization results against thermal measurements acquired from a state-of-the-art infrared camera that captures the mid-band infrared emissions from the back of the die of a 45 nm dual-core processor. Our results show that our techniques are capable of accurately characterizing the temperatures of real processors.

Design-time power analysis is one of the most critical tasks conducted by chip architects and circuit designers. While computer-aided power analysis tools can provide power consumption estimates for various circuit blocks, these estimates can substantially deviate from the actual power consumption of working silicon chips. We propose a novel methodology that provides accurate, detailed post-silicon spatial power estimates using the thermal infrared emissions from the backside of silicon die. We theoretically and empirically demonstrate the inherent difficulties in thermal to power inversion. These difficulties arise from measurement errors and from the inherent spatial low-pass filtering associated with heat diffusion. To address these difficulties we propose new techniques from regularization theory to invert temperature to power. Furthermore, we propose new techniques to compute the emissivities and conductances required for any infrared to power inversion method. To verify our results, a programmable circuit of micro heaters is implemented to create any desired power pattern. The thermal emissions of different known injected power patterns are captured using a state-of-the-art infrared camera, and then our characterization techniques are applied to invert the thermal emissions to power. The estimated power patterns are validated against the injected power patterns to demonstrate the accuracy of our methodology.