VLDB 2026 Research / reviewers in the wild / expert
Ben Gras
dblp:68/86
· DBLP profile ↗
12ranked-venue papers
3as first author
1since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 11 · 3 first-author · 1 since 2021Systems, architecture and hardware · 4Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
7 papers |
Hardware security and side channels · 78% Systems and software security · 22% | |
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 71% Processor architecture and microarchitecture · 16% Memory systems · 12% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 14 heaviest of 16, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › microarchitectural attacks
cache attacks |
0.7 | 2 | 2020 | : Practical Cache Attacks from the Network · SP 2020 ASLR on the Line: Practical Cache Attacks on the MMU · NDSS 2017 |
Hardware security and side channels
microarchitectural side channel |
0.7 | 2 | 2020 | ABSynthe: Automatic Blackbox Side-channel Synthesis on Commodity Microarchitectures · NDSS 2020 ASLR on the Line: Practical Cache Attacks on the MMU · NDSS 2017 |
Electronic design automation
hardware verification and test |
0.6 | 1 | 2022 | CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL · USENIX Security Symposium 2022 |
Hardware security and side channels
microarchitectural attacks |
0.4 | 1 | 2020 | : Practical Cache Attacks from the Network · SP 2020 |
Hardware security and side channels › side-channel attack
cache side-channel attacks |
0.3 | 1 | 2018 | Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks · USENIX Security Symposium 2018 |
Hardware security and side channels
fault attacks |
0.2 | 1 | 2016 | Flip Feng Shui: Hammering a Needle in the Software Stack · USENIX Security Symposium 2016 |
Hardware security and side channels › fault attacks › fault injection attack
rowhammer attack |
0.2 | 1 | 2016 | Flip Feng Shui: Hammering a Needle in the Software Stack · USENIX Security Symposium 2016 |
Systems and software security › memory safety
control-flow integrity |
0.2 | 1 | 2015 | Practical Context-Sensitive CFI · CCS 2015 |
Systems and software security
information flow tracking |
0.2 | 1 | 2022 | CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL · USENIX Security Symposium 2022 |
Memory systems › memory management › virtual memory › address translation
TLB |
0.1 | 1 | 2018 | Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks · USENIX Security Symposium 2018 |
Operating systems › system security › operating system security › protection mechanism
address space layout randomization |
0.1 | 1 | 2017 | ASLR on the Line: Practical Cache Attacks on the MMU · NDSS 2017 |
Operating systems › resource management
memory management |
0.1 | 1 | 2017 | ASLR on the Line: Practical Cache Attacks on the MMU · NDSS 2017 |
Systems and software security
exploitation |
0.1 | 1 | 2015 | Practical Context-Sensitive CFI · CCS 2015 |
Systems and software security
return-oriented programming defense |
0.1 | 1 | 2015 | Practical Context-Sensitive CFI · CCS 2015 |
Methods — techniques the papers use, named apart from their topics
information flow tracking · 1.1fuzzing · 0.9black-box analysis · 0.9cache timing analysis · 0.6reverse engineering · 0.4prime+probe · 0.4rowhammer · 0.2path tracking · 0.2binary instrumentation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | CellIFT: Leveraging Cells for Scalable and Precise Dynamic Information Flow Tracking in RTL
Flavien Solt, Ben Gras, Kaveh Razavi |
USENIX Security Symposium | 2 |
| 2020 | ABSynthe: Automatic Blackbox Side-channel Synthesis on Commodity Microarchitectures
Ben Gras, Cristiano Giuffrida, Michael Kurth, Herbert Bos, Kaveh Razavi |
NDSS | 1 |
| 2020 | : Practical Cache Attacks from the NetworkabstractIncreased peripheral performance is causing strain on the memory subsystem of modern processors. For example, available DRAM throughput can no longer sustain the traffic of a modern network card. Scrambling to deliver the promised performance, instead of transferring peripheral data to and from DRAM, modern Intel processors perform I/O operations directly on the Last Level Cache (LLC). While Direct Cache Access (DCA) instead of Direct Memory Access (DMA) is a sensible performance optimization, it is unfortunately implemented without care for security, as the LLC is now shared between the CPU and all the attached devices, including the network card.In this paper, we reverse engineer the behavior of DCA, widely referred to as Data-Direct I/O (DDIO), on recent Intel processors and present its first security analysis. Based on our analysis, we present NetCAT, the first Network-based PRIME+PROBE Cache Attack on the processor's LLC of a remote machine. We show that NetCAT not only enables attacks in cooperative settings where an attacker can build a covert channel between a network client and a sandboxed server process (without network), but more worryingly, in general adversarial settings. In such settings, NetCAT can enable disclosure of network timing-based sensitive information. As an example, we show a keystroke timing attack on a victim SSH connection belonging to another client on the target server. Our results should caution processor vendors against unsupervised sharing of (additional) microarchitectural components with peripherals exposed to malicious input. Michael Kurth, Ben Gras, Dennis Andriesse, Cristiano Giuffrida, Herbert Bos, Kaveh Razavi |
SP | 2 |
| 2018 | Translation Leak-aside Buffer: Defeating Cache Side-channel Protections with TLB Attacks
Ben Gras, Kaveh Razavi, Herbert Bos, Cristiano Giuffrida |
USENIX Security Symposium | 1 |
| 2017 | ASLR on the Line: Practical Cache Attacks on the MMU
Ben Gras, Kaveh Razavi, Erik Bosman, Herbert Bos, Cristiano Giuffrida |
NDSS | 1 |
| 2016 | OSIRIS: Efficient and Consistent Recovery of Compartmentalized Operating SystemsabstractMuch research has gone into making operating systems more amenable to recovery and more resilient to crashes. Traditional solutions rely on partitioning the operating system (OS) to contain the effects of crashes within compartments and facilitate modular recovery. However, state dependencies among the compartments hinder recovery that is globally consistent. Such recovery typically requires expensive runtime dependency tracking which results in high performance overhead, highcomplexity and a large Reliable Computing Base (RCB). We propose a lightweight strategy that limits recovery to cases where we can statically and conservatively prove that compartment recovery leads to a globally consistent state - trading recoverable surface for a simpler and smaller RCB with lower performance overhead and maintenance cost. We present OSIRIS, a research OS design prototype that demonstrates efficient and consistent crash recovery. Our evaluation shows that OSIRIS effectively recovers from important classes of real-world software bugs with a modest RCB and low overheads. Koustubha Bhat, Dirk Vogt, Erik van der Kouwe, Ben Gras, Lionel Sambuc, Andrew S. Tanenbaum, Herbert Bos, Cristiano Giuffrida |
DSN | 4 |
| 2016 | Flip Feng Shui: Hammering a Needle in the Software Stack
Kaveh Razavi, Ben Gras, Erik Bosman, Bart Preneel, Cristiano Giuffrida, Herbert Bos |
USENIX Security Symposium | 2 |
| 2015 | Practical Context-Sensitive CFIabstractCurrent Control-Flow Integrity (CFI) implementations track control edges individually, insensitive to the context of preceding edges. Recent work demonstrates that this leaves sufficient leeway for powerful ROP attacks. Context-sensitive CFI, which can provide enhanced security, is widely considered impractical for real-world adoption. Our work shows that Context-sensitive CFI (CCFI) for both the backward and forward edge can be implemented efficiently on commodity hardware. We present PathArmor, a binary-level CCFI implementation which tracks paths to sensitive program states, and defines the set of valid control edges within the state context to yield higher precision than existing CFI implementations. Even with simple context-sensitive policies, PathArmor yields significantly stronger CFI invariants than context-insensitive CFI, with similar performance. Victor van der Veen, Dennis Andriesse, Enes Göktas, Ben Gras, Lionel Sambuc, Asia Slowinska, Herbert Bos, Cristiano Giuffrida |
CCS | 4 |
| 2009 | Fault isolation for device driversabstractThis work explores the principles and practice of isolating low-level device drivers in order to improve OS dependability. In particular, we explore the operations drivers can perform and how fault propagation in the event a bug is triggered can be prevented. We have prototyped our ideas in an open-source multiserver OS (MINIX 3) that isolates drivers by strictly enforcing least authority and iteratively refined our isolation techniques using a pragmatic approach based on extensive software-implemented fault-injection (SWIFI) testing. In the end, out of 3,400,000 common faults injected randomly into 4 different Ethernet drivers using both programmed I/O and DMA, no fault was able to break our protection mechanisms and crash the OS. In total, we experienced only one hang, but this appears to be caused by buggy hardware. Jorrit N. Herder, Herbert Bos, Ben Gras, Philip Homburg, Andrew S. Tanenbaum |
DSN | 3 |
| 2009 | Enhancing a dependable multiserver operating system with temporal protection via resource reservations
Antonio Mancina, Dario Faggioli, Giuseppe Lipari, Jorrit N. Herder, Ben Gras, Andrew S. Tanenbaum |
Real Time Syst. | 5 |
| 2008 | Countering IPC Threats in Multiserver Operating Systems (A Fundamental Requirement for Dependability)abstractMultiserver operating systems have great potential to improve dependability, but, paradoxically, are paired with inherently more complex interprocess communication (IPC). Several projects have attempted to run drivers and extensions in isolated protection domains, but a systematic way to deal with IPC threats posed by untrusted parties is not yet available in the literature. IPC is fundamental to the dependability of multiserver systems.In this paper, we present a classification of IPC threats in multiserver systems with unreliable and hostile senders and receivers, such as resource exhaustion, spoofing, and unauthorized access. We also introduce an extended asymmetric trust model, describing two new IPC vulnerabilities relating to caller blockage. Based on our classification of IPC threats we present the IPC defense mechanisms and architecture of MINIX 3. Jorrit N. Herder, Herbert Bos, Ben Gras, Philip Homburg, Andrew S. Tanenbaum |
PRDC | 3 |
| 2007 | Failure Resilience for Device DriversabstractStudies have shown that device drivers and extensions contain 3-7 times more bugs than other operating system code and thus are more likely to fail. Therefore, we present a failure-resilient operating system design that can recover from dead drivers and other critical components - primarily through monitoring and replacing malfunctioning components on the fly - transparent to applications and without user intervention. This paper focuses on the post-mortem recovery procedure. We explain the working of our defect detection mechanism, the policy-driven recovery procedure, and post-restart reintegration of the components. Furthermore, we discuss the concrete steps taken to recover from network, block device, and character device driver failures. Finally, we evaluate our design using performance measurements, software fault-injection experiments, and an analysis of the reengineering effort. Jorrit N. Herder, Herbert Bos, Ben Gras, Philip Homburg, Andrew S. Tanenbaum |
DSN | 3 |