This paper presents a framework which can avoid the lengthy system test by utilizing machine-learning techniques to classify parts into different DVFS bins based on the results collected at CP and FT test only. The core machine-learning techniques in use are Bayesian linear regression for model fitting and stepwise regression for feature selection. Another method, called the incremental F_max-model search, is also presented to reduce the test time of collecting the required data for each training sample. The experiments are conducted based on 249 test chips of an industrial SoC. The experimental results demonstrate that our proposed framework can achieve a high accuracy ratio of placing a part into correct DVFS bin without placing any slower part into a faster DVFS bin. The experimental results also demonstrate that the incremental F_max-model search can save 45.1% and 52.6% of applications of the system-level test compared to the conventional median linear search and binary search, respectively.

As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electro-migration (EM) constraints. This paper presents a design flow to generate a PDN that can result in near-minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28 nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.

In previous literatures, many approaches use ring oscillators or other process monitors to correlate the chip's maximum operating frequency (Fmax). But none of them focus on the placement of these on-chip process monitors (OPMs) on a chip. The placement will greatly influence the accuracy of a prediction model. In this paper, we first propose a simulation framework to sample a chip's Fmax and it's OPM result. These samples are used to develop our methodology of OPM placement and to verify the effectiveness of an OPM placement. Then, a model-fitting framework is presented to correlate the OPMs' result to chip's Fmax. Finally, we propose a methodology to idenify optimal placement of OPM for predicting Fmax. The experiments demonstrate the effectiveness of our methodology in both simulation and silicon data.

As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and EM constraints. This paper presents a design flow to generate a PDN that can result in minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.

This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip's maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.

Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switches. In this paper, we study the usage of coarse-grain MTCMOS power switches for both logic circuits and SRAMs, and then propose corresponding methods of testing stuck-open power switches for each of them. For logic circuits, a specialized ATPG framework is proposed to generate a longest possible robust test while creating as many effective transitions in the switch-centered region as possible. For SRAMs, a novel test algorithm is proposed to exercise the worst-case power consumption and performance when stuck-open power switches exist. The experimental results based on an industrial MTCMOS technology demonstrate the advantage of our proposed testing methods on detecting stuck-open power switches for both logic circuits and SRAMs, when compared to conventional testing methods.

This paper presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this paper to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. The experimental results based on large ISCAS and ITC benchmark circuits demonstrate the accuracy of the proposed mathematical models and the advantages of using STSD scheme.