As semiconductor technology advances, small delay defects (SDDs) have become a major concern in System-on-Chip (SoC) testing due to shrinking timing margins. Moreover, diagnosing SDDs is getting even more challenging due to their subtle impact on circuit timing and the existence of process variations. This paper presents an SDD diagnosis method integrating timing-aware fault simulation with injected delay selection and a mismatch-weighted (MW) score method to enhance diagnostic accuracy. Rather than relying on fixed delay values, the proposed method determines injected delays based on the slack of transition paths, generating multiple delay sizes to improve fault simulation resolution. The MW score calculation adjusts contributions of failures, enhancing defect ranking and mitigating process variation effects. Experimental results demonstrate that the proposed method significantly improves SDD localization and reduces the number of fault candidates, outperforming conventional approaches in both accuracy and efficiency.

Integrated circuits (ICs) have become extremely complex nowadays. Therefore, multiple test standards could be employed to handle different testing scenarios. Unfortunately, this also leads to serious security problems since attackers can exploit the excellent controllability and observability of test standards to steal confidential information or disrupt the circuit’s functionality. This article proposes a universal sequential authentication scheme that is compatible with test standards employing the test access port controller (TAPC) defined in IEEE Std 1149.1. The main objective is to protect multiple TAPC-based test standards with a universal security module. In this scheme, only authorized test data can be updated to the target register to control the corresponding test standard, and only the response to authorized test data can be output. The key idea is to generate different authentication keys for different test data, and even with the same set of test data, if their input sequences are different, their authentication keys will also be different. Furthermore, we develop an irreversible obfuscation mechanism to generate fake output data to confuse attackers. Due to its irreversibility, the original correct output data cannot be deduced from the fake output data. Experimental results on a typical processor, i.e., SCR1, show that the proposed scheme causes no time overhead, and the area overhead is only 1.74%.

The IEEE 1687 test standard provides an effective way to access on-chip instruments by an Internal Joint Test Action Group (IJTAG) network. However, it also leads to severe security problems because anyone can easily access these instruments through IJTAG networks. This paper proposes an authentication-based secure IJTAG network to defend the potential threats. The main idea is to ensure that instruments can be accessed only when users enter legal patterns. The secure structure generates different keys for different patterns to overcome the single key's weakness. If attackers shift in illegal patterns, they cannot manipulate target instruments. An obfuscator to generate fake output data is also developed to confuse attackers. The proposed method can defend against memory attacks, brute-force attacks, and reverse engineering attacks. Experimental results show that the proposed method requires only a small area overhead.

This paper presents a novel diagnostic procedure for transition delay faults (TDFs) using a two-dimensional scan - based test chip architecture. The test chip architecture consists of C-testable blocks (CTBs) and scan registers. Each CTB has the distinguished VH-bijection property that ensures any change on either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. The diagnostic procedure consists of two tests, one for the scan chain test and the other for the whole chip test. Experimental result s show that the required time for a test chip containing 68*68 8-input/8-output CTBs is less than 0.2 seconds when executing the test procedure at 100MHz. The proposed diagnostic procedure can achieve 100% diagnosability for all transition faults in th e test chip.

A scan-based test chip architecture composed of a two-dimensional array of C-testable blocks (CTBs) and scan registers is proposed, where each CTB contains several XOR modules and has the distinguished VH-bijection property, i.e., each CTB is bijective, and any change in either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. We present a novel method to systematically embed each combinational standard cell in a cell library to an XOR module such that almost all input pattern faults (including all stuck-at faults) in the standard cells can be detected even if multiple faults exist. Great diagnosability is achieved due to the VH-bijection property of CTBs, the full fault coverage property for faults in the standard cells inside CTBs, and the scan-based test chip architecture.

Test cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.

This article presents a diagnosis pattern generation procedure that not only can generate very compact diagnosis patterns to distinguish nonequivalent transition faults, but also can identify equivalent (EQ) transition faults efficiently. This procedure mainly consists of two major methods: 1) a user-defined-fault-based inactivation method that transforms the problem of distinguishing all transition faults into that of detecting a set of user-defined faults and then deals with all these faults at a time by using an ATPG tool and 2) a unified fault-pair transformation method that transforms the problem of distinguishing two transition faults into the problem of detecting a transition fault and then process all these faults also in one ATPG run. By these two methods, very compact diagnosis pattern sets can be obtained. For the very few fault pairs that cannot be handled by these two methods due to ATPG backtracking limit, we employ a SAT-based method to deal with these pairs and show that they are all EQ-fault pairs. Experimental results on ISCAS’89 and IWLS’05 benchmark circuits show that this is the first work that can distinguish all distinguishable transition faults and identify all EQ transition faults for ISCAS’89 and IWLS’05 benchmark circuits.

Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing the test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this article, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.

As the Internet of Things (IoT) systems become more and more popular, many devices around life are now connected to the internet. While allowing large amounts of information to be transmitted and exchanged, sensitive information in IoTs also becomes vulnerable to leakage. Therefore the security of each device and network in IoT systems has become a critical issue. Many IoT devices are simple devices used for daily supplies; they cannot cost too much and must be lightweight. These devices are often controlled by simple Operating Systems (OS), some even in bare-metal environments without OS. In this paper we propose a lightweight memory security mechanism implemented mainly by hardware. This mechanism puts critical data in secure regions, and the processor can access the secure regions only after passing a hardware-based authentication process. Our method allows the processor to maintain high security without relying on the OS; hence even if the IoT device only has a bare-metal environment, it still can protect important data at a low cost. Experimental results show that a very high level of security can be achieved with only a very small extra delay and area overhead required.

This article proposes a scan-based test chip architecture targeting the diagnosis of multiple faults consisting of input pattern faults, stuck-at faults, and bridging faults (BFs). The architecture consists of a 2-D array of logic blocks and two sets of scan chains isolating the logic blocks. The scan chains are used to fully control and observe the logic blocks so as to enhance the testability and diagnosability of test chips. An efficient diagnostic procedure composed of two tests is developed to carry out the defect diagnosis process. Evaluation results show that the proposed procedure can always achieve 100% accuracy for single faults. When double faults containing 0, 1, and 2 BFs are considered, the proposed procedure can achieve 100% accuracy for 99.38%, 98.398%, and 97.416% of the faults and achieve perfect resolution for 98.81%, 98.006%, and 97.202% of the faults, respectively. Moreover, no matter how many faults exist, as long as no fault affects the scan registers, the proposed procedure can report all faulty logic blocks.

A novel method to efficiently and accurately prognosticate the pattern count at different input compression ratios with the Embedded Deterministic Test (EDT) compression technology is proposed. With this method the total ATPG run time can be significantly reduced compared to the currently used trial-and-error method.

Over the past two decades, test data compression has become a de facto technology used in large industrial designs to reduce the overall test cost. During DFT planning, it is very important to understand the impact of using different numbers of input/output channels on test coverage, test cycles, and test data volume. In this paper, an efficient method to estimate the test data volume with different input channel counts using the Embedded Deterministic Test (EDT) compression technology is proposed. The results can then be used to quickly determine the scan configuration that results in the least or near least test data volume. With this method, the total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error method.

As the complexity of industrial integrated circuits continue to increase rapidly, test data compression has now become a de facto technology for large designs to reduce the overall test cost. During the design for test (DFT) planning, it is critical to understand the impact of using different numbers of input/output test channels on test coverage, test cycles, and test data volume. In this paper, two approaches to predict the test pattern counts and test data volumes with different input channel counts are presented, one with the compression tool able to generate channel-scaling patterns and the other without this capability. The results can be used to determine the scan test configuration that results in the smallest or near smallest test data volume. Experiments on industrial circuits show that the average error rates of pattern count prediction for most circuits are less than 10% for both approaches. The error rates of the predicted smallest data volumes are all less than 3.5%. The total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error approach.

A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.

With the increase in design complexity and test data volume, compressed tests together with on-chip test decompression hardware such as Embedded Deterministic Test (EDTTM) are widely used in industry in order to reduce test cost. One of the challenges of such Design-for-Test (DFT) technology is to determine a set of optimal parameters such as the number of scan chains, scan channels, power budget, etc. such that it can reach the highest test coverage with a minimum amount of test data volume whilst satisfying various other constraints. To achieve the optimal compression configuration quickly, in this work deep learning technology based on Tensorflow is explored to estimate the test coverage and the data volume for a design when employing EDT under a given set of circuit parameters. Based on the estimated data, the optimal test architecture is also predicted, yielding a more efficient approach compared to the currently used trial-and-error methods. To demonstrate the advantages of our deep learning approach over the currently used utility, we present experimental data for eight industrial designs.

Real-time clock circuits are widely used in modern electronic systems to provide time information to the systems at the beginning of the system power-on. In this paper, we present two types of Hardware Trojan designs that employ the time information as the trigger conditions. One is a real-time based Trojan, which will attack a system at some specific realworld time. The other is a relative-time based Trojan, which will be triggered when a specific time period passes after the system is powered on. In either case when a Trojan is triggered its payload may corrupt the system or leakage internal information to the outside world. Experimental results show that the extra power consumption, area overhead and delay time are all quite small and thus the detection of the Trojans is difficult by using traditional side-channel detection methods.

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This paper presents a novel test architecture that combines the advantages of high-quality deterministic scan-based test and low-cost built-in self-test. The main idea is to record (store) all required compressed test data in a novel scan chain structure, and extract and decompress them during testing. This requires a very high compression ratio to obtain a low test data volume, that is, smaller than the number of scan cells in the circuit under test. To achieve such a high compression ratio, we propose a novel compression method that combines broadcast scan as well as a tailored single-input compression architecture. We also utilize the concept of scan chain partitioning and clock gating to reduce the test time and test power. An on-chip test controller is employed to automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external automatic test equipment. Experimental results show that our method is well suitable for multicore designs. For example, experiments on the 8-core open-source OpenSPARC T2 processor with 5.7M gates show that all required test data for 100% testable stuck-at fault coverage can be stored in just 59.4% of the scan cells of the processor. Experimental results for transition faults are also presented, which show that more identical cores are needed in order to store all test data for transition faults. We also discuss how to extend this paper to address fault diagnosis and engineering change order problems.

This paper proposes an efficient diagnosis-aware automatic test pattern generation (ATPG) procedure that can quickly identify equivalent-fault pairs and generate diagnosis patterns (DPs) for nonequivalent-fault pairs, where a (non)equivalent fault pair contains two stuck-at faults that are (non)equivalent. The proposed procedure contains three main methods, which together can efficiently generate highly compacted DPs by using a conventional ATPG tool. First, an all-pairs at-a-time diagnosis pattern generation (AFPAT-DPG) method, which adopts user-defined fault models (UDFMs), is employed to quickly generate DPs for most fault pairs that cannot be distinguished by a given set of, typically fault detection, test patterns (TP). For those fault pairs that cannot be distinguished by AFPAT-DPG, a multipair diagnostic ATPG method (MP-DATPG) is used. MP-DATPG is a complete method in the sense that it can generate diagnosis tests for every distinguishable pair of faults or prove that the pair of faults is indistinguishable. However, due to back-track limits in test generation procedures, diagnosis test generation for some fault pairs may be aborted after the application of the two methods. For such fault pairs, a subcircuit analysis (SCA) method is applied to identify equivalent fault pairs among the aborted fault pairs by trimming the circuit under consideration into one that is much easier to process within the back-track limits of the test generation procedures. Experimental results show that the proposed procedure is the first work that distinguishes 100% of all fault pairs in all ISCAS'89 and IWLS'05 benchmark circuits and over 99.99% for all ITC'99 benchmark circuits using a conventional ATPG tool that generates tests to detect faults.

Scan design is a universal design for test (DFT) technology to increase the observability and controllability of the circuits under test by using scan chains. However, it also leads to a potential security problem that attackers can use scan design as a backdoor to extract confidential information. Researchers have tried to address this problem by using secure scan structures that usually have some keys to confirm the identities of users. However, the traditional methods to store intermediate data or keys in memory are also under high risk of being attacked. In this paper, we propose a dynamic-key secure DFT structure that can defend scan-based and memory attacks without decreasing the system performance and the testability. The main idea is to build a scan design key generator that can generate the keys dynamically instead of storing and using keys in the circuit statically. Only specific patterns derived from the original test patterns are valid to construct the keys and hence the attackers cannot shift in any other patterns to extract correct internal response from the scan chains or retrieve the keys from memory. Analysis results show that the proposed method can achieve a very high security level and the security level will not decrease no matter how many guess rounds the attackers have tried due to the dynamic nature of our method.

This paper presents a novel test pattern generation flow to detect stuck-at and transition faults simultaneously. Both fault models are transformed into a unified fault model for a proposed 2-time-frame circuit model. This makes it possible to generate patterns for both types of faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set can thus be obtained which requires less test data volume and shorter test application time without degrading the fault coverage for either type of faults. Experimental results show that, compared to the conventional methods, the proposed method can reduce the total test pattern counts by up to 12.27% and 15.54% and test application times up to 12.06% and 15.58% for ISCAS'89 and ITC'99 circuits, respectively.

A novel test pattern generation flow for both DC and AC faults is presented. All faults to be processed are transformed into stuck-at faults with some constraints in a proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model which is supported by most commercial ATPG tools. This makes it possible to generate all required patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool. A highly compact pattern set thus can be obtained which requires smaller test data volume and shorter test application time. The fault models considered in this paper include stuck-at faults, bridging faults and transition faults. Experiments on ISCAS`89, IWLS`05 and ITC`99 benchmark circuits show that, compared to the most efficient conventional methods, on average our method can reduce test pattern counts by 14.55%, 11.26% and 13.69% and reduce test application time by 25.93%, 24.47% and 31.67%, respectively, without degrading fault coverage.

Multicast communication can greatly enhance the performance of Networks-on-Chip. Currently most multicast routing algorithms are either tree-based or path-based. The former has low latency but needs to solve multicast deadlocks through additional hardware resources. The latter can avoid deadlocks easily but may require long routing paths. In this paper we propose a hybrid multicast routing approach that combines the advantages of both path- and tree-based methods. The proposed approach ensures deadlock-free multicast routing without requiring additional virtual channels or large buffers to hold large packets. High routing performance is achieved using an adaptive routing strategy considering the traffic load in nearby routers. Two techniques, namely node balancing and path balancing, are further developed to enhance this hybrid routing algorithm. Extensive experiments with different buffer sizes, packet sizes and numbers of destinations per packet under random and Rent's rule traffic at various traffic injection rates have been conducted. The results show that the average latency of our approach is lower than previous multicast routing algorithms in most cases, and the saturation points of our approach are always at much higher injection rates.

Test time and test data volume required to test modern integrated circuits grow rapidly with circuit complexity. Test compression is now widely used in industry to reduce test cost. In this paper, a simple yet highly efficient test data compression technique with small area overhead is presented. Efficient algorithms are developed to determine configurations of the test decompressor and corresponding test patterns in multiple test sessions. These algorithms result in higher test compression ratio and lower test application time with less CPU runtime compared to the latest previous work. Experimental results on IWLS'05 benchmark circuits show that on average we can increase the compression factor by 17.26%, decrease the test application time by 12.28% and cut down the CPU time by 42.92%, with only slight increase of area overhead. More importantly, up to 1500x test compression factor is achieved for a design containing about 2M gates, with only 0.1% area overhead.

The run-pause-resume (RPR) debug methodology allows one to pause the normal circuit operations, observe the internal states of flip-flops and then resume the normal operations for further debug process. Data invalidation is a major problem that needs to be addressed when debugging a multiple-clock design with this methodology. This problem occurs when flip-flops in a receiving clock domain capture incorrect data during debugging, and thus cannot be resumed correctly. In this paper we propose a novel RPR technique that can avoid data invalidation with the cycle-level granularity of debug resolution. A software program is employed to calculate the exact time to transmit pause control signals according to the user-defined breakpoint and a hardware controller is developed to convert the pause signal to appropriate gating signals for the circuit under debug (CUD) and the data path of the clock domain crossing interface. By doing this, we can avoid data invalidation as well as allow users to pause and resume the CUD at arbitrary clock cycle. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved.

This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the total test generation time can be reduced and very compact (small) test sets can be obtained. In addition, we present a path-based test generation method that aims to choose the smallest set of paths to cover all faults and each path tends to have the largest delay in the CMOS cell containing it. Using this method one can generate tests with better quality without increasing the number of test patterns. Experimental results show that on average 1.28X (1.35X) of the number of test patterns for transition delay faults are sufficient to detect all open and delay faults in CMOS cells as well as the transition faults in gate interconnects of ISCAS'89 (IWLS'05) circuits.

A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpoint-setup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.

In this paper, a novel test compression technique is proposed that can achieve very high test compression ratio with low area overhead and only one single test input. An inverter and a series of D flip-flops together with a configurable switch logic are inserted between the single input and the scan chains so as to convert the input patterns to the test data required by each scan chain. All scan chains are divided into some scan groups such that scan chains in the same group can share the same test data and the switch logic only needs to connect each group to an appropriate data provider. Hence the total area overhead is quite small. A novel algorithm is developed to determine the required test configurations and corresponding test patterns for 100% testable fault coverage. Experimental results show that on average this method can achieve data reduction factors of 23×, 124×, and 394× with 3.77%, 0.95%, and 0.03% area overhead for ISCAS'89, IWLS'05 OpenCores, and IWLS'05 Gaisler Research benchmark circuits, respectively. These results indicate that the reduction factor increases with the sizes of circuits; it even reaches 464× for a circuit containing 2.07 million gates with very small area overhead. As all test and control data can be provided by a single input, great reduction on test channel requirement is also achieved.

Through silicon vias (TSVs) play an important role in 3-D chip integration. Effective and efficient testing for correct operation of TSVs is essential for 3-D integrated circuit design. This paper addresses the post-bond test and diagnosis of crosstalk faults among TSVs considering different impact ranges, and proposes a TSV grouping method for rectangular and hexagonal TSV placements such that as many TSVs as possible are tested simultaneously. Based on the results of the TSV grouping, we implement a high-efficiency, low-area-overhead TSV test architecture that reuses the existing boundary scan or IEEE 1500 wrapper cells typically present for prebond testing. Experimental results show the short test and diagnosis time as well as the low area overhead of the proposed test architecture.

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

A dynamic bridging fault (DBF) induces a transition delay on a circuit node and hence has fault effects similar to a transition delay fault (TDF). However the causes of these two types of faults are quite different: a DBF is due to the bridging effects between two circuit nodes, while a TDF is due to a node itself or the logic connected to the node. In this paper we present an efficient test and diagnosis pattern generation procedure to detect DBFs and TDFs as well as to distinguish them such that the exact sources of defects can be identified during the yield ramping process. We first analyze the dominance relation between a DBF and its corresponding TDF. A new circuit model called the inverse DBF (IDBF) model is then employed which can transform the problem of distinguishing a pair of a DBF and a TDF into the problem of detecting the inverse DBF. The pattern generation process can then be done by using an ATPG tool for dynamic bridging faults. A complete procedure to generate both test and diagnosis patterns to detect all testable TDFs and DBFs as well as to distinguish them is then presented. In this flow all TDFs, DBFs, and all fault pairs between the two types of faults can be modeled in a single circuit and dealt with in a few ATPG runs. Thus the pattern generation process is quite efficient and very compact pattern sets can be obtained by utilizing the test pattern compaction feature of the ATPG tool. Experimental results on ISCAS89 benchmarks show that our procedure can detect all detectable TDFs and DBFs and 99.94% of fault pairs between DBFs and TDFs can either be distinguished or identified as equivalent-fault pairs.

Fault diagnosis plays a major role in IC yield enhancement. Due to circuit structure and ATPG limitation, there exist many undistinguished fault pairs after applying test patterns and diagnosis patterns, including equivalent fault pairs and aborted fault pairs. This paper proposes a scan-based repair-for-diagnosis architecture that can distinguish undistinguished fault pairs by repairing cell defects. A repairable standard cell design technique is presented that makes the repair of defective cells easy to control. To efficiently distinguish all targeted undistinguished fault pairs, a novel fault-grouping method is developed and applied to the proposed scan-based repair-for-diagnosis architecture. With this architecture, one can distinguish multiple fault pairs and repair those defective cells hence improving yield at the same time. Experimental results show that our proposed architecture can distinguish all targeted undistinguished fault pairs and repair the defective cells with low area overhead.

IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.

This work proposes a novel test architecture that combines the advantages of both scan-based and built-in self-test (BIST) designs. The main idea is to record (store) all required compressed test data in a novel scan chain structure such that the stored data can be extracted, reconstructed and decompressed into required deterministic patterns using an on-chip test controller with a test pattern decompressor. The recording of test data is achieved by modifying the connections between scan cells. Techniques to extract test data from the modified scan cells and to deliver decompressed test patterns to the modified scan cells are presented. The on-chip test controller can automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external ATE. Experimental results on OpenSPARC T2, a publicly accessible 8-core processor containing 5.7M gates, show that all required test data for 100% testable stuck-at fault coverage can be stored in the scan chains of the processor with less than 3% total area overhead for the whole test architecture.

In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10% of test response data of already very compact test sets are needed to detect all testable stuck-at or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27% of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.

This paper presents a systematic approach to transform various fault models to a unified model such that all faults of interest can be handled in one ATPG run. The fault models that can be transformed include, but are not limited to, stuck-at faults, various types of bridging faults, and cell-internal faults. The unified model is the aggressor-victim type of bridging fault model. Two transformation methods, namely fault-based and pattern-based transformations, are developed for cell-external and cell-internal faults, respectively. With the proposed approach, one can use an ATPG tool for bridging faults to deal with the test generation problems of multiple fault models simultaneously. Hence the total test generation time can be reduced and highly compact test sets can be obtained. Experimental results show that on average 54.94% (16.45%) and 47.22% (17.51%) test pattern volume reductions are achieved compared to the method that deals with the three fault models separately without (with) fault dropping for ISCAS'89 andIWLS'05 circuits, respectively.

TSV-based 3D-IC design can reduce the connection length of stacked ICs and enhance I/O bandwidth of heterogeneous integrated circuits. However the testing of 3D ICs is more complicated than that of 2D ICs. This paper presents an efficient on-chip 3D-IC test framework that can embed the test procedure of TSVs into the memory BIST process. By using the same test patterns generated from the memory BIST mechanism, the faults in both memories and TSVs can be detected simultaneously without extra time to test TSVs. The area overhead for on-chip testing can also be reduced significantly. Experimental results show that the proposed test framework can gain a good performance in test time reduction with very low area overhead penalty for a memory-logic stacked IC.

Fault Diagnosis is a critical process to identify the locations of physical defects in advanced integrated circuits. Current diagnosis tools often report multiple types of faults as defect candidates. Thus an efficient method to distinguish different types of faults is highly desired. Stuck-at and bridging faults are two most commonly used DC fault models during diagnosis. In this paper we present an efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults. Two major techniques are proposed. The first one is a fault-inactivation method (FIM) that can quickly distinguish most fault pairs by inactivating one fault while detecting the other in each fault pair. The second one is a fault-types-transformation method (FTTM) that can transform the problem of distinguishing a stuck-at fault and a bridging fault into the problem of detecting a stuck-at fault. Both methods involve only one copy of the original circuit and require only an ordinary ATPG tool for stuck-at faults. Furthermore, both methods can deal with multiple fault pairs at a time and thus not only is the required CPU time small but also the dynamic test compaction capability of the ATPG tool can be utilized. Experiments on a large number of randomly selected fault pairs in ISCAS'89 and IWLS'05 benchmark circuits have been carried out. The results show that the FIM can distinguish about 91.9% of distinguishable fault pairs quickly and the FTTM can distinguish all other distinguishable fault pairs and identify all equivalent fault pairs. The average ratio of the number of diagnosis patterns over that of the test patterns for stuck-at faults is only 0.64. On average, one diagnosis pattern can distinguish 10.89 fault pairs.

Output-bit selection is a recently proposed test-response compaction approach that can effectively deal with aliasing, unknown-value, and low-diagnosis problems. This approach has been implemented using a single counter and a multiplexer without considering unknown values. Also, such an implementation may require the application of a pattern multiple times in order to observe all selected responses. In this paper, we present a multiple-counter-based architecture with a new selection algorithm that can avoid most unknown-values yet achieve high compaction ratio. The remaining small number of unknowns can then be dealt with using some simple masking logic. Experiments on IWLS'05 circuits show that even with 16% unknown responses, all unknown values can be handled with 88.92%~93.21% response-volume reduction still achieved and only a moderate increase in test-application time.

This paper presents an efficient transition-fault diagnosis pattern generation procedure to identify equivalent-fault pairs and generate diagnosis patterns for nonequivalent-fault pairs. Two major techniques are proposed. The first one is a fault-inactivation method that can quickly distinguish most fault pairs by inactivating one fault while detecting the other in each fault pair. The second one is a fault-transformation method that can transform the problem of distinguishing two transition faults into the problem of detecting a transition fault. Both methods involve only one copy of the original circuit and require only an ordinary ATPG tool for transition faults. Furthermore, both methods can deal with multiple fault pairs at the same time and thus not only the total CPU time can be significantly reduced but also the dynamic test compaction capability of the ATPG tool can be utilized. Experimental results on all possible transition-fault pairs of both ISCAS'89 and IWLS'05 benchmark circuits show that the fault-inactivation method can distinguish about 95.6% of distinguishable fault pairs quickly and the fault-transformation method can deal with almost all the remaining indistinguished fault pairs. The average ratio of the number of diagnosis patterns over that of original test patterns is only 0.41.

This paper proposes an efficient diagnosis-aware ATPG method that can quickly identify equivalent-fault pairs and generate diagnosis patterns for nonequivalent-fault pairs, where an (non)equivalent-fault pair contains two stuck-at faults that are (not) equivalent. A novel fault injection method is developed which allows one to embed all fault pairs undistinguished by the conventional test patterns into a circuit model with only one copy of the original circuit. Each pair of faults to be processed is transformed to a stuck-at fault and all fault pairs can be dealt with by invoking an ordinary ATPG tool for stuck-at faults just once. High efficiency of diagnosis pattern generation can be achieved due to 1) the circuit to be processed is read only once, 2) the data structure for ATPG process is constructed only once, 3) multiple fault pairs can be processed at a time, and 4) only one copy of the original circuit is needed. Experimental results show that this is the first reported work that can achieve 100% diagnosis resolutions for all ISCAS'89 and IWLS'05 benchmark circuits using an ordinary ATPG tool. Furthermore, we also find that the total number of patterns required to deal with all fault pairs in our method is smaller than that of the current state-of-the-art work.

During an at-speed scan-based test, excessive capture power may cause significant current demand, resulting in the IR-drop problem and unnecessary yield loss. Many methods address this problem by reducing the switching activities of power-risky patterns. These methods may not be efficient when the number of power-risky patterns is large or when some of the patterns require extremely high power. In this paper, we propose discarding all power-risky patterns and starting with power-safe patterns only. Our test generation procedure includes two processes, namely, test pattern refinement and low-power test pattern regeneration. The first process is used to refine the power-safe patterns to detect faults originally detected only by power-risky patterns. If some faults are still undetected after this process, the second process is applied to generate new power-safe patterns to detect these faults. The patterns obtained using the proposed procedure are guaranteed to be power-safe for the given power constraints. To the best of our knowledge, this is the first method that refines only the power-safe patterns to address the capture power problem. Experimental results on ISCAS'89 and ITC'99 benchmark circuits show that an average of 75% of faults originally detected only by power-risky patterns can be detected by refining power-safe patterns and that most of the remaining faults can be detected by the low-power test generation process. Furthermore, the required test data volume can be reduced by 12.76% on average with little or no fault coverage loss.

Modern on-chip communication protocols such as advanced eXtensible interface and open core protocol support advanced transactions to improve communication efficiency. Out-of-order transactions that allow responses to be returned in an order different from their request order play an important role in this improvement. However, a deadlock situation may occur if these transactions are not properly manipulated. In this paper, we address the deadlock problem in an on-chip bus system supporting out-of-order transactions. We present a graphic model that can well represent the status of a bus system and show that a cycle exists in the graph if and only if the bus system is in an unsafe state that may lead to a bus deadlock. Based on this model, we propose a novel bus design technique that can efficiently resolve the bus deadlock problem. Experimental results show that buses with the proposed technique can be up to 3.3 times faster than those with the currently available techniques.

Reseeding techniques have been adopted in BIST to enhance fault detect ability and shorten test application time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need large storage space to store all required seeds. In this paper, we propose a new LFSR reseeding technique that employs the internal net responses of the circuit itself as the control signals to change the states of the LFSR. A novel test architecture containing a net selection logic module and an LFSR with some inversion logic is presented that can generate all required seeds on-chip in real time without any external or internal storage requirement. Experimental results on ISCAS benchmark circuits show that the presented technique can achieve 100% stuck-at fault coverage in a short test time by using only 0.23-2.36% of internal nets for reseeding control.

Twisted-ring-counters (TRCs) have been used as built-in test pattern generators for high-performance circuits due to their small area overhead, low performance impact and simple control circuitry. However, previous work based on a single, fixed-order TRC often requires long test time to achieve high fault coverage and large storage space to store required control data and TRC seeds. In this paper, a novel programmable multiple-TRC-based on-chip test generation scheme is proposed to minimize both the required test time and test data volume. The scan path of a circuit under test is divided into multiple equal-length scan segments, each converted to a small-size TRC controlled by a programmable control logic unit. An efficient algorithm to determine the required seeds and the control vectors is developed. Experimental results on ISCAS'89, ITC'99 and IWLS'05 benchmark circuits show that, on average, the proposed scheme using only a single programmable TRC design can achieve 35.58%-98.73% reductions on the number of test application cycles with smaller storage data volume compared with previous work. When using more programmable TRC designs, 83.60%-99.59% reductions can be achieved with only slight increase on test data volume.

Output selection is a recently proposed test response compaction method, where only a subset of output response bits is selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. One critical issue for output selection is how to implement the selection hardware. In this paper, we present a counter-based output selection scheme that employs only a counter and a multiplexer, hence involving very small area overhead and simple test control. The proposed scheme is ATPG-independent and thus can easily be incorporated into a typical design flow. Two efficient output selection algorithms are presented to determine the desired output responses, one using a single counter operation for simpler test control and the other using more counter operations for achieving a better test-response reduction ratio. Experimental results show that for stuck-at faults in large ISCAS'89 and ITC'99 benchmark circuits, 48%~90% reduction ratios on test responses can be achieved with only one counter and one multiplexer employed. Even better results, i.e., 76%~95% reductions, can be obtained for transition faults. It is also shown that the diagnostic resolution of this method is almost the same as that achieved by observing all output responses.

This paper proposes a new test-per-clock BIST method that attempts to minimize the test sequence length and the test data volume simultaneously. An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect the maximum number of so far undetected faults. During the seed determination process an adaptive X-filling process is first employed to generate a set of candidate patterns for pattern embedding. The process then derives a seed solution that can embed multiple candidate patterns at one time so as to minimize the number of seeds. To shorten the test sequence, the pattern embedding process begins with a small initial set of pseudo-random patterns and will incrementally add more patterns only when necessary. Experimental results show that compared with the previous test-per-clock techniques based on the LFSR- and twisted-ring-counter-reseeding methods, our method can reduce the test sequence length by over 60% with generally smaller numbers of storage bits. When compared with the mapping-logic-based BIST methods, our method can reduce the test sequence length by over 50% with a comparable area overhead.

Output selection is a recently proposed test response compaction method, where only a subset of output response bits is selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. We propose an output selection scheme for multiple scan designs, which employs only accumulators and multiplexers, and thus involves small area overhead and simple test control. An efficient selection procedure is presented to determine a minimal test set and the corresponding output bits to select for complete fault coverage. Experimental results show that when only one accumulator and one multiplexer are employed, 100% single stuck-at fault coverage for ISCAS'89 (ITC'99) circuits can be achieved by observing only 9.84% (8.19%) of the test response bits with only 1.86% (1.18%) area overhead.

Acceptable faults in a circuit under test (CUT) refer to those faults that have no or only minor impacts on the performance of the CUT. A circuit with an acceptable fault may be marketable for some specific applications. Therefore, by carefully dealing with these faults during testing, significant yield improvement can be achieved. Previous studies have shown that the patterns generated by a conventional automatic test pattern generation procedure to detect all unacceptable faults also detect many acceptable ones, resulting in a severe loss on achievable yield improvement. In this paper, we present a novel test methodology called multiple test set detection (MTSD) to totally eliminate this overdetection problem. A basic test set generation method is first presented, which depicts a fundamental scheme to generate appropriate test sets for MTSD. We then describe an enhanced test generation method that can significantly reduce the total number of test patterns. Solid theoretical derivations are provided to validate the effectiveness of the proposed methods. Experimental results show that in general an 80%-99% reduction in the number of test patterns can be achieved compared with previous work addressing this problem.

This paper presents a novel error-tolerance-based test methodology to grade defective chips according to their degree of acceptability so as to improve the effective yield of chips. We employ error rate as the attribute of error-tolerance to determine acceptability. We show that the number of test patterns that need to be applied to a circuit under test in estimating the circuit's error rate is highly dependent on how close the circuit's actual error rate is to the given grading thresholds. An iterative and adaptive error rate estimation technique is developed by which an appropriate number of test patterns can be efficiently determined and the circuit can be immediately classified into appropriate grades to fit various application requirements. Experimental results show that: 1) only a few iterations are required to classify a circuit, and 2) the total number of test patterns used is in general independent of the circuit size. Both of these observations imply that these techniques are applicable to large circuits.

The conventional output compaction methods based on XOR-networks and/or linear feedback shift registers may suffer from the problems of aliasing, unknown-values, and/or poor diagnosability. In this paper, we present an alternative method called the output-bit-selection method to address the test compaction problem. By observing only a subset of output responses, this method can effectively deal with all the above-mentioned problems. Efficient algorithms that can identify near optimum subsets of output bits to cover all detectable faults in very large circuits are developed. Experimental results show that less than 10% of the output response bits of an already very compact test set are enough to achieve 100% single stuck-at fault coverage for most ISCAS benchmark circuits. Even better results are obtained for ITC 99 benchmark circuits as less than 3% of output bits are enough to cover all stuck-at faults in these circuits. The increase ratio of selected bits to cover other types of faults is shown to be quite small if these faults are taken into account during automatic test pattern generation. Furthermore, the diagnosis resolution of this method is almost the same as that achieved by observing all output response bits.

This paper presents an effective hybrid test program for the software-based self-testing (SBST) of pipeline processor cores. The test program combines a deterministically developed program which explores different levels of processor core information and a block-based random program which consists of a combination of in-order instructions, random-order instructions, return instructions, as well as instruction sequences used to trigger exception/interrupt requests. Due to the complementary nature of this hybrid test program, it can achieve processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the processor local bus, while conventional methods that observe only the program results in the memory lead to significantly less processor fault coverage.

Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudo-random and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.

IEEE 1500 Standard defines a standard test interface for embedded cores of a system-on-a-chip (SOC) to simplify the test problems. In this paper we present a systematic method to employ this standard in a SOC test platform so as to carry out on-chip at-speed testing for embedded SOC cores without using expensive external automatic test equipment. The cores that can be handled include scan-based logic cores, BIST-based memory cores, BIST-based mixed-signal devices, and hierarchical cores. All required test control signals for these cores can be generated on-chip by a single centralized test access mechanism (TAM) controller. These control signals along with test data formatted in a single buffer are transferred to the cores via a dedicated test bus, which facilitates parallel core testing. A number of design techniques, including on-chip comparison, direct memory access, hierarchical core test architecture, and hierarchical test bus design, are also employed to enhance the efficiency of the test platform. A sample SOC equipped with the test platform has been designed. Experimental results on both FPGA prototyping and real chip implementation confirm that the test platform can efficiently execute all test procedures and effectively identify potential defect(s) in the target circuit(s).

In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.

Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan- or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external control is carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the design space of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.

To provide a new avenue for improving yield for nano-scale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.

We present a software-based test methodology that utilizes an on-chip processor to perform test procedures for direct-mapped data cache. The cache system under test is divided into two major groups, namely the memory modules and the logic modules. For the memory modules which include the tag memory, the data memory, and the physical address tag memory, systematic procedures to transform a widely-used March algorithm into various executable instruction sequences are developed. For the logic modules, extensive analysis on the functions as well as the structures (architecture, RTL, and gate-level) of these modules is carried out and effective test instruction sequences based on the analysis are derived. A 100% fault coverage for six conventional RAM fault models and 99.13% test efficiency for single stuck-at fault model are obtained on a real 32-bit RISC processor. These results validate the viability and effectiveness of the proposed methodology for data-cache testing.

Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new SBST methodology that uses information abstracted from the processor instruction set architecture (ISA), pipeline architecture model, RTL descriptions, and gate-level net-list for test program development of different types of the processor circuitry. This paper demonstrates the feasibility of the proposed methodology by the achieved fault coverage on a complex pipeline processor core. Comparisons with previous work are also made. Experimental results show its potential as an effective method for practical use.

This paper describes a core-based test and diagnosis integration and automation system, called Turbo1500, which automatically synthesizes test and diagnosis logic in accordance with the IEEE 1500 standard. Turbo1500 serves two major purposes. One is for use as a core test automation tool in a system-on-chip (SOC) environment to automatically connect multiple cores from various sources and create testbenches each targeting an individual core under the control of a chip-level test access port (TAP) controller. The other is for hierarchical (block-by-block) core test and diagnosis when chips on a printed-circuit board are embedded with 1149.1 boundary scan I/O cells and cores under test and diagnosis are surrounded with 1500-compliant wrapper cells. Application experience showed that the simplicity of the IEEE 1500 standard combined with an easy-to-use automation tool can make core-based design for test and diagnosis no longer a nightmare, especially when some cores are extremely large or complex.

Error-tolerance is an innovative technique to address the problem of low yields in nanometer very large scale integrated (VLSI) circuitry, which is the backbone of the system-on-a-chip (SOC) revolution. The basic principle of error-tolerance is that some chips may occasionally produce erroneous outputs, but still provide acceptable performance when used in certain systems. Using these chips in such systems results in an increase in effective yield. In this paper, a fault-oriented test methodology is presented for classifying whether or not a chip is acceptable based on error rate estimation. A sampling method is proposed to estimate error rate associated with each possible fault in the target circuit. According to this information, an approach is developed to identify a list of faults that are acceptable with respect to a specified upper bound on expected error rates of acceptable chips. Furthermore, a test pattern selection method, and an output masking technique are presented to identify tests which detect all of the unacceptable faults, and as few acceptable faults as possible, so as to maximize the effective yield. Experimental results indicate the high effectiveness of the proposed error rate estimation method, and the degree to which yield can be enhanced.

Employing a test platform in an SOC design has been shown to be an effective method for SOC testing. However the test efficiency problem of a test platform has not been addressed. In this paper, we formally analyze the test efficiency of test platforms and seek for its optimization. We formulate the required numbers of test cycles for test platforms implemented with different test structures and/or executed with different test procedures. It is shown that up to 24X test time difference for platforms with different test structures/procedures is possible. Based on the derived formula, an appropriate test platform that can achieve best test efficiency with minimal area overhead can be determined.

The main objective of error-tolerance is to increase the effective yield of a process by identifying defective but acceptable chips. In this paper, we propose an error-oriented test methodology to support error-tolerance in scan-based digital circuits. Error-rates of defective chips are first estimated and then compared with application-specific acceptable values of error-rates to determine the suitability of each chip. A theoretical basis to estimate error-rates of chips with a specified degree of confidence is presented. We determine an appropriate upper bound on the number of test patterns needed to satisfy a given estimation accuracy. To find out the yield improvement of the proposed test methodology, we present a method to determine the error-rate distribution of defective chips, and thus predict the fraction of defective chips that are acceptable. The proposed test methodology can support product grading, i.e., chips can be classified based on their actual error-rates such that best pricing for products used in different applications can be determined. Experimental results show that the proposed method accurately estimates error-rates of faulty chips, and the estimation results can be applied to increase the effective yield of a VLSI part as a function of various values of acceptable error-rate.

As the advance of VLSI technology approaches physical limitations, the yield associated with high performance system-on-chip (SOC) designs continue to decline. Conventional methodologies to address this problem, such as fault-tolerance and defect-tolerance, may become inadequate. Recently, the concept of error-tolerance has drawn much attention. Under this new concept, some defective chips (or systems) can still be labeled as acceptable, i.e., marketable, even if some outputted results are erroneous. The motivation for employing error-tolerance is to significantly increase the effective yield of some chips when used in certain applications. In this paper, we propose a novel error-rate based test methodology to support the notion of error-tolerance. Several definitions, such as various measures of yields, individual-fault and system error-rates, defect level and unacceptable defect levels are clarified or redefined. Analytically derived measures are formulated to estimate the error-rate associated with a fault, and to generate lists of faults that are acceptable with respect to a specified upper bound on the system error-rate. These results include consideration of the degree of confidence of an estimate, and provide a theoretic basis that enables the practical application of the concept of error-tolerance to both test set reduction and yield improvement. Experimental results show that the proposed test methodology can easily identify a set of acceptable faults, i.e., faults that might occur but need not cause the part to be discarded. The increase in effective yield depends on requirements imposed by end users. We show that a significant improvement in effective yield can be achieved for some applications.

Pipelined A/D converters have intrinsic high-speed characteristics and are widely used in wideband communication and video systems. In this paper, we propose a low-cost diagnosis methodology for pipelined A/D converters which employs three techniques in the diagnosis process: (1) time-division-multiplexing (TDM), (2) scan based testing, and (3) VCO based measurement. The last technique is developed to diagnose the most critical mixed-signal functional blocks in the pipelined ADC including the sample-and-hold amplifier (SHA) and the digital-to-analog sub-converters (DASC). It provides a great capability to distinct signals with very small voltage difference and is insensitive to process variations and immune to noise induced errors. The diagnosis methodology is power- and area-efficient because it only needs low-complexity and low-area BIST circuits to accomplish the full diagnosis process. A 12-bit pipelined A/D converter with the proposed diagnosis scheme is designed and simulated using the TSMC 0.25um 1P5M technology to demonstrate the effectiveness of the proposed methodology.

This paper proposes a method to reduce the excess power dissipation during scan testing. The proposed method divides a scan chain into a number of sub-chains, and enables only one sub-chain at a time for both the scan and capture operations. To efficiently deal with the data dependence problem during the capture cycles, we develop a multiple-capture-orders method to guarantee the full scan fault coverage. A test pattern generation procedure is developed to reduce the test application time and a test architecture based on a ring control structure is adopted which makes the test control very simple and requires very low area overhead. Experimental results for large ISCAS'89 benchmark circuits show that the proposed method can reduce average and peak power by 86.8% and 66.1% in average, respectively, when 8 sub-chains are used.

In this paper, a built-in self test (BIST) methodology to measure the four key parameters of A/D converters, namely offset error, gain error, integral nonlinearity error and differential nonlinearity error is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce analog sinusoidal test stimuli and digital sinusoidal reference signals on chip. By comparing the sinusoidal histogram of the ADC output signals with that of the generated reference digital signals, the parameters can be determined on chip based on some previously-derived equations. This BIST scheme has the following advantages: (1) high accuracy; (2) parameter measurement capability for different frequencies; (3) dynamic sinusoidal testing capability; and (4) low chip area overhead. An 8 bit A/D converter with the proposed BIST architecture is designed and simulated using the TSMC 0.35 /spl mu/m 1P4M technology. The simulation results show that the test accuracies for the four parameters are all within 0.05 LSB.

Scan-based design has been widely used to transport test patterns in a system-on-a-chip (SOC) test architecture. Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly modifying and integrating a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results for the International Symposium on Circuits and Systems (ISCAS) '85 and '89 benchmark circuits show that significant reduction on both test application time and power dissipation can be achieved compared to the conventional scan method.

Two problems that are becoming quite critical for scan-based testing are long test application time and high test power consumption. Previously, many efficient methods have been developed to address these two problems separately. In this paper, we propose a novel method called the multiple clock disabling (MCD) technique to reduce test application time and test power dissipation simultaneously. Our method is made possible by cleverly employing a number of existing techniques to generate a special set of test patterns that is suitable for a scan architecture based on the MCD technique. Experimental results show that on average 81% and 85% reductions in test application time and power dissipation have been respectively obtained when comparing to the conventional scan method.

In this work, we propose a new built-in self-testing (BIST) method that is able to concurrently test a set of spatially distributed embedded-memory modules with different sizes. Using the concept of redundant read-write operations, we develop a new march method, called RSMarch, to efficiently test each memory module. The new method has the advantages of low hardware overhead, short test time, and high-fault coverage. The total test time is dominated by large-size modules. To further reduce the test time, we also propose a split-mode test method to virtually partition each large memory array into smaller modules, which can be tested simultaneously.

Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes. The clock and data input capacitances of a latch are assumed the same as that of a regular gate. A double-latch FF thus consumes 5 transitions including the interconnection between latches when the data changes.

Presents a novel scan architecture for low-power testing, which employs the techniques of multiphase clocking, token ring, and clock-gating. When the multiphase clocking technique is directly employed to a scan chain, inter-phase skews and large routing area will be the problems. We develop a token scan cell design to address these problems. To reduce the power dissipation due to the clock and scan-in data trees, we propose a novel clock-gating technique that takes advantage of the regularity and periodicity of the token scan chain. Combining the three techniques, the token scan architecture can efficiently reduce the data transitions in the scan circuits as well as the switching activity in both the clock and the scan-in data trees. From experiments, more than 95% of power reduction can be achieved for most circuits with long scan chains.

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application time. The basic idea is to identify an input control pattern (CP) for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be reduced or even eliminated. A D-algorithm-like CP generator is developed to generate the CP. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve 22.37% of average improvement by redoing the experiments in previous work using our test sets, while 34.23% average improvement can be achieved if the input control technique is employed after the latch ordering and vector ordering techniques.

Using control and observation structures (COSs) to enhance the testability of analog circuits has recently received much attention. However, previous methods for generating COS are rather ad hoc. In this paper, we present an algorithm that can systematically generate all possible COSs based on the user's requirements. Extensive analysis on the common features, constraints, possible operations, and required number of switches and nodes for a COS has been carried out. Various kinds of matrices to represent the properties of COSs are defined. A compatibility checking method based on a transitive closure procedure is developed to identify the required COSs. Experimental results show that the algorithm can effectively generate all required COSs, including many COSs that are previously not identified.

In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead.

Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the core-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power. This method can be efficiently employed in a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. The improvement percentage can be up to 50% when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, 76% of peak-power reduction can be achieved.

Linear feedback shift registers (LFSRs) are used to generate both pseudorandom and deterministic patterns in the scan-based built-in self-test environment to raise the fault coverage and reduce the test cost. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time on feeding deterministic patterns from the LFSR into a scan chain. In this paper we derive a generalized relationship between the bits in the original scan chain and the states of the LFSR such that the bits generated by an LFSR in any future clock cycle can be pre-generated by the proposed test pattern generator. With this relationship, we can divide a scan chain into multiple sub-chains and use an LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time.

In this paper; a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator serves as a test input signal. A specific range of this signal is divided into 2/sup n+1/ segments, with each segment corresponding to one output combination of an n+1-bit counter; where n is the number of bits of the ADCs under test. The testing process is done with digital data processing by comparing the outputs of ADCs under test with the outputs of the n+1 bit counter. Simple structure, low area overhead, and high speed are the advantages of the proposed test structure.

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and the latch ordering techniques.

In this work, we propose a new built-in self-testing (BIST) method that is able to concurrently test a set of spatially distributed embedded-memory modules with different sizes. By allowing some redundant read/write operations for small modules, we develop a new march algorithm, called RSMarch, that can concurrently test all memory modules with the same fault coverage as if each module is tested individually. We also show that this method requires only one simple BIST controller and one test data line for all modules. Thus the new method has the advantages of short test time, high fault coverage and low area overhead.

Scan designs can alleviate test difficulties of sequential circuits by replacing the memory elements with scannable registers. However, scan operations usually result in long test application time. Most classical methods to solving this problem either perform test compaction to obtain fewer test vectors or use multiple scan chain design to reduce the scan time. For a large system, test vector compaction is a time-consuming process, while multiple scan chains either require extra pin overhead or need the sharing of normal I/O and scan I/O pins. In this paper, we present a novel test methodology that not only substantially reduces the total test pattern number for multiple circuits but also allows a single input data line to support multiple scan chains. Our main idea is to explore the "sharing" property of test patterns among all circuits under test (CUT's). By appropriately connecting the inputs of all CUT's during the automatic test-pattern generation process such that the generated test patterns can be broadcast to all scan chains when the actual testing operation is executed, the above-mentioned problems can be solved effectively. Our method also provides a low-cost and high-performance method to integrate the boundary scan and scan architectures. Experimental results show that 157 test patterns are enough to detect all detectable faults in the ten ISCAS'85 combinational circuits, while 280 are enough for the ten largest ISCAS'89 scan-based sequential circuits.

This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employingIDDQtesting can be achieved with only logic monitoring required.

An accurate threshold voltage determination method for CMOS gates is presented that can be used to enhance the performance of test pattern generation (TPG) and fault simulation (FS). By using this model the "Byzantine General" problem during the FS and TPG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation.

Article Using a single input to support multiple scan chains Share on Authors: Kuen-Jong Lee Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C. Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C.View Profile , Jih-Jeen Chen Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C. Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C.View Profile , Cheng-Hua Huang Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C. Dept. of E.E, Nat'l Cheng-Kung U. Tainan, Taiwan 70101, R.O.C.View Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 74–78https://doi.org/10.1145/288548.288563Online:01 November 1998Publication History 157citation256DownloadsMetricsTotal Citations157Total Downloads256Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively. Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model. Hence, the work of automatic test-pattern generation for a PLA and for other random logic ran be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLAs. Thus, this graph model can unify the data structure and operations required in PLA design and test.

Recently the bulk-driven current mirror technique has been employed in built-in current sensors for low voltage environment. This paper proposes 4 arrangements of built-in current sensors based on this technique. They are mainly different in biasing schemes end respectively take the advantages of simplicity, accuracy, flexibility and low power dissipation. From experiments, these sensors have small performance impact which causes only 0.3 V of power supply voltage drop and 0.3 ns delay of circuit speed degradation. These sensors require single external power supply and small area overhead.

In this paper we present two accurate and efficient modeling techniques for CMOS circuits to enhance the performance of test generation and fault simulation for bridging faults. The first one is a fault modeling technique for inter-gate bridging faults. The second one is an accurate threshold determination method. The accuracy of our model is achieved because all the following factors, including device parameters, voltage operation range of each logic value, resistance of ON-transistors, resistance of bridging faults, and test patterns are considered. The efficiency is achieved due to the simplicity of the solution methods that require no complex circuit level simulation. Experimental data show that SPICE like accuracy can be efficiently achieved.

This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intermediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.

The IEEE Boundary Scan Standard 1149.1 has been widely used for digital circuit testing. A similar standard for analog circuits is yet to be set up. In this paper we propose a new analog boundary scan architecture which is similar to the IEEE Std. 1149.1. The basic analog boundary scan cell, the defined instructions, the associated operations, and the control circuitry are described. The advantages of this architecture include: (1) Signal at various test points can be sampled simultaneously, (2) test stimuli can be injected to various test points simultaneously, and (3) test stimuli loading and test response outputting can be done simultaneously.

In-this paper, we present an efficient and accurate I/sub DDQ/ fault modeling technique for digital CMOS circuit. Both the normal and faulty "current" behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is obtained. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.

Signal flow direction information has been used to improve the accuracy and performance of many CAD tools. Hence deriving this information correctly and efficiently is an important and useful task. In this paper, an integrated system for deriving signal flow direction information in CMOS circuits is presented. This system consists of two subsystems: structure-based and rule-based. In the structure-based subsystem, a new graph-theoretic algorithm is used. The direction assignment problem is modeled as a two-paths problem on an undirected graph, called the global source target graph (GST-graph). The GST-graph is decomposed into split components by a linear time algorithm and the direction information of most edges in each split component can be derived by another linear time algorithm. If all transistors in a circuit are structurally unidirectional then their directions will be determined in this subsystem. Those transistors, if any, whose directions cannot be determined by this subsystem will be dealt with in the rule-based subsystem. A new set of rules including logic implication and precharge node driven rules have been developed. By considering circuit semantics, some difficult circuits such as a pass transistor based XOR gate, a six-transistor memory cell, barrel shifters, and precharge logic circuits can be processed. Experimental results show the accuracy and efficiency of this integrated system.

In this paper, a practical design for built-in current sensors (BICS's) is proposed. This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT). In addition, scalable resolutions and no external voltage/current reference make this design more effective and efficient than previous designs. Moreover this scheme can be used to monitor the current-related faults of both CMOS and non-CMOS circuits. Thus it is highly suitable for design for testability (DFT) on a multiple-chip module (MCM) or to be the current monitor on the test fixture under the quality test action group (QTAG) standard.>

Switch level test generation (SLTG) is potentially more powerful than conventional gate level test generation (GLTG) or CMOS circuits. Over the last decade much research has been carried out on SLTG. However to date no widely accepted SLTG system exists. The objectives of this work are to analyze the various problems associated with SLTG, to identify a feasible way to deal with these problems, and to develop an efficient and useful SLTG system for combinational circuits. The basic idea is to make use of as many GLTG concepts as possible without modeling a CMOS circuit at the gate level. Based on the analysis of CMOS circuits and faults, a SLTG system called SWiTEST has been developed. This system can deal with bridging, transistor stuck-open, transistor stuck-on and stuck-at faults. It employs both logic and current (IDDQ testing) monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework of this system is PODEM-based. To be applicable to switch level circuits, the basic PODEM algorithm has been enhanced to deal with concepts such as multiple objective selection, search-based backtracing and incremental event-driven logic implication. Experimental results indicate that SWiTEST is quite efficient in both CPU time and memory usage.>

In this paper an efficient method called the fast augmented state transition (FAST) test method is proposed to alleviate the testing problem of sequential circuits at the state transition level. By adding some extra logic gates to a sequential circuit under test the FAST method guarantees that each state of the augmented circuit has both the shortest distinguishing and synchronizing sequences, hence the testing complexity can be greatly reduced. The test length of the FAST method is shorter than any other exhaustive testing approaches based on the state transition level. Furthermore the test set for the augmented circuit can be easily identified.

All possible bridging faults (BFs) between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. Several examples are given to show that under certain circumstances current supply monitoring (CSM) cannot give correct test results. A circuit partitioning model is described, and a minimal set of design and test rules is presented. This set of rules is minimal in the sense that if any one of these rules is removed, then circuits exist for which CSM cannot give correct test results. When all the rules are satisfied it can be formally shown that: (1) all signal irredundant BFs can be detected by single vector tests, and (2) a test vector that detects a single bridging fault f/sub 1/ also detects all multiple BFs that contain f/sub 1/. To enhance the applicability of CSM, test and/or design strategies for dealing with circuits that do not satisfy each rule are proposed. Such circuits include a special exclusive OR gate, BiCMOS circuits, domino logic, synchronous sequential circuits, and circuits implemented by the silicon on insulator (SOI) technology.>

Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is 'what circuits does it apply to'. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.>

Signal flow directions of MOS transistors have been used in many CAD tools. A graph theoretic approach is presented for determining these directions. A MOS circuit is represented using several undirected graphs called ST-graphs. The direction assignment problem is modeled as a two paths problem in each ST-graph. Necessary and sufficient conditions under which all edges in an ST-graph are unidirectional are derived. A linear time algorithm is presented that assigns directions to all edges in an ST-graph if they all unidirectional. If bidirectional edges exist, the algorithm assigns directions to most edges in the ST-graph, and the remaining edges are resolved by a sequence of additional algorithms. Experimental results validate the performance benefits of this approach.>

The charge-sharing problem associated with the detection of CMOS stuck-open faults is analyzed. It is shown that this problem cannot be ignored if high-quality tests are required, and that assuming the worst-case condition and using conventional testing techniques may dramatically reduce the detectability of stuck-open faults. The authors present a layout-driven method to characterize this problem and show that by monitoring of the current supply this problem becomes much easier to solve. Through the use of current supply monitoring a very high improvement factor, which can easily offset the error caused by imprecise estimations of capacitance, has been obtained. It is demonstrated that by slight modification of the layout of a circuit the charge-sharing problem can be eliminated. A robust test generation procedure is also presented.>