This paper presents a method to consider a given SOC with pin and peak power constraints, and simultaneously (1) determine an optimal wrapper width for each core, (2) allocate SOC pins to cores and (3) schedule core tests to minimize the test completion time. For the first time the stated problem is formulated as a restricted 3 dimensional bin-packing problem and a heuristic to determine an optimal solution is proposed.

A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific test access mechanism (TAM). Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem. A best fit heuristic algorithm is employed to obtain satisfactory results.

This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

To predict the difficulty of testing a wire stuck-at fault, testability analysis algorithms provide an estimated testability value by computing controllability and observability. In all previous work, signal correlation between controllability and observability is generally ignored. As a result, the estimated value can be inaccurate. This paper discusses an efficient method to take into account signal correlation for testability analysis. Our experimental results have shown that, with little run time overhead, significant improvement of testability analysis can be achieved.

In this paper, we present a new method to characterize completely specified Boolean functions. The central theme of the classification is the functional equivalence (a.k.a. Boolean matching). Two Boolean functions are equivalent if there exists input permutation, input negation, or output negation that can transform one function to the other. We have derived a method that can efficiently identify equivalence classes of Boolean functions. The well-known canonical Fixed Polarity Reed-Muller (FPRM) forms are used as a powerful analysis tool. The necessary transformations to derive one function from the other are inherent in the FPRM representations. To identify uniquely each equivalence class, a set of well-known characteristics of Boolean functions and their variables (including linearity, symmetry, total symmetry, self-complement, and self-duality) are employed. It is shown that all the equivalence classes of four-variable functions are uniquely identified where majority of the classes have a single FPRM form as their representative. The Boolean matching has applications in technology mapping and in design of standard cell libraries.

Article Multilevel logic synthesis for arithmetic functions Share on Authors: Chien-Chung Tsai Mentor Graphics Corporation, Wilsonville, OR and University of California, Santa Barbara Mentor Graphics Corporation, Wilsonville, OR and University of California, Santa BarbaraView Profile , Malgorzata Marek-Sadowska Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA Department of Electrical and Computer Engineering, University of California, Santa Barbara, CAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 242–247https://doi.org/10.1145/240518.240563Online:01 June 1996Publication History 8citation376DownloadsMetricsTotal Citations8Total Downloads376Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

This paper presents a multilevel logic synthesis method that achieves 100% single stuck-at fault testability. We assume any cell library composed of AND/OR gates. The Fixed Polarity Reed-Muller forms are used to build the initial design. Algebraic factorizations and redundancy removal are two major steps that are used in deriving the final circuit. A predetermined set of input patterns is applied to identify redundancies and serves as the test set for the resulting circuit. Therefore, test pattern generation is not needed. Experimental results show that our method produces circuits with area comparable to Berkeley SIS 1.2.

In this paper, we present a new method for detecting groups of symmetric variables of completely specified Boolean functions. The canonical Generalized Reed-Muller (GRM) forms are used as a powerful analysis tool. To reduce the search space we have developed a set of signatures that allow us to identify quickly sets of potentially symmetric variables. Our approach allows for detecting symmetries of any number of inputs simultaneously. Totally symmetric functions can be detected very quickly. The traditional definitions of symmetry have also been extended to include more types. This extension has the advantage of grouping input variables into more classes. Experiments have been performed on MCNC benchmark cases and the results verify the efficiency of our method.

In this paper we present a new method for Boolean matching of completely specified Boolean functions.The canonical Generalized Reed-Muller forms are used as a powerful analysis tool.Input permutation, as well as input and output negation for matching are handled simultaneously.To reduce the search space for input correspondence, we have developed a method that can detect symmetries of any number of inputs simultaneously.Experiments on MCNC benchmark circuits are very encouraging.

We present a new method for detecting groups of symmetric variables in completely specified Boolean functions. The canonical Generalized Reed-Muller forms are used as a powerful analysis tool. To reduce the search space a set of signatures which identify quickly sets of potentially symmetric variables has been developed. Detecting symmetries of any number of inputs is done simultaneously. Totally symmetric functions can be detected very quickly. The traditional definitions of symmetry have been extended to include more types allowing the grouping of input variables into more classes. Experiments have been performed on MCNC benchmark circuits and the results are very encouraging.>

Each Boolean function with fixed polarity of variables can be represented uniquely in a two-level AND/XOR form, called the generalized Reed-Muller (GRM) form. The minimization problem is to find the optimal polarity that requires the least number of product terms in the GRM representation. An efficient algorithm was developed to extract product terms of Boolean function, given a polarity of variables. It achieves the lower bound complexity. A heuristic algorithm targeting the minimization problem is proposed. It derives the polarity for every variable and extracts all product terms simultaneously. It is based on the concept of a Boolean center for minterms, which emulates the center of gravity concept in geometry. The experimental results are very encouraging.>