As we approach the limits of Moore's law, researchers are exploring new paradigms for future high-performance computing (HPC) systems. Approximate computing has gained traction by promising to deliver substantial computing power. However, due to the stringent accuracy requirements of HPC scientific applications, the broad adoption of approximate computing methods in HPC requires an in-depth understanding of the application's amenability to approximations.

This paper covers the Rigorous Examination of Reactive Systems (RERS) Challenge 2019. For the first time in the history of RERS, the challenge features industrial tracks where benchmark programs that participants need to analyze are synthesized from real-world models. These new tracks comprise LTL, CTL, and Reachability properties. In addition, we have further improved our benchmark generation infrastructure for parallel programs towards a full automation. RERS 2019 is part of TOOLympics, an event that hosts several popular challenges and competitions. In this paper, we highlight the newly added industrial tracks and our changes in response to the discussions at and results of the last RERS Challenge in Cyprus.

State recoverability is a crucial aspect of speculative Time Warp-based Parallel Discrete Event Simulation. In the literature, we can identify three major classes of techniques to support the correct restoration of a previous simulation state upon the execution of a rollback operation: state checkpointing/restore, manual reverse computation and automatic reverse computation. The latter class has been recently supported by relying either on binary code instrumentation or on source-to-source code transformation. Nevertheless, both solutions are not intrinsically meant to support a reversible execution of third-party shared libraries, which can be pretty useful when implementing complex simulation models.

Data races in multi-threaded parallel applications are notoriously damaging while extremely difficult to detect. Many tools have been developed to help programmers find data races. However, there is no dedicated OpenMP benchmark suite to systematically evaluate data race detection tools for their strengths and limitations.

RERS is an annual verification challenge that focuses on LTL and reachability properties of reactive systems. In 2017, RERS was extended to a one day workshop that in addition to the original challenge program also featured an invited talk about possible future developments. As a satellite of ISSTA and SPIN, the 2017 RERS Challenge itself increased emphasis on the parallel benchmark problems which, like their sequential counterparts, were generated using property-preserving transformations in order to scale their level of difficulty. The first half of the RERS workshop focused on the 2017 benchmark profiles, the evaluation of the received contributions, and short presentations of each participating team. The second half comprised discussions about attractive problem scenarios for future benchmarks, like race detection, the topic of the invited talk, and about systematic ways to leverage a tool's performance based on competition benchmarks and machine learning.

The fully automatic generation of code that establishes the reversibility of arbitrary C/C++ code has been a target of research and engineering for more than a decade as reverse computation has become a central notion in large scale parallel discrete event simulation (PDES). The simulation models that are implemented for PDES are of increasing complexity and size and require various language features to support abstraction, encapsulation, and composition when building a simulation model. In this paper we focus on parallel simulation models that are written in C++ and present an approach and an evaluation for a fully automatically generated reversible code for a kinetic Monte-Carlo application implemented in C++. Although a significant runtime overhead is introduced with our technique, the assurance that the reverse code is generated automatically and correctly, is an enormous win that allows simulation model developers to write forward event code using the entire C++ language, and have that code automatically transformed into reversible code to enable parallel execution with the Rensselaer's Optimistic Simulation System (ROSS).

Various shape analysis algorithms have been introduced but their relation in terms of precision often remains unclear as different analyses use different representations of analysis results. The aim of our work is to extract alias sets from shape analysis results to compute a relative precision factor that expresses for a given program how much more precise one analysis is than the other. We present a significant improvement over an existing algorithm based on 3-valued logic to compute alias sets from shape graphs. Instead of looking only at the final nodes in pointer access paths, our common tail algorithm takes sequences of selectors into account. The common tail algorithm is strictly more precise than the existing algorithm by Reps, Sagiv, and Wilhelm, for our benchmarks we can reduce the number of conservative results by a factor of up to 5 in the best case while incurring an additional analysis overhead that is below 10% even in the worst case of our benchmarks. We selected two well-known graph-based shape analyses that use different representations of analysis results to demonstrate the usefulness of our approach. The shape analysis proposed by Nielson, Nielson & Hankin (NNH) and the analysis by Sagiv, Reps & Wilhelm (SRW) were implemented for a subset of C++ in the SATIrE program analysis framework. We are thus able to determine that NNH is more precise than SRW by a factor of 1.62 on average for our set of benchmarks.

Worst-case execution time (WCET) analysis is concerned with computing a precise-as-possible bound for the maximum time the execution of a program can take. This information is indispensable for developing safety-critical real-time systems, e. g., in the avionics and automotive fields. Starting with the initial works of Chen, Mok, Puschner, Shaw, and others in the mid and late 1980s, WCET analysis turned into a well-established and vibrant field of research and development in academia and industry. The increasing number and diversity of hardware and software platforms and the ongoing rapid technological advancement became drivers for the development of a wide array of distinct methods and tools for WCET analysis. The precision, generality, and efficiency of these methods and tools depend much on the expressiveness and usability of the annotation languages that are used to describe feasible and infeasible program paths. In this article we survey the annotation languages which we consider formative for the field. By investigating and comparing their individual strengths and limitations with respect to a set of pivotal criteria, we provide a coherent overview of the state of the art. Identifying open issues, we encourage further research. This way, our approach is orthogonal and complementary to a recent approach of Wilhelm et al. who provide a thorough survey of WCET analysis methods and tools that have been developed and used in academia and industry.

Distributed real-time automotive embedded systems have to be highly dependable as well as cost-efficient due to the large number of manufactured units. To close the gap between raising complexity and cutting costs, upcoming software standards like AUTOSAR introduce a clear separation of concerns into their system architecture. An AUTOSAR application is built from components that deal with business logic only whereas infrastructural services are provided by standardized middleware. Unfortunately, this middleware tends to be heavy-weight due to its coarse-grained layered design. By applying a component based design to AUTOSAR's middleware, a custom-tailored version for each specific application and system node can be built to overcome this problem. This paper demonstrates how to automatically synthesize component based middleware via the connector transformation: component connectors in platform independent application models are utilized to automatically assemble platform- and application specific middleware. As a result, AUTOSAR middleware becomes custom-tailored and hence light-weight and flexible. In addition, the described synthesis algorithm is capable of incorporating timing annotations via interface contracts at model level, and thus reflects upcoming ambitions to cover real-time constraints at middleware level within AUTOSAR. To prove our approach we successfully synthesized middleware for a demonstrator application and compared it to its conventional counterpart.

AUTOSAR as specified in its current version fosters timing-constraints at application level to support the development of real-time automotive applications. However, the standard's actual specification does not consider any timing information for its basic software. In consequence, the over-all timing-behavior of software running at a specific system node can not be calculated and thus validated at development-time. Even worse, any exchange or modification of basic software modules induces unpredictable alteration in system timing, and may even lead to a severe miss of execution deadlines. Within this paper we solve this issue by using a component based basic software architecture, as much as timing-aware software composition for basic software components. We therefore introduce timing contracts as enhancement for existing interface contracts, specify a timing annotation language on a conceptual level, and demonstrate how to capitalize on our approach by calculating timings within composed basic software architectures at development time.

Although conventional compilers implement a wide range of optimization techniques, they frequently miss opportunities to optimize the use of abstractions, largely because they are not designed to recognize and use the relevant semantic information about such abstractions. In this position paper, we propose a set of annotations to help communicate high-level semantic information about abstractions to the compiler, thereby enabling the large body of traditional compiler optimizations to be applied to the use of those abstractions. Our annotations explicitly describe properties of abstractions that are needed to guarantee the applicability and profitability of a broad variety of such optimizations, including memoization, reordering, data layout transformations, and inlining and specialization

Abstract Sophisticated parallel languages are difficult to develop; most parallel distributed memory scientific applications are developed using a serial language, expressing parallelism through third party libraries (e.g. MPI). As a result, frameworks and libraries are often used to encapsulate significant complexities. We define a novel approach to optimize the use of libraries within applications. The resulting tool, named ROSE, leverages the additional semantics provided by library‐defined abstractions enabling library specific optimization of application codes. It is a common perception that performance is inversely proportional to the level of abstraction. Our work shows that this is not the case if the additional semantics can be leveraged. We show how ROSE can be used to leverage the semantics within the compile‐time optimization. Copyright © 2004 John Wiley & Sons, Ltd.