Matrix placement machines improve production efficiency of printed circuit board assembly (PCBA), addressing critical needs for flexible and intelligent electronics manufacturing. However, their complex head structure renders solutions for traditional beam-head placement machines inefficient for matrix placement machines. This article proposes a phased hybrid algorithm with adaptive hyper-nondominated sorting genetic algorithm II (NSGA-II) for PCBA optimization. A bidirectional search mechanism is applied to derive feeder distributions and nozzle configurations, and iteratively tighten the solution space using priority-based search strategies. The softmax, max greatest common divisor, and max matching mechanisms are proposed for placement and pickup sequences, which facilitates construction of solution pools. Initial solutions are extracted from the pool and, subsequently, hyperheuristic mechanisms dynamically adjust genetic operators within NSGA-II to minimize placement, pickup, and recognition times with better convergence speed. Experimental validation with real-world production data demonstrates that the proposed algorithm achieves 6.05%–38.18% performance improvements compared to state-of-the-art solutions.

Operational efficiency of placement machines constrains the overall production capacity of printed circuit board (PCB) assembly lines. Existing state-of-the-art algorithms face challenges, such as conflicts between multiple objectives and coupling within different problems. This article proposes a multiobjective hybrid evolutionary multitasking algorithm (MOHEMTA) to address PCB assembly optimization in beam-head placement machines. The algorithm divides the problem into pickup and placement tasks, leveraging implicit parallelism to enhance solution efficiency. A nozzle block encoding method and heuristic decoding strategies with domain knowledge are introduced to reduce encoding complexity and accelerate algorithm convergence. MOHEMTA enhances offspring population diversity and quality through an elitist strategy, evolutionary operators, and knowledge transfer mechanisms, while incorporating safeguards against negative transfer. Experiments demonstrate that the multiobjective solution performance and practical results of MOHEMTA are better than those of other state-of-the-art algorithms.

In surface mount technology, solder paste printing quality critically affects product reliability. Accurate segmentation of solder paste regions is essential for defect detection, quantitative analysis, and process optimization. Traditional threshold-based methods lack robustness under varying surface textures and lighting, while deep learning approaches require large annotated datasets and expensive hardware, limiting their use in cost-sensitive manufacturing. We propose a fast, annotation-free segmentation framework based on parameteric multimodal learning, integrating RGB color with 3-D height data. Height priors generate an initial mask, followed by a lookup table–based parameteric color model that adapts to different printed circuit board types and batches. A convolutional feature fusion operator then constructs a joint height–color probability space, suppressing interference from substrate variations and uneven illumination, yielding a refined probability map for final segmentation. Tests on a 3D-solder paste inspection industrial dataset achieve 96.0% mean intersection over union and 98.8% pixel accuracy, matching state-of-the-art deep learning performance while greatly improving efficiency and suitability for real-world deployment without annotated data.

In printed circuit board assembly (PCBA), placement route schedule (PRS) significantly affects assembly efficiency of the beam head placement machine. The PRS is typically solved by decomposing it into placement point assignment problem (PPAP) and beam heads sequencing problem (BHSP). This article first proposes a deep reinforcement learning framework to tackle PPAP, which is a key determinant of overall process quality. Then, to mitigate the impact of placement position and angle on assembly efficiency, a dynamic programming-based beam head sequencing algorithm is introduced to solve BHSP. Since component types and placement point assignment states vary across different pick-and-place cycles, a dynamic combinatorial mask encoding method is proposed to effectively extract feature information between placement points. Inspired by the beam head placement process, a decoder that combines gated recurrent units and an attention mechanism is finally introduced, which fully utilizes historical node information to predict the next node. Experimental results demonstrate that the proposed method reduces PCBA routing distance by an average of 4.62%, outperforming other State-of-the-Art approaches.

Time-optimal path generation is critical for maximizing throughput in high-speed PCB assembly, yet existing approaches predominantly focus on geometric distance minimization, overlooking the fundamental impact of acceleration dynamics and multi-axis coordination on temporal efficiency. This study addresses this gap by introducing a physics-based time estimator that explicitly models trapezoidal acceleration profiles for synchronized X/Y/Z/R-axis motions, enabling precise performance evaluation under realistic kinematic constraints. Experimental validation on production PCBs demonstrates that the proposed estimator achieves much higher estimation accuracy, outperforming conventional methods. When integrated as the objective function in multi-chromosome genetic algorithm optimization, time-optimal solutions effectively reduce actual movement times compared to distance-optimal baselines, despite requiring longer travel paths. These findings confirm the time-optimal estimator’s superiority over pure distance minimization, proving that peak efficiency is achieved by balancing travel distance with movement speed.

Many studies have shown the significant benefits of using specialized hardware, such as Graphics Processing Units (GPUs), to accelerate Deep Learning tasks that require efficient large-scale data processing while maintaining high accuracy. Numerous software tools also exist that simplify model deployment. Given the large variety of hardware and software alternatives available, achieving optimal performance requires selecting and adapting the deployment to best suit each application. As highlighted in this article, performance depends not only on the hardware itself but also on the efficient design and implementation of the underlying code, to fully leverage available computational resources. To assess the impact of different implementation strategies on Deep Learning models and to better understand the tradeoffs between implementation complexity and application requirements, this work analyzes and compares two different approaches for deploying the EfficientAD visual anomaly detection model on GPUs. Notably, by increasing software development complexity to a limited and affordable extent, performance can be largely improved, achieving around 60% reduction in total execution latency.

In surface mount technology (SMT) assembly, the increasing complexity and miniaturization of electronic components pose critical challenges to balancing placement precision and production efficiency. This paper presents a quality-efficiency driven scheduling and process co-optimization (SPCO) methodology for the pick-and-place (PAP) process in SMT production lines. Leveraging a cyber-physical system framework integrated with automated optical inspection, the proposed approach dynamically couples offline scheduling with online process capability feedback to achieve adaptive allocation of components. A precision-aware SPCO model is formulated to assign components to placement heads based on real-time process capability indices, ensuring compliance with stringent precision constraints. To enable real-time deployment, a precision-prioritized allocation heuristic (PPAH) is introduced, supporting component-head assignments under heterogeneous head capabilities. Experiments on industrial datasets demonstrate that PPAH completely eliminates precision violations while improving the overall process capability margin by 2.6-fold compared to state-of-the-art benchmarks, with only a moderate increase in total PAP time. These results validate the effectiveness of the proposed co-optimization strategy in improving first-pass yield and robustness in high-mix SMT environments.

Printed circuit board assembly line scheduling (PCBALS) is a difficult task in the electronic industry for assembly lines using surface mounters, which is critical for production efficiency. This is a special type of line optimization problem that uses different allocation techniques, resulting in wide differences in assembly times between machines. This article proposes a hyper-heuristic optimizer embedded with a multifeature fusion ensemble estimator (HHO-MFEE) for PCBALS using linear-aligned-heads surface mounters. The objective and constraints of the problem are discussed, and a min-max integer model for small-scale problems is built. At the hyper-heuristic low level, seven data- and target-driven heuristics are presented for allocating components to different machines. Strategies for duplicated conditions with component types and placement points allocation are proposed to improve the applicability of the algorithm and the quality of the solution. An ensemble assembly time estimator that incorporates the coding of multifeatures, including estimated subobjectives, is proposed for evaluating the quality of the solution. Experimental results show that: 1) the gaps between the solution from HHO-MFEE and the optimal solution of the model are 3.44%~7.28% for small-scale data; 2) the proposed time estimator has higher accuracy than regression and heuristic-based ones, with mean absolute error of 2.01% and 3.43% for training and testing data, respectively; and 3) HHO-MFEE is better than other state-of-the-art algorithms, with average improvement of 7.21%~9.47%.

This brief presents an adaptive neural zeta-backstepping control strategy for a class of uncertain nonlinear systems, which allows these systems to be practically stabilized with predefined damping ratios. By introducing the zeta-backstepping technique, system damping ratios can be predetermined based on specific parameter selection rules. To reduce the impact of unknown nonlinearities, neural networks (NNs) with gradient descent training are applied to compensate such nonlinearities online. A new filter, called dynamic command filter, is used to construct the gradient of the NNs. By resorting to second-order Lyapunov stability criteria, it is proved that the closed-loop system is practically stable and has predefined damping ratio. Finally, experiments on a perturbed direct current (DC) motor system demonstrate the advantages of the proposed method.

Route scheduling for automatic optical inspection (AOI) of printed circuit boards (PCBs) impacts the productivity of surface mount production lines. Current state-of-the-art mathematical models in the area are not rigorous enough and neglect significant practical constraints, such as component geometric constraints. This article proposes a hierarchical mixed integer programming model to describe the route scheduling problem for AOI of PCBs. The model allows theoretical optimal solutions to be obtained for small-scale problems. In addition, a two-stage heuristic framework, consisting of clustering and path planning stages, is proposed to improve efficiency in solving large-scale problems, achieving near-optimal solutions. Taking into account that component distribution affects clustering results, the clustering stage is developed with a hierarchical heuristic algorithm based on block density with an aggregation strategy. The Lin–Kernighan algorithm is first used to quickly generate the scheduling sequence in the path planning stage. Image acquisition centers are initially adjusted with a customized heuristic. After that, a hybrid evolutionary multitask algorithm is proposed to further reduce path distance by dividing the image acquisition center adjustment task into several subtasks using heuristic rules. The algorithm obtains better quality results and is faster than traditional evolutionary algorithms. Experiments on an actual industrial AOI platform demonstrate that the proposed two-stage heuristic route scheduling algorithm outperforms state-of-the-art research in the area.

Structured light imaging is a typical technique for industrial 3-D microscopic measurement. Extensive research on structured light codecs has been conducted to accurately correlate camera and projector pixels. However, these methods suffer significant degradation when measuring low-reflectivity and complex surfaces. This article introduces a deep correlation-based cascade structured light network (CasSLNet) that utilizes deep phase and column features to calculate correspondences at the subpixel scale. To mitigate the huge computational cost of full correlation, a coarse-to-fine approach is proposed. Specifically, multiscale features from the camera observation sequence and the 1-D encoding pattern are extracted through a pseudosiamese network, and cascade cost volumes are constructed. An initial column map is then regressed from the low-resolution column cost volume. Based on this, an iterative update operator is introduced to refine initial estimates, resulting in a full-resolution column map. Furthermore, a structured light dataset has been collected and experiments have been conducted on a typical structured light imaging platform. Experimental results demonstrate that CasSLNet outperforms both traditional and state-of-the-art deep learning-based methods.

This article proposes a novel safety-critical control (SCC) framework based on embedded control barrier functions (EMB-CBF-SCC) for high-order strict-feedback nonlinear affine control systems. It is aimed at reconciling the potential conflict between predesigned desired trajectory and multiple safety constraints that could have different high relative degrees. Compared with existing CBF-based SCCs, our method can significantly reduce differential order and computational burden. Specifically, we first propose a novel concept of embedded control barrier function (EMB-CBF), which can reduce an arbitrary high-relative-degree safety constraint to relative degree one, and ensure safety of high-relative-degree systems. Further, EMB-CBF-SCC divides the original system into a top-level and a bottom-level subsystem. Then, it embeds between the two subsystems a quadratic program based on EMB-CBF, and introduces command filters to smooth virtual control inputs and obtain differential signals. Coordination performance of safety and stability is analyzed, considering the impact of filter errors. Finally, we present two real safety-critical robotic application scenarios with different safety constraint settings, namely, multiple state constraints for a single-link manipulator numerical model and dynamic obstacle avoidance constraints for a self-developed micro mobile robot experimental platform, respectively. The effectiveness of the proposed framework is demonstrated in both scenarios.

This article introduces a novel composite aerial vehicle configuration called hybrid quadrotor with all-moving wings (HQWAW), consisting of a conventional quadrotor combined with two independently all-moving wings. A nonlinear geometric controller in the special Euclidean group SE(3) is proposed as the basic controller for the HQWAW, achieving high maneuverability and energy-efficient flight. Lyapunov stability criterion is used to prove that the proposed control scheme can track the reference trajectory almost globally ultimately uniformly bounded. A deep reinforcement learning compensator, based on the twin delayed deep deterministic policy gradient algorithm, is designed to fine-tune all-moving wing angles, ensuring that wing surfaces remain at optimal angles, thereby maximizing aerodynamic efficiency and reducing rotor consumption. Tracking results for a trajectory involving high-speed dive followed by spiral ascent demonstrate that the proposed algorithm achieves both high maneuverability and improved energy efficiency of the HQWAW.

In mounting machines, vision measurement of surface mount devices (SMDs) is a crucial task, widely used for size calculation and defect detection. However, current vision measurement methods focus on specific SMDs, such as quad flat packages. There is no unified method for measuring all kinds of rectangular-pin components, which account for more than half of the SMDs processed in mounting machines. This article presents an automatic and universal method for measuring with subpixel accuracy the parameters of rectangular-pin SMDs, which can be applied to different types of SMDs. First, an edge gradient model is proposed in the form of asymmetric Gaussian function. After that, line segments of SMDs are extracted and a line adjacency matrix is obtained that describes the relationship between lines. Then, segments are combined into long lines by searching through the line adjacency matrix. Finally, pixel line pairs are refined to subpixel level. Experimental results on the surface mount hardware platform for different components under different angles and light conditions demonstrate the high accuracy and strong robustness of the proposed method.

Dual-gantry surface mount optimization effectively improves the productivity of printed circuit board assembly (PCBA), but also brings new challenges. Optimizing workload allocation to balance the front and rear gantry placement completion time is a significant challenge for improving PCBA productivity. This study proposes a finite potential game heuristic algorithm (FPGHA) to solve the workload allocation problem. The algorithm generates game agents by analyzing the feeding characteristics of the dual-gantry placement machine and using an improved bisection K-means clustering method. Agent utility is calculated based on metrics affecting productivity of the pick-and-place process, including the number of simultaneous pickups, nozzle changes, cycles, and mounting points. Nash equilibrium of FPGHA is obtained by a best-response dynamics and heuristic algorithm. Then, the effectiveness of FPGHA in solving the workload allocation problem is first demonstrated in simulated experiments with different nozzle and feeder configurations. Finally, FPGHA is compared with the hierarchical restricted balance algorithm, adaptive clustering algorithm, and the popular industrial optimizer software in actual placement experiments using real-world industrial printed circuit boards. The effectiveness and accuracy of FPGHA are verified by analyzing the correlation between three variables: The FPGHA estimated value, the actual assembly value, and the PCB assembly time.

The development of autonomous laboratories has significantly advanced with the integration of computer vision, simultaneous localization and mapping, cloud computation technologies, etc. These advancements have enhanced the automation and efficiency of experimental processes. However, the optimal management of complex task scheduling within such environments remains underexplored, especially in the face of challenges such as managing numerous tasks, adhering to strict time and state constraints, and ensuring the sustainable stability and performance of the entire laboratory operation. This article introduces a novel model predictive control (MPC)-based strategy for the optimal management of task scheduling in autonomous laboratories. Our approach begins with the abstraction of the scheduling problem as a finite state machine, which lays the foundation for a systematic analysis. We then employ concepts of invariant sets and stability to ensure that the pro posed scheduling strategy is not only efficient but also resilient to operational uncertainties. The proposed approach ensures recursive feasibility, which guarantees the adaptability of the scheduling strategy over time. Through a series of simulations, we demonstrate the efficacy of our MPC-based management strategy in optimizing task scheduling, thereby significantly enhancing the laboratory's operational efficiency, stability, and sustainability. Our findings offer promising insights into the future of autonomous laboratory management, providing a robust framework for tackling the complexities of task scheduling in such environments.

In this article, a practical finite-time command-filtered adaptive backstepping (PFTCFAB) control method is presented for a class of uncertain nonlinear systems with nonparametric unknown nonlinearities and external disturbances. Unlike PFTCFAB control techniques that use neural networks (NNs) or fuzzy-logic systems (FLSs) to deal with system uncertainties, the proposed method is capable of handling such uncertainties without the need for NNs or FLSs, thus reducing complexity and increasing reliability. In the proposed approach, novel function adaptive laws are designed to directly estimate unknown nonparametric nonlinearities and external disturbances by means of command filter techniques, and a type of practical finite-time command filters is proposed to obtain such laws. Moreover, the PFTCFAB controllers and finite-time command filters are designed with practical finite-time Lyapunov stability, which ensures finite-time stability of system tracking and filter estimation errors. Experimental results with a quadrotor hover system are presented and discussed to demonstrate the advantages and effectiveness of the proposed control strategy.

Nowadays segmentation Convolutional Neural Networks (CNNs) are used in industrial quality control systems to accurately measure the shape and size of production defects. However, these models are quite big and require quite powerful computing systems to be deployed in real applications. In order to obtain fast, power-efficient, and affordable implementations of segmentation CNNs for industrial quality control, in this paper execution time, memory usage, and power consumption measurements are carried out in different modern embedded GPU SoC devices, using different optimization strategies. Results show that segmentation CNNs can be deployed in embedded devices using FP16 or INT8 quantization with negligible accuracy loss and high throughput, up to 240fps.

Field-programmable system-on-chip (FPSoC) devices, combining high-performance processors and FPGA fabric in the same chip, are currently a leading technology in the design of complex digital systems. Since design times are longer than those of systems based on graphic processing units or standalone processors, many efforts are being devoted to develope efficient compilers from high-level languages. Even though, efficient processor-FPGA communication is still an important open issue. To contribute to this area, this article presents an extensive characterization of the processor-FPGA communication delays in Zynq-7000 devices. Although partial analyses of communication performance in these devices have been reported, this is the first work to address very important issues such as the use of DMA for data transfers or the effect of L2 cache controller settings and external RAM controller settings. As a result, data transfer rates are analyzed considering all parameters that influence them. The performance of Zynq-7000 devices is also compared to that of Cyclone V devices, hence covering the two most important current families that dominate the FPSoC market. This information is of utmost importance for designers to optimize processor-FPGA communication and, in turn, the performance of their FPSoC-based systems.

Fast Deep Neural Network (DNN) inference is nowadays possible thanks to the recent significant advancements in computing platforms and DNN frameworks. The advent of the Internet of Things, among other factors, leads to the massive deployment of edge computing devices, whose features and performance are very diverse. In order to help designers identify the hardware platforms and DNNs that best suit their target embedded applications, this paper presents a DNN inference performance analysis for state-of-the-art edge devices. These include Graphical Processing Units, Tensor Processing Units and Field-Programmable Systems-on-Chip. Different versions of the MobileNet and Inception DNNs and different frameworks are considered in the analysis.

This paper presents a case study and the underlying methodology of controller design for nonlinear multiple input multiple output systems. Deep neural networks are used to represent the controller policy and a reinforcement learning technique, namely Double Deep Q-Learning, is used to train it. The controller is designed from a simplified virtual model of the system and directly ported to the real system. This frees the designer from extracting an accurate model of the system (classic control theory approach), translating expert knowledge (fuzzy controllers), or acquiring large sets of data (supervised training of neural networks). Without loss of generality, the case study corresponds to the design of a 2-input 2-output line follower controller for unmanned ground vehicles (UGVs). Results show that the virtually-designed controller can drive real UGVs through the target trajectories with deviations within acceptable margins.

This paper presents a generic method to process mid-wave infrared (MWIR) images in laser-based manufacturing processes. The background noise of the camera is used as a source of information for correcting different problems that affect MWIR cameras. The mean of the noise distribution is used to correct the background drift due to sensor heat-up, whereas the standard deviation is used to generate dynamic thresholds for subsequent algorithms. The proposed method is portable, robust, and independent of the background, scale, and optical and electronic aberrations of the camera. The method is validated in the calculation of melt pool cooling rate. Performance is tested in a real scenario using a Field Programmable System-on-Chip platform. Results show that the system is capable of sending to a remote computer MWIR images at 1,435 frames per second and cooling rate information at a rate of 10,680 samples per second.

This paper presents a camera-based localization system for controlling unmanned ground vehicles in a 2D space using Field Programmable System-on-Chip devices, whose architecture combines powerful hard processors and FPGA fabric in the same chip. The FPGA captures and preprocesses images in real time while the hard processor is in charge of most image processing tasks. In these architectures, efficient data exchange between the hardware and software subsystems is a key feature to achieve high performance. In this case, versatile image writers have been designed to efficiently share images between the FPGA and the processor. The proposed free-software solution has been tested in Cyclone V devices, and compared with a previous pure hardware version of the system, as well as with other localization systems. Experimental results demonstrate that this system achieves better accuracy and higher frame rate than non-commercial localization systems in the literature, while being less expensive than commercial (closed) ones.

Atrial fibrillation (AF) is the most prevalent type of cardiac arrhythmia. As such, its early detection at a massive population scale is of paramount importance not only to avoid serious risks to people's health but also to ensure the sustainability of health care systems worldwide. Ambulatory monitoring can help mitigate these problems, and wearable devices can play a fundamental role in this regard. These devices can be equipped with sensors to measure cardiac activity, for instance from photoplethysmography (PPG) signals. The use of these sensors in wearable devices for AF screening faces several technological challenges. One of them is their sensitivity to interferences, in particular caused by patient's physical activity, which may be indistinguishable from cardiac activity. This paper presents a method to identify the periods of time during which PPG signals can be used because these effects are not present in them. Experimental results obtained from real patients show that by using the proposed method, a significant amount of valid data can be obtained, improving the usability of wearable devices for affordable AF ambulatory screening.

Decreasing profit margins and increasing concerns about animal welfare are boosting the interest for the development of monitoring and analysis technologies specifically targeting the poultry meat production process. In this context, this paper addresses monitoring of poultry activity in breeding farms. Specifically, it analyzes the suitability of different vision systems and image processing algorithms with this purpose. These systems and algorithms have been tested in an actual farm during a breeding cycle. Experimental results are presented demonstrating that density-based computations provide the best results, and that they can be carried out using either video or thermographic images, but the latter are a better option because of practical operating reasons related to varying, low light intensity conditions.

Education in industrial electronics-related subjects is very challenging because of the many different technological topics and application domains to be addressed. Mobile robotics is a very interesting area in this context, because it requires a wide coverage of many diverse topics and, at the same time, it is typically very appealing for engineering students. Therefore, mobile robot systems are very suitable platforms for the development of Project Based Learning solutions. This paper presents UviSpace, a modular, open-source intelligent space with Unmanned Ground Vehicles, which is being successfully applied for hands-on training of students in real-world problem solving in industrial electronics-related subjects. The hardware and software modules of the system are described, and student projects are discussed to demonstrate the usefulness and versatility of UviSpace as educational platform.

Decreasing profit margins and increasing concerns about animal welfare are boosting the interest for the development of monitoring and analysis technologies specifically targeting the poultry meat production process. In this context, this paper addresses one of the most critical steps of such process, the transportation of newborn animals from birth places to breeding farms. Specifically, an intelligent sensor system to monitor ventilation in truck trailers has been designed and validated. Experimental results obtained both in the lab and during real transportation trips are presented to demonstrate the suitability of the proposed system for the target application, in terms of cost, size, power consumption, and ability to operate at low air speeds.

As a type of Cyber-Physical Systems (CPSs), Smart Grid has been adding more communication and control capabilities to improve power efficiency and availability. Especially, more and more distributed control algorithms have been developed for Smart Grids because of their flexibility and robustness. In order to deploy them in real electric power systems, distributed control algorithms must be tested, not only in theoretical simulations, but also in testbeds subject to real world constraints that can provide feedback to make the algorithm robust. Implementations of these algorithms in a Smart Grid environment are facing many cyber-physical challenges such as possible communication failures or imperfections, noisy signals, etc. These challenges can lead to increasing economical expenditure or cause failure of the power system. There exist different approaches for testing distributed control algorithms, from using state-of-the-art facilities to software or hardware-in-the-loop simulations. To better emulate real-world electric grid operation scenarios with low capital investment, in this paper the Green City (GC) testbed is proposed as a suitable platform for both control theory researchers in Smart Grid, and for engineering education, allowing students to learn through hands-on experiences. GC has been conceived as a multi-agent networked CPS with the following main features: 1- Smart Grid environment emulation with low-cost physical elements; 2- Fast prototyping capability of distributed control algorithms for Smart Grid.

FPGAs have evolved from hardware accelerators to very powerful System-on-Chip platforms, mainly thanks to the availability of increasingly powerful embedded processors. The efficient integration of embedded processors with the FPGA fabric requires fast exchange of information between both sides, not to compromise the performance improvement these architectures should provide. Therefore, detailed performance analyses of different FPGA-processor communication scenarios are needed for designers to be able to evaluate the suitability of current devices for a given application, and to take the most advantage of them in it. This paper presents, to the best of authors' knowledge, the first reported characterization of FPGA-processor communications in Altera Cyclone V SoC devices. In this initial step towards a comprehensive study, the performance of communication mechanisms where the processor acts as master is analyzed.

Laser Metal Deposition (LMD) is a promising technique for fabrication of large metallic parts directly from 3D CAD models. However, the complexity of the process makes it challenging to prevent geometrical distortions and defects to affect the fabricated parts. On-line monitoring and control are fundamental issues to mitigate these problems, but they are not efficiently enough provided by current LMD techniques. As the first step in the development of an efficient unified on-line monitoring and control system for LMD, this paper presents a novel on-line 3D monitoring system for part geometry measurement. The system is capable of working in real-time in robot coordinates, without imposing restrictions to the possible paths, orientations or speed of movement. The use of ROS and the self-calibration method also proposed in the paper provide a flexible, cost-effective solution to easily upgrade current industrial LMD robotized cells. Experimental results support the practical feasibility of the proposed solution.

Field programmable gate arrays (FPGAs) have established themselves as one of the preferred digital implementation platforms in a plethora of current industrial applications, and extensions and improvements are still continuously being included in the devices. This paper reviews recent advancements in FPGA technology, emphasizing the novel features that may significantly contribute to the development of more efficient digital systems for industrial applications. Special attention is paid to the design paradigm shift caused by the availability of increasingly powerful embedded (and soft) processors, which transformed FPGAs from hardware accelerators to very powerful system-on-chip (SoC) platforms. New analog resources, floating-point operators, and hard memory controllers are also described, because of the great advantages they provide to designers. Software tools are being strongly influenced by the design paradigm shift, which requires from them a much better support for software developers. Focusing mainly on this issue, recent advancements in software resources [intellectual property (IP) cores and design tools] are also reviewed. The impact of new FPGA features in industrial applications is analyzed in detail in three main areas, namely digital real-time simulation, advanced control techniques, and electronic instrumentation, with focus on mechatronics, robotics, and power systems design. The way digital systems are being currently designed in these areas is comprehensively reviewed, and a critical analysis of how they could significantly benefit from new FPGA features is presented.

The ability to perform accurate localization is a fundamental requirement of the navigation systems intended to guide unmanned ground vehicles in a given environment. Currently, the use of vision-based systems is a very suitable alternative for some indoor applications. This paper presents a novel distributed FPGA-based embedded image processing system for accurate and fast simultaneous estimation of the position and orientation of remotely controlled vehicles in indoor spaces. It is based on a network of distributed image processing nodes, which minimize the amount of data to be transmitted through communication networks and hence allow dynamic response to be improved, providing a simple, flexible, low-cost, and very efficient solution. The proposed system works properly under variable or nonhomogeneous illumination conditions, which simplifies the deployment. Experimental results on a real scenario are presented and discussed. They demonstrate that the system clearly outperforms the existing solutions of similar complexity. Only much more complex and expensive systems achieve similar performance.

In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing locked) is required. When sensors observe a user's defined time guardband violation, safe operation is endangered and action can be triggered, either to reduce clock frequency or to increase core VDD. Simulation and experimental results are presented, using Spartan 6 boards and vendor tools. The testbench uses a Data Acquisition (DAQ) system with Triple Modular Redundancy (TMR) architecture and a Built-In Self-Test (BIST) infrastructure. It is shown that local sensors will anticipate system failure. Various devices are also used to analyze sensitivity to process variations.

Current industrial electronic control systems have been integrating innovative reconfigurable technologies, as those available through Field Programmable Gate Arrays (FPGA) and embedded systems, supporting development of different types of solutions, ranging from system-on-chip (SoC) solutions to networked and highly distributed and heterogeneous solutions. This paper brings an updated view on usage of FPGA, embedded systems, and SoC solutions for industrial electronic control.

Currently, frequency is the physical variable that can be measured with the best accuracy. Therefore, sensors based on frequency measurements are used in many industrial applications. QCM sensors are a kind of resonator-based sensors that allow mass variations in the nanogram-picogram range to be detected. This paper presents a high-accuracy frequency meter system for QCM sensors based on a Field-Programmable System-on-Chip architecture. A high-performance custom hardware peripheral integrated in a Nios II-based system has been implemented and experimentally validated. The obtained results demonstrate the suitability of the proposed system for the target application, as well as its potential to be extended to others. Some limitations and possible ways of improvement have also been identified.

The papers in this special section focus on the educational aspects of industrial informatics systems.

Laser cladding is a material processing technique widely used in industry for part reconstruction, coating or rapid prototyping, among other fields. When optical systems are used as sensing elements to measure the cladding area, malfunctions can occur because of interferences of suspended powder or damages to the cameras caused by laser beams. It is therefore important to provide means to detect problems affecting the optical system and, if possible, extend its life cycle by keeping correct performance even when damaged. In previous works, an FPGA-based measurement and control system for laser cladding has been proposed, which significantly outperforms other solutions used in industry, allowing some of their limitations to be overcome. This paper presents an improved FPGA system, capable of providing correct operation in the presence of suspended powder or (to some extent) other defects affecting the optical system. Experimental results obtained in an industrial part reconstruction system are presented that demonstrate the claimed contributions of the work.

The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to monitor parametric Process, supply Voltage and Temperature (PVT) and aging-induced variations. It can be used during product lifetime, as a predictive delay fault detection technique, either to avoid unreliable operation, or to guarantee correct functionality with lower power consumption. The usefulness of the proposed technique is demonstrated with part of the data processor of a complex design for a medical imaging system used in PET-based mammography, configured in a Virtex-4 FPGA device (xc4vfx60-11ff1152).

Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to an insufficiency of the usually adopted functional fault models. In this sense, these fault models are no longer able to correctly reproduce the effects caused by some defects generated during the manufacturing process. In this paper, we investigate the possibility of using Built-In Current Sensors (BICSs) to detect static faults associated to resistive-open defects in SRAMs. Experimental results obtained throughout electrical simulations demonstrate the BICSs' capability to detect the considered faults, while resulting in negligible degradation on the SRAM access time.

In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time management methodology, it is shown that nanometer technologies impose the need of fault-tolerance methodologies, although the margins of tolerance or fault-free operations are being reduced as technology scales down. SPICE simulation results with 350 nm, 130 nm, 90 nm, 65 nm, 45 nm and 32 nm CMOS technologies show an increasing dependence of propagation delays on power supply variations, as technology is being scaled down. Monte Carlo simulations show that, even in the presence of process variations, a dynamic delay-fault tolerance methodology can be rewarding even at nanometer scale, although the margins for Power-supply variations are becoming smaller.

The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology is reviewed, highlighting its characteristics and limitations. The underlying principle is to introduce on-line additional tolerance, by dynamically controlling the time of the clock edge trigger driving specific memory cells. Second, it is shown that the proposed methodology is still useful in the presence of process variations. Third, discussion and preliminary results on the automatic selection (at gate level) of critical FF for which DDB insertion should take place are presented. Finally, it is shown that parametric delay tolerance insertion does not necessarily reduce delay fault detection, as multi-vdd or multi-frequency self-test can be used to recover detection capability.

In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (Vdd) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional tolerance, by dynamically controlling the instant of occurrence of the clock edge trigger driving specific memory cells. On-line, dynamic delay insertion in the clock signal driving such memory cells is performed, according to local VDDand/or T variations, using a dynamic delay buffer (DDB) block. The circuit becomes more tolerant to power line and temperature fluctuations, while maintaining at-speed clock rate. Moreover, when clock frequency reduction becomes unavoidable, the methodology improves signal integrity when the disturbances start to occur, allowing time for the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for two sequential circuits are used to demonstrate the usefulness of the proposed methodology.

One of the most important issues in current high-performance packet switches is the availability of efficient algorithms to maximize instantaneous throughput. The PHM (parallel hierarchical matching) algorithm and its decoupled version, DPHM, are recently proposed distributed maximal size matching scheduling algorithms for virtual output-queued switches. In this paper, the design and evaluation of PHM/DPHM schedulers implemented in FPGAs is presented and discussed. Experimental results show that, in addition to the well-known advantages of using field-programmable logic, the proposed implementations provide a performance level which makes them a suitable alternative to ASICs for high-performance scheduling tasks

Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs to be evaluated. In this paper, a novel semi-empirical analytical model to compute, at logic level, the impact of power supply voltage variations (/spl Delta/V/sub DD/) and/or of temperature variations (/spl Delta/T) on speed response of a digital module is proposed. The model allows low-cost fault simulation. Moreover, it is shown that delay variation can be emulated either by a /spl Delta/V/sub DDi/ or a /spl Delta/Tj variation. The on-chip availability of multiple V/sub DD/ values in products with DVS (dynamic voltage scaling) opens opportunities for novel BIST techniques. A new DVS-based BIST approach is proposed and its ability to detect and diagnose resistive open defects is ascertained.

This paper presents a methodology for characterizing the behaviour of wavelet-based image coding systems in the presence of faults. This is a previous step in the development of efficient concurrent error detection techniques for such systems. The faulty behaviour of complex signal processing systems is better described at the algorithmic level (i.e., checking the accomplishment of a given functional property by large blocks of data) rather than using the ''classical'' approach at the structural (i.e., building block) level. Therefore, the issues related to algorithmic fault detection are addressed. Two different platforms for error characterization are presented and their main characteristics are discussed. Experimental results are presented that prove the suitability of the proposed methodology for the target application.

High-speed telecommunications routers are very important systems in today's networked environments. The purpose of this paper is to propose a mathematical model of the faulty behaviour of such systems and, derived from it, a scheme for the detection of errors occurring concurrently with their normal operation. Although the ultimate goal is to obtain a fault-tolerant router, this work concentrates on the scheduler part of the system and, in particular, in the case of virtual output-queued (VOQ) switches. As starting point, in this paper a balanced traffic load is assumed. The faulty behaviour of complex digital processing systems is usually better described at the algorithmic level, particularly when the operation of the system relies on complex mathematical principles. Therefore, the issues related to concurrent error detection are addressed from the developed mathematical model. Results are presented that point to the ability of the proposed solution to detect errors at a high abstraction level. They have been obtained by injecting faults in the algorithm flow rather than in the hardware itself.

Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-VDD test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulation it has been demonstrated that the effect of lowering VDD on the propagation delay time, while keeping invariant the observation pace at speed test, is similar to the effect of decreasing the clock period tCLKwhile keeping nominal VDD. In this paper, a simple analytical model to represent the dependence of propagation delay time variations of logic elements, Δpdon depleted VDD (i.e., on ΔVDD) is introduced. The model allows to back-annotate this dependence to logic-level fault simulation. As clock period decreases (or VDD decreases) failing vectors inducing errors are identified. Performance histograms, describing the dependence of the number of failing vectors on higher clock speed (or lower VDD) are used for delay fault detection and defect diagnosis. Basic infrastructures, ISCAS benchmarks and a combinational block of an industrial fleet management system, XTRAN, is used to demonstrate the results.

Today, encryption is widely used to incorporate privacy in data communications. Hardware implementations of encryption algorithms are fast enough to cope with the high throughput required in modern transmission channels. However, faults may occur in such circuits that can cause errors in encrypted text. A new technique is proposed to concurrently detect errors in block ciphers. It introduces very low area overhead in the system. In addition, a new encoding scheme is presented that has higher detection capabilities than other common error detection codes, when applied to encryption systems. Experiments conducted with widely used encryption algorithms (DES, RC5, IDEA and SKIPJACK) demonstrate the advantages of the proposed technique.