This article investigates the use of many-core systems to execute the disparity estimation algorithm, used in stereo vision applications, as these systems can provide flexibility between performance scaling and power consumption. We present a learning-based runtime management approach that achieves a required performance threshold while minimizing power consumption through dynamic control of frequency and core allocation. Experimental results are obtained from a 61-core Intel Xeon Phi platform for the aforementioned investigation. The same performance can be achieved with an average reduction in power consumption of 27.8% and increased energy efficiency by 30.04% when compared to Dynamic Voltage and Frequency Scaling control alone without runtime management.

Modern mobile and embedded devices are required to be increasingly energy-efficient while running more sophisticated tasks, causing the CPU design to become more complex and employ more energy-saving techniques. This has created a greater need for fast and accurate power estimation frameworks for both run-time CPU energy management and design-space exploration. We present a statistically rigorous and novel methodology for building accurate run-time power models using performance monitoring counters (PMCs) for mobile and embedded devices, and demonstrate how our models make more efficient use of limited training data and better adapt to unseen scenarios by uniquely considering stability. Our robust model formulation reduces multicollinearity, allows separation of static and dynamic power, and allows a 100× reduction in experiment time while sacrificing only 0.6% accuracy. We present a statistically detailed evaluation of our model, highlighting and addressing the problem of heteroscedasticity in power modeling. We present software implementing our methodology and build power models for ARM Cortex-A7 and Cortex-A15 CPUs, with 3.8% and 2.8% average error, respectively. We model the behavior of the nonideal CPU voltage regulator under dynamic CPU activity to improve modeling accuracy by up to 5.5% in situations where the voltage cannot be measured. To address the lack of research utilizing PMC data from real mobile devices, we also present our data acquisition method and experimental platform software. We support this paper with online resources including software tools, documentation, raw data and further results.

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-power-network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3× and 1.45× the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.

Modern embedded systems execute multiple applications, both sequentially and concurrently. These applications are exercised on heterogeneous platforms generating varying power consumption and system workloads (CPU or memory intensive or both). As a result, determining the most energy-efficient system configuration (i.e. the number of parallel threads, their core allocations and operating frequencies) tailored for each kind of workload and application scenario is extremely challenging. In this paper, we propose a novel runtime optimization approach with the aim of achieving maximized power normalized performance considering dynamic variation of workload and application scenarios. Fundamental to this approach is a comprehensive study to investigate the tradeoffs between inter-application concurrency with performance and power consumption under different system configurations. Using real experimental measurements on an Odroid XU-3 heterogeneous platform with a number of PARSEC benchmark applications, we model power normalized performance (in terms of IPS/Watt) underpinning analytical power and performance models, derived through multivariate linear regression (MLR). Using these models, we show that with increasing number of concurrent CPU intensive applications show variable gains in IPS/Watt compared to the memory intensive applications in both sequential and concurrent application scenarios. Furthermore, we demonstrate that it is possible to continuously adapt system configuration through a low-cost and linear-complexity runtime algorithm, which can improve the IPS/Watt by up to 125% compared to the existing approach.

Embedded systems execute applications with varying performance requirements. These applications exercise the hardware differently depending on the computation task, generating varying workloads with time. Energy minimization with such workload and performance variations within (intra) and across (inter) applications is particularly challenging. To address this challenge, we propose an online approach, capable of minimizing energy through adaptation to these variations. At the core of this approach is a reinforcement learning algorithm that suitably selects the appropriate voltage/frequency scaling (VFS) based on workload predictions to meet the applications' performance requirements. The adaptation is then facilitated and expedited through learning transfer, which uses the interaction between the application, runtime, and hardware layers to adjust the VFS. The proposed approach is implemented as a power governor in Linux and extensively validated on an ARM Cortex-A8 running different benchmark applications. We show that with intra- and inter-application variations, our proposed approach can effectively minimize energy consumption by up to 33% compared to the existing approaches. Scaling the approach to multicore systems, we also demonstrate that it can minimize energy by up to 18% with 2× reduction in the learning time when compared with an existing approach.

In this paper, we show that negative bias temperature instability (NBTI) aging of sleep transistors (STs), together with its detrimental effect for circuit performance and lifetime (LT), presents considerable benefits for power-gated circuits. Indeed, it reduces static power due to leakage current, and increases ST switch efficiency, making power gating more efficient and effective over time. The magnitude of these aging benefits depends on operating and environmental conditions. By means of HSPICE simulations, considering a 32-nm CMOS technology, we demonstrate that static power may reduce by more than 80% in 10 years of operation. Static power decrease over time due to NBTI aging is also proven experimentally, using a test chip manufactured with a 65-nm technology. We propose an ST design strategy for reliable power gating, in order to harvest the benefits offered by NBTI aging. It relies on the design of STs with a proper lower$V_{\textrm {th}}$compared with the standard STs. This can be achieved by either redesigning the STs with the identified$V_{\textrm {th}}$value or applying a proper forward body bias to the available power switching fabrics. Through the HSPICE simulations, we show LT extension up to$21.4\times $and average static power reduction up to 16.3% compared with the standard ST design approach, without additional area overhead. Finally, we show LT extension and several performance-cost tradeoffs when a target maximum LT is considered.

In this paper, we show that the vulnerability of memory components due to data retention in the presence of soft errors exhibit orders of magnitude variations with applications through extensive analysis of MiBench benchmarks. Underpinning such analysis, we propose a novel application-specific design flow for joint energy efficiency and reliability optimization. The energy efficiency is achieved through voltage/frequency scaling (VFS), while reliability is achieved through suitably choosing the appropriate protection policies (L1-Cache resizing and selective ECC) for hierarchical memory components. Fundamental to such joint optimization is a design analysis framework, which can analyze trade-off between memory protection policies considering the impact of VFS, and apply design optimization algorithm to provide with an energy-efficient design, while meeting a given reliability target. Using this framework the proposed design flow is validated through extensive number of application case studies based on ARMv7 processors modeled in GEM5. We show that the joint consideration of cache resizing and VFS can improve the L1-Cache reliability by up to 5x compared to VFS alone, while incurring <10% energy overhead. Additionally, using selective ECC for L2-Cache and DRAM, we show that energy consumption can be reduced by up to 40%.

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles.

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality.

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.

State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software, respectively. To validate the methodology, ARM® Cortex™-M0 embedded microprocessor (provided by our industrial project partner) is implemented in field-programmable gate array and further synthesized using 65-nm technology to quantify the cost in terms of area, latency, and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multibit errors for a wide range of fault rates.

Power gating is an effective technique for reducing leakage power which involves powering off idle circuits through power switches, but those power-gated circuits which need to retain their states store their data in state retention registers. When power-gated circuits are switched from sleep to active mode, sudden rush of current has the potential of corrupting the stored data in the state retention registers which could be a reliability problem. This paper presents a methodology for improving the reliability of power-gated designs by protecting the integrity of state retention registers through state monitoring and correction. This is achieved by scan chain data encoding and decoding. The methodology is compatible with EDA tools design and power gating control flows. A detailed analysis of the proposed methodology's capability in detecting and correcting errors is given including the area overhead and energy consumption of the protection circuitry. The methodology is validate using FPGA and show that it is possible to correct all single errors with Hamming code and detect all multiple errors with CRC-16 code. To the best of our knowledge this is the first study in the area of reliable power gating designs through state monitoring and correction.

Progressive coding of 3D textured graphic models using a joint mesh-texture optimization technique is investigated in this work. The mesh and texture data of a model are first fed into their respective compression modules to result in a series of levels of details. Then, for a given viewpoint, a rate-distortion surface is generated using these mesh and texture data. Afterwards, an optimal path over the rate-distortion surface is determined by the steepest descent algorithm. To achieve progressive transmission, the mesh and texture are transmitted in a certain ratio along the optimal path to provide the best visual quality for the given viewpoint. For further generalization, a layered sampling algorithm is proposed to deal with an arbitrary viewing angle. The performance of the proposed joint mesh-texture progressive coding algorithm is demonstrated by experimental results.

An optimized scheme of multiplexing coded mesh and texture data to facilitate progressive transmission of 3D textured models is proposed in this work. The mesh and texture data of a 3D textured model are fed into their respective compression modules and represented by a series of levels of details. Then, for a given viewpoint, a rate-distortion surface can be generated based on the multiplexing of mesh and texture data in different details. The distortion is calculated by measuring the visual quality of rendered images. Furthermore, an optimal path over the rate-distortion surface is determined by the steepest descent algorithm. When the mesh and texture data streams are transmitted in a certain ratio along the optimal path, it is guaranteed that the rendered images have the best visual quality perceived from the given viewpoint. To deal with an arbitrary viewpoint, we propose a hierarchical sampling algorithm so that the optimal path can be interpolated from finite sampling points. Experimental results demonstrate that the proposed method can provide the best visual quality of a 3D textured model for any observation point at any bit rate.

Progressive coding of 3D textured graphic models using a joint mesh-texture optimization technique is investigated in this work. The mesh and texture data of a model are first fed into their respective compression modules to result in a series of levels of details. Then, for a given viewpoint, a rate-distortion surface is generated using these mesh and texture data. Afterwards, an optimal path over the rate-distortion surface is determined by the steepest descent algorithm. To achieve progressive transmission, the mesh and texture are transmitted in a certain ratio along the optimal path to provide the best visual quality for the given viewpoint. For further generalization, a layered sampling algorithm is proposed to deal with an arbitrary viewing angle. The performance of the proposed joint mesh-texture progressive coding algorithm is demonstrated by experimental results.

A view-dependent graphics streaming scheme is proposed in this work that facilitates interactive streaming and browsing of three-dimensional (3-D) graphics models. First, a 3-D model is split into several partitions. Second, each partition is simplified and coded independently. Finally, the compressed data is sent in order of relevance to the user's requests to maximize visual quality. Specifically, the server can transmit visible parts in detail, while cutting out invisible parts. Experimental results demonstrate that the proposed algorithm reduces the required transmission bandwidth, and provides an acceptable visual quality even at low bit rates.

A graphics streaming system for walkthrough virtual environments is presented that facilitates reliable delivery and interactive browse of 3D models via wireless channels. Models are compressed by a partitioning-based progressive mesh compression algorithm to enable decorrelation of partitions and offer finer granularity. Then, the data of the virtual world are prioritized and organized according to viewer's requests. Finally, a transmission scheme is developed to adapt the sending rate to the available bandwidth and offer data protection techniques. Experimental results demonstrate that the proposed system reduces the required transmission bandwidth and provides an acceptable visual quality even at low bit rates.