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Morteza Afghahi

dblp:69/4307 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 80% Distributed systems · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
asynchronous circuit design		 0.011992
Performance of Synchronous and Asynchronous Schemes for VLSI Systems · IEEE Trans. Computers 1992
Integrated circuit design
clocking		 0.011992
Performance of Synchronous and Asynchronous Schemes for VLSI Systems · IEEE Trans. Computers 1992
Integrated circuit design › clocking
clock skew		 0.011992
Performance of Synchronous and Asynchronous Schemes for VLSI Systems · IEEE Trans. Computers 1992
Distributed systems
clock synchronization		 0.011992
Performance of Synchronous and Asynchronous Schemes for VLSI Systems · IEEE Trans. Computers 1992
Integrated circuit design › digital circuit design › sequential circuit design
synchronizer		 0.011992
Performance of Synchronous and Asynchronous Schemes for VLSI Systems · IEEE Trans. Computers 1992

Methods — techniques the papers use, named apart from their topics

system and delay modeling · 0.0
YearPublicationVenuePosition
1992 Performance of Synchronous and Asynchronous Schemes for VLSI Systems
abstract
Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the system size and operation speed increase, which leads to increased problems with timing and synchronization. System and delay models necessary for the study of time performances of synchronous and asynchronous systems are developed. Clock skew is recognized as a key factor for the performance of synchronous systems. A mode of clocking that reduces the clock skew substantially is proposed and examined. Time penalty introduced by synchronizers is recognized as a key factor for the performance of asynchronous systems. This parameter is expressed in terms of system parameters. Different techniques and recommendations concerning performance improvement of synchronous and asynchronous systems are discussed.>
Morteza Afghahi, Christer Svensson
 IEEE Trans. Computers1
1987 A high speed 2-D discrete cosine transform chip
B. Sikström, Lars Wanhammar, Morteza Afghahi, J. Pencz
 Integr.3