Given a synchronous sequential machine M, this correspondence deals with the fault-tolerant realization M of M and also its fail-safe realization M on the assumption that the faults that can occur to the circuitry of M or M are of permanent stuck-at type and the total number of faults can be at most some preset positive integer r. First, the realization of M or M is derived for r = 1 and then the same idea is extended to have the realization for any arbitrary r. It has been shown that the realization of M is such that it is also able to tolerate faults of nonpermanent nature.

In the present paper efforts have been made to arrive at the three-level NAND network of any general Boolean function by utilizing its complementary function. It has been shown that the knowledge of the complementing gates of the three-level NAND circuit with minimum number of gates in the AND level can readily be obtained from the study of the prime implicants of the complementary function. A reduced form of the Cover and Closure (CC) table is suggested which is applicable in the above three-level NAND network synthesis. The paper also deals with the recognition of the class of functions for which the use of the CC table may be avoided to obtain the same network.