Healthcare Education and Labeling for Cardiopulmonary Sounds, HEALSound, is an interactive platform designed to enhance the identification and labeling of adventitious cardiopulmonary sounds through gamification. HEALSound enables users, particularly medical professionals, to engage in exercises that improve their knowledge of abnormal heart and lung sounds while simultaneously contributing to the labeling of raw audio data. By incorporating real-time feedback and progress tracking, the app promotes continuous learning and provides a valuable crowdsourced resource for building high-quality labeled datasets over time. This dual-purpose platform not only aids in medical education but also contributes to the advancement of machine learning models for sound classification in healthcare. The system demonstrates a new potential for significant impact in educational and clinical environments by seamlessly integrating learning with data collection, ensuring scalability and the continuous improvement of cardiopulmonary sound databases.

Advances in digital stethoscopes and wearable health sensors now support real-time cardiopulmonary monitoring and AI-driven diagnostic tools. However, the extensive manual labeling required for large datasets of respiratory sounds presents a significant barrier, traditionally dependent on expert input. To address this, we introduce HEALSound, a mobile application designed to blend educational training with crowdsourced data labeling. By engaging users in interactive auscultation exercises and providing immediate feedback, HEALSound promotes skill development while generating high-quality labeled data through weighted consensus methods. Experimental results highlight the app’s dual effectiveness: enhancing diagnostic learning for users and accelerating the development of machine-learning models through enriched datasets, thus addressing critical challenges in AI-based health diagnostics.

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW,$1.4\times $–$3.8\times $less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step,$1.2\times $–$4\times $less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

This work introduces an innovative wearable health-care system that offers personalized cardiopulmonary monitoring by continuously capturing a variety of physiological signals. Users can engage with the system to view their own data in real-time, thereby gaining a nuanced understanding of its multi-modal sensing capabilities and the potential for remote health monitoring.

Continuous physiological sound monitoring is crucial for the prevention, diagnosis, and treatment of various diseases like cardiopulmonary and gastrointestinal conditions. Wearable healthcare sensors have emerged as a potent solution, streamlining the capture, storage, transmission, and analysis of individualized physiological sounds. However, challenges exist including large data volumes, limited hardware computational capabilities, and constrained transmission bit rates. To address these issues, we propose a physiological sound compression system using compressive sensing with self-adaptive compression ratio across sound types to implement physiological sound compression and Optimized Discrete Cosine Transform (ODCT) reconstruction to reduce loss in effective bands. Evaluated on SPRSound and PhysioNet 2016, our approach attains correlation coefficients of 0.863 and 0.883 for respiratory and cardiac sounds, with -3.14 dB and -1.84 dB signal-to-noise ratio loss at 3.5 and 3.0 compression ratios. Implemented on a custom healthcare sensor, our approach optimizes bit rate to 1.73× and power consumption to 0.82× compared to the uncompressed system.

This paper presents a VCO-based ADC design for use in flexible electronics, specifically leveraging Low-Temperature Polysilicon Thin-Film Transistor (LTPS TFT) technology. The design achieves a resolution of 8.11 bits at a 20 MHz sampling rate with a bandwidth (BW) of 2.5kHz. A linearity compensation technique combining a resistive input stage with a frequency-dependent resistor (FDR)-based feedback loop significantly enhances the VCO linearity. Simulation results validate the design, exhibiting an R2value of 0.9999 for the VCO tuning curve, a Signal-to-Noise and Distortion Ratio (SNDR) of 50.57 dB, and a Spurious-Free Dynamic Range (SFDR) of 52.34 dB at a supply voltage of 10V. The proposed design also features the lowest Figure of Merit (FoM) (0.73 nJ/conversion-step) compared with the state-of-the-art.

In this paper, we demonstrate a bi-directional biomedical process-invariant pixel interface based on the LTPS-TFT that integrates a front-end amplifier, an analog-to-digital converter and a stimulator. The pixel interface can convert biopotential into digital signals. This near-sensor signal processing can avoid the interference of motion artifacts, and the all-digital transfer has a high noise tolerance. Under the process variation of 1×-1.4× threshold voltage and ±10% mobility fluctuations, the DC gain of the operational amplifier changes from 58.83 dB to 57.21 dB, and 39.09 dB to 37.88 dB for the front-end amplifier. Compared with the single-stage amplifier, the stability has been improved by 13.2×. The proposed pseudo differential VCO-based ADC can effectively eliminate second-order non-linearity which achieves the best performance in state-of-the-art TFT-ADCs. When the threshold voltage and mobility fluctuate, ENOB changes from 7.36 bit to 7.30 bit (OSR=64) and 11.52 bit to 11.14 bit (OSR=256). The change rate does not exceed 4%.

The level shifter (LS) circuit has become an indispensable circuit component in both analog and digital systems. In the past decades, there has been an exponential increase in the academic publications for the LS circuits to improve their performances and their applications. Therefore, this review paper provides a comprehensive study of the LS circuit, ranging from circuit topologies and various design methodologies such as sizing methodology, layout design methodology, circuit evaluation methodology, and testing methodology. Finally, we evaluate the state-of-the-art LS circuits and present their performance metrics.

The implementation of a power-efficient neuron array system with high throughput and controllable mismatch plays an important role in power-sensitive applications and brain simulations. This paper presents an array of 48 Integrate-and-Fire neurons with axon-sharing architecture implemented in 55-nm CMOS technology. The combination of log-domain circuits and comparator-sharing in neuron design achieves the integration of 3125 neurons/mm2and power consumption of 5.3 pJ/spike. The proposed time modulated axon-sharing synapse architecture realizes 5500 events/s/neuron unit throughput. A novel background calibration module is integrated to reduce the mismatch between neurons. Simulations presents a 45% improvement in SD of inter-spike interval variation. Finally, we validate the architecture by implementing a spiking neural network for solving a 3-stage Sudoku Puzzle. 100% success rate is obtained after calibration.

This paper presents a multi-rate hybrid multistage noise shaping (MASH) ΔΣ modulator (DSM) with high tolerance to noise leakage. The front-end discrete-time (DT) stage works in a low sampling frequency while the back-end continuous-time (CT) stage runs in a 4X higher clock frequency. Thereby, the quantization noise of the first stage could be easily extracted by using feedforward topology. Moreover, the required upsampling behavior between the two stages is intrinsically implemented in the CT second stage without requiring an additional 4X upsampler. This multi-rate hybrid DT/CT DSM combines the accurate feature of DT loop filter and the high-speed advantage of CT loop filter. Eventually, it results in a high-speed operation for wideband applications while exhibiting a much higher tolerance to noise leakage compared to a conventional CT MASH structure. Simulations results demonstrate the efficacy of the proposed architecture.

Circuits based on tunneling FET (TFET) devices are fueling the beyond CMOS logic design, meeting the ultra-low-power demands for Internet-of-Things (IoT) applications. This paper presents a highly energy-efficient hybrid TFET/FinFET level shifter (LS) circuit, providing a robust signal up-conversion from deep subthreshold voltage. A pulse-triggered dynamic fully-regenerative latch and two modified dynamic current generators are incorporated to overcome the timing variation of input differential signals and current contention in the cross-coupled circuit. The simulation results show that the hybrid TFET/FinFET LS circuit has achieved a low propagation delay, dynamic power consumption, and power-delay-product (PDP) of ≤378 ps, ≤39.6 μW, and ≤13,950 ns-nW, respectively while converting the input signal from the ultra-low-voltage of sub-50mV to the nominal supply voltage of FinFET (0.8-1.2V). The proposed architecture has achieved up to 2.71-to-15.99x improvement in PDP compared to the reported state-of-the-art LS architectures.

A low-power and fast-transient capacitor-less low dropout regulator (CL-LDO) has been proposed in this paper. A class-AB amplifier with adaptive embedded slew-rate enhancement (SRE) circuit is employed to improve both the transient response performance and load current range. The proposed CL- LDO has been implemented in a 55-nm standard CMOS process and occupies an active chip area of 0.012 mm2. It is capable of delivering 0-10 mA load current and recovering within 0.075 ps under maximum load current change with 1.3 V supply voltage and 0.1 V dropout, while consuming only 1-pA quiescent current, demonstrating its potential capability to be applied in low power duty-cycling wireless sensor applications.

With Moore's law reaching its limits, the use of new materials or new devices' structure has emerged as the next generation of CMOS devices. Among all, tunneling field-effect transistors (TFETs) have achieved a steep sub-threshold slope of less than 60mV/decade yet there is a lack of a complete process design kit (PDK) for large-scale circuit design. Hence, we present an open-source 15nm TFET PDK (15nmTFETPDK), which is based on FreePDK15 with additional support for open-source TFET models and its associated Cadence Virtuoso pcell in OA format and Mentor Calibre physical verification files. Our users can design their circuit in the Cadence Virtuoso platform and verify the consistency of the drawn layout and the circuit through the Calibre Platform. We hope that this open-source PDK allows them to further advance their research with new emerging devices.

Thin-film transistors suffer from mechanical strain, which limits their performance in wearable systems. This paper proposes an IGZO-based omni-directional transistor (OT), whose force-insensitive axis can be aligned to the direction of the external force by dynamically adjusting the voltage on the top gates. As a result, the strain-induced variation on mobility and threshold voltage can be significantly attenuated. Based on the proposed OTs, a ring oscillator (RO) is designed and simulated by applying tensile force in different directions. The OT-based ring oscillator can achieve less than 1% frequency variation under a 0.4% induced strain, which is 12× lower compared with the conventional transistors.

Functional near-infrared spectroscopy (fNIRS) is considered as a non-invasive and effective brain-computer interface technology. Wearable high-resolution fNIRS requires a large-scale LED array, which consumes a lot of power, and shorten the battery life. This paper proposes a spatial adaptive sampling (SAS) method that can take advantage of the spatial sparsity of fNIRS devices and greatly reduce the power consumption while maintaining high image quality. To improve the performance of the proposed SAS technique, a low power binary neural network (BNN) is proposed to accurately predict the current brain task. And the optimal dynamic LED pattern for each brain task is investigated. The proposed SAS technique is validate through an off-line experiment, it can reduce the power consumption of the LED array by 62.5% compared to not using SAS technology while maintaining a PSNR (Peak Signal to Noise Ratio) of 33 dB.

Photoplethysmography (PPG) is one of the widely used noninvasive heart rate (HR) monitoring techniques in wearable devices. Lighting of the LED dominates the power consumption of a PPG sensor. Lowering the LED lighting duration is an effectively approach to save power. This paper proposes an adaptive heartbeat locked loop (AHBLL) technique, which can dynamically adjust the dividing ratio N according to the heart rate derivative (HRD). In this way, the LED pulse duty cycle can be significantly reduced to save power. To improve the robustness of the AHBLL system, the relationship between HRD and the dividing ratio N is theoretically analyzed, which provides an optimal design guideline. To verify the proposed technique, an HR sensing circuit including an HRD detector is designed and simulated. The results show that the LED power consumption is reduced by 2.2~3.3× compared with the state-of-the-art heartbeat locked loop (HBLL) technique.

Implantable medical microsystems need an efficient power and data transmission link. The demand for increasing the battery life requests for higher power transfer efficiency (PTE), whereas the increasing functionality of the implantable chip demands a higher data-rate. The traditional single-pair-of-coil link based on Amplitude-Shift keying (ASK) modulated Class-E amplifier tends to have limited immunity on the interference. In addition, due to the conflict on the quality factor (Q) between the power transmission and data transmission band, high PTE and high data rates are difficult to achieve at the same time. This paper proposes a power and data transmission link based on the adaptive duty-cycling binary phase-shift keying (BPSK) modulated Class-E amplifier. The Class-E works alternatively between two modes determined by two clocks with different duty-cycles. The variation of the duty-cycle modulates the phase of the carrier through the resonant networks of the Class-E amplifier. A low-power Costas Loop is adopted to efficiently synchronize the carrier and recover the data from an inductive received signal. The whole link has been implemented and simulated in a 350-nm CMOS process. The simulation shows under date-rate of 4 Mbps, the link achieves a PTE of 53% with an energy efficiency of 600 pJ/bit.

Thin-film transistor (TFT) circuits are important for flexible electronics which are promising in the area of wearable devices and Internet of Things. However, most flexible TFT technologies only have unipolar devices and the process variation and defective rate are relatively high, which impose challenges to TFT circuit design. In this paper, we propose a novel logic array design based on pseudo-CMOS logic to address the problems of unipolar TFT circuit design. A multilayer interconnection architecture is presented to improve the routability of circuit and the area efficiency. Cell mapping and wire routing algorithms, which aim to map the logic gates of circuit to logic array and then route the interconnection wires, are devised to improve the performance of circuit in consideration of parameter variations of TFT and meanwhile enhance the routability. The experimental results show that the proposed logic array along with design methodologies can reduce more than 80% area compared with transistor level scheme and help to improve performance significantly.

This paper proposes a novel auto loss compensation (ALC) system to enable non-contact operations for capacitive coupled body channel communication (CC-BCC). The system employs a time-division compensation mismatch indicator (CMI) to continuously monitor the compensation error, and dynamically adjust the compensation inductor through a PI controller. With the close-loop topology, the proposed ALC system has three advantages: First, the path loss induced by non-contact status and backward coupling effect can be compensated simultaneously; Second, this system can dynamically attenuate the path losses, even when the channel characteristics vary with time; Third, this system has high robustness, which is insusceptible to channel variations; The simulation results show that the loss reduction of the proposed ALC system is 18 dB higher than the conventional compensation technique in the worst case.