VLDB 2026 Research / reviewers in the wild / expert
Hariharan Sandanagobalane
dblp:70/3291
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 87% Program analysis · 13% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › prefetching
compiler-inserted prefetching |
0.0 | 1 | 2004 | Compiler orchestrated prefetching via speculation and predication · ASPLOS 2004 |
Compilers and program optimization
prefetching |
0.0 | 1 | 2004 | Compiler orchestrated prefetching via speculation and predication · ASPLOS 2004 |
Memory systems
memory access latency |
0.0 | 1 | 2004 | Compiler orchestrated prefetching via speculation and predication · ASPLOS 2004 |
Memory systems › cache
prefetching |
0.0 | 1 | 2004 | Compiler orchestrated prefetching via speculation and predication · ASPLOS 2004 |
Program analysis › program representation
dependence graphs |
0.0 | 1 | 2004 | Compiler orchestrated prefetching via speculation and predication · ASPLOS 2004 |
Methods — techniques the papers use, named apart from their topics
speculation · 0.1sentineled prefetching · 0.1predication · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Compiler orchestrated prefetching via speculation and predicationabstractThis paper introduces a compiler orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. We focus the scope of the optimization on specific subsets of the program dependence graph that succinctly characterize the memory access pattern of both regular array-based applications and irregular pointer-intensive programs. We illustrate how program embedded precomputation via speculative execution can accurately predict and effectively prefetch future memory references with negligible overhead. The proposed techniques reduce the total running time of seven SPEC benchmarks and two OLDEN benchmarks by 27% on an Itanium 2 processor. The improvements are in addition to several state-of-the-art optimizations including software pipelining and data prefetching. In addition, we use cycle-accurate simulations to identify important and lightweight architectural innovations that further mitigate the memory system bottleneck. In particular, we focus on the notoriously challenging class of pointer-chasing applications, and demonstrate how they may benefit from a novel scheme of it sentineled prefetching. Our results for twelve SPEC benchmarks demonstrate that 45% of the processor stalls that are caused by the memory system are avoidable. The techniques in this paper can effectively mask long memory latencies with little instruction overhead, and can readily contribute to the performance of processors today. Rodric M. Rabbah, Hariharan Sandanagobalane, Mongkol Ekpanyapong, Weng-Fai Wong |
ASPLOS | 2 |