Silicon height, width, and number of 3D stacked nanosheet layers are optimized in this paper to achieve lower power consumption, enhanced integration density, and higher performance with gate all-around (GAA) 3D stacked nanosheet transistors. Electrical characteristics of vertically stacked nanosheet transistors are compared with FinFETs under equal silicon area and ON current constraints. Assuming a tight vertical silicon sheet pitch of 5nm, test circuits with the vertically stacked nanowires provide comparable speed with active mode energy consumption, silicon area, and idle mode leakage power consumption savings of up to 40.24%, 21.81%, and 63.58%, respectively, as compared to FinFETs in a 5nm CMOS technology.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

Leakage power consumption of clock distribution networks (CDNs) is an important challenge in modern synchronous integrated circuits with billions of deeply scaled transistors. Multithreshold CMOS technology is commonly used to provide power reduction in standby mode while maintaining high performance in active mode. In this paper, a novel dual-threshold-voltage repeater circuit with split inputs-outputs (SPLIT-IOs) is employed for suppressing leakage currents in gated CDNs. Three floor planning strategies are considered for clock distribution across the chip with signal transition times of less than or equal to 50 ps at the leaves. Depending on the power supply voltage and floor plan, the standby leakage power consumption is reduced by 50.36%-78.43% with the proposed clock tree with SPLIT-IO repeaters as compared to the conventional three-level H-tree in a 45-nm CMOS technology. The spread of standby leakage power due to process variations is compressed by 36.72%-73.77% with the proposed clock tree as compared to the standard network. The proposed circuit technique significantly lowers the total energy consumption of partially active networks with local clock gating as well. The energy savings provided by the SPLIT-IO buffers are enhanced with the scaling of power supply voltage and frequency in synchronous systems-on-chip.

Design of static random access memory (SRAM) circuits is challenging due to the degradation of data stability, weakening of write ability, increase of leakage power consumption, and exacerbation of process parameter variations with CMOS technology scaling. An asymmetrically ground-gated nine-transistor (9T) MTCMOS SRAM circuit is proposed in this paper for providing a low-leakage SLEEP mode with data retention capability. The worst-case static noise margin and write voltage margin are increased by up to 2.52x and 21.84%, respectively, with the asymmetrical 9T SRAM cells as compared to conventional six-transistor (6T) and eight-transistor (8T) SRAM cells under die-to-die process parameter variations in a 65nm CMOS technology. Furthermore, the mean values of static noise margin and write voltage margin are enhanced by up to 2.58x and 21.78% with the new 9T SRAM cells as compared with the conventional 6T and 8T SRAM cells under within-die process parameter fluctuations.

A new variable strength keeper technique is presented in this paper for achieving higher-speed and lower-leakage currents in wide fan-in dynamic logic gates with carbon nanotube transistors. The strength of the keeper is dynamically adjusted depending on the logical state of the dynamic node during evaluation phase in a domino logic circuit. While providing similar noise immunity, the evaluation delay and power-delay product of the proposed domino logic circuits are reduced by up to 13.33% and 13.84%, respectively, as compared to the standard domino logic circuits in a 16nm carbon nanotube transistor technology. Furthermore, the proposed technique provides up to 77.98% savings in average leakage power consumption as compared to the standard domino logic circuits in idle mode.

Leakage power that is consumed by gigascale clock distribution networks is an important challenge in modern synchronous integrated circuits with billions of deeply-scaled transistors. A novel dual-threshold-voltage repeater circuit with split inputs and outputs is employed for achieving enhanced power efficiency in clock distribution networks in this paper. With the new repeaters, the mean of the statistical leakage power consumption distribution is reduced by up to 39.6% without increasing the layout area, active power consumption, clock skew, and clock period as compared to a conventional clock distribution network with standard static CMOS inverter based repeaters in a TSMC 65nm CMOS technology.

A novel static random-access memory (SRAM) cell with nine carbon nanotube MOSFETs (9-CN-MOSFETs) is proposed in this paper. With the new 9-CN-MOSFET SRAM cell, the read data stability is enhanced by 99.09%, while providing similar read speed as compared with the conventional six-transistor (6T) SRAM cell in a 16-nm carbon nanotube transistor technology. The worst-case write voltage margin is increased by 4.57× and 3.90× with the proposed 9-CN-MOSFET SRAM cell as compared with the conventional 6T SRAM cell and a previously published eight-transistor (8T) SRAM cell, respectively. A 1 Kibit SRAM array with the new memory cells consumes 34.18% and 12.27% lower leakage power as compared with the memory arrays with 6T and 8T SRAM cells, respectively, in idle mode. The overall electrical quality is enhanced by up to 13.63× with the proposed 9-CN-MOSFET memory circuit as compared with the other memory cells that are evaluated in this paper.

Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing power supply voltage in scaled CMOS technologies. Triple-threshold-voltage seven-transistor (7T), eight-transistor (8T), and nine-transistor (9T) SRAM cells are characterized for layout area, data stability, write voltage margin, idle mode leakage currents, data access speed, and active power consumption considering process parameter fluctuations in a TSMC 65 nm CMOS technology in this paper. The single-ended and differential read / write schemes are also compared for data access speed and power consumption in SRAM circuits.

The degraded read data stability and write ability of SRAM cells have become primary design concerns with CMOS technology scaling into the sub-22nm channel lengths. A new six-FinFET SRAM cell with asymmetrical bitline access transistors is proposed in this paper for enhancing the read data stability and suppressing the leakage power consumption in memory circuits. The bitline access transistor channel is underlapped on one side while overlapped by the gate terminal on the opposite side of the transistor. The asymmetrical bitline access transistors are weakened during read operations and strengthened during write operations as the direction of current flow is reversed. With the proposed asymmetrical six-FinFET SRAM cell, the read data stability is enhanced by up to 62% and the leakage power consumption is reduced by up to 49.3%, while maintaining similar write margin, cell layout area, read delay, and write delay as compared to a previously published asymmetrical six-FinFET SRAM cell in a 15nm FinFET technology.

Low-power, compact, and high-performance NP dynamic CMOS circuits implemented with a 16nm carbon nanotube transistor technology are presented in this paper. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated with two circuit techniques: the carbon nanotube MOSFET (CN-MOSFET) domino logic and the CN-MOSFET NP dynamic CMOS. While providing similar propagation delay, the total area of CN-MOSFET NP dynamic CMOS circuit is reduced by 13.61% as compared to the CN-MOSFET domino adder. Miniaturization of the CN-MOSFET NP dynamic CMOS adder reduces the dynamic switching power consumption by 30.42% as compared to the CN-MOSFET domino circuit. Furthermore, the CN-MOSFET NP dynamic CMOS circuit provides 49.32% savings in leakage power consumption as compared to the CN-MOSFET domino adder.

Switching speed, power consumption, standby leakage current, and silicon area are major concerns in buffer design. A novel dual-threshold-voltage buffer is proposed in this paper for higher energy efficiency and shorter propagation delay while driving high capacitive load. The novel buffer offers up to 23.3% shorter propagation delay, 13.6% less switching energy consumption, and 75.7% lower standby leakage current as compared to the conventional drivers under equal silicon area and identical extrinsic load capacitance conditions in a TSMC 65nm multi-threshold-voltage CMOS technology.

Multi-threshold CMOS (MTCMOS) is commonly utilized for suppressing leakage currents in idle integrated circuits. The deactivation/reactivation energy consumption however degrades the effectiveness of MTCMOS technique for providing significant savings in total energy consumption in CMOS integrated circuits. The mode transition energy overheads of various recently published low-noise ground-gated MTCMOS circuits are characterized in this paper. With a digital triple-phase sleep signal slew rate modulated MTCMOS circuit, the overall mode transition energy consumption is reduced by up to 45.31% as compared to the other MTCMOS circuits that are evaluated in this paper in a UMC 80nm CMOS technology. Furthermore, the digital triple-phase MTCMOS circuit shortens the mode transition timing overhead by up to 65.26% as compared with the other MTCMOS circuits that are evaluated in this paper.

Multi-threshold CMOS (MTCMOS) is commonly used for suppressing leakage currents in idle integrated circuits. Power and ground distribution network noise produced during SLEEP to ACTIVE mode transitions is an important reliability concern in MTCMOS circuits. Sleep signal slew rate modulation techniques for suppressing mode-transition noise are explored in this paper. A triple-phase sleep signal slew rate modulation (TPS) technique with a novel digital sleep signal generator is proposed. Reactivation time, mode-transition energy consumption, leakage power consumption, and layout area of different MTCMOS circuits are characterized under an equal-noise constraint. Influences of within-die and die-to-die parameter variations on the reactivation noise, time, and energy consumption of sleep signal slew rate modulated MTCMOS circuits are evaluated with a process imperfections aware robustness metric. The proposed triple-phase sleep signal slew rate modulation technique enhances the tolerance to process parameter fluctuations by up to$183.1\times$as compared to various alternative MTCMOS noise suppression techniques in a UMC 80-nm CMOS technology.

An asymmetrically ground-gated six-transistor (6T) SRAM circuit is presented in this paper for providing a low leakage data preserving SLEEP mode. By employing multiple write assist techniques, the write margin is enhanced by up to 2.73x and the write access time is reduced by up to 57.45% as compared with a previously published asymmetrically ground-gated 6T SRAM circuit in a TSMC 65nm CMOS technology. Furthermore, the new ground-gated 6T memory circuit enhances the data stability by 2.09x and reduces the leakage power consumption by 58.55% as compared to a ground-gated memory array with conventional 6T SRAM cells. A design methodology is presented to optimize the asymmetrically ground-gated 6T SRAM circuits for achieving the highest overall electrical quality.

A new threshold voltage tuning methodology is explored in this paper to minimize the peak power/ground bouncing noise with smaller sleep transistors in multi-threshold CMOS (MTCMOS) circuits. Different circuit techniques with the threshold voltage tuning strategy lower the activation noise, the activation delay, and the size of the additional sleep transistors by up to 27.76%, 32.66%, and 85.71%, respectively, as compared to a previously published noise-aware MTCMOS circuit with standard zero-body-biased high threshold voltage sleep transistors in a UMC 80-nm CMOS technology.

The influence of substrate voltage on carbon nanotube MOSFET (CN-MOSFET) performance is investigated in this paper. The optimum device profiles with different transistor sizes are identified for achieving the highest on-state to off-state current ratio (Ion/Ioff)Tradeoffs between subthreshold leakage current and device performance are evaluated with different substrate bias voltages. Technology development guidelines are provided for achieving low-leakage, high-speed, area efficient, and manufacturable integrated circuits with carbon nanotube transistors.

Uniformities of carbon nanotube diameters and nanoarray pitch values of all the transistors across a chip are required to enable low cost very large scale integration (VLSI) with the carbon nanotube technology. Nanotube diameter and nanoarray pitch are concurrently optimized and unified in this paper with two different substrate bias voltages considering a wide range of p-channel transistor sizes. A performance and density metric is evaluated to identify the optimum p-type device profiles suitable for very large scale integration with a 16nm carbon nanotube transistor technology.

Ground distribution network noise produced during sleep-to-active mode transitions is an important reliability concern in standard multi-threshold CMOS (MTCMOS) circuits. Different noise-aware sequential MTCMOS circuits are explored in this paper. A low-leakage data retention sleep mode is implemented with smaller centralized sleep transistors to suppress the ground bouncing noise produced during reactivation events in sequential MTCMOS circuits. Ground bouncing noise, leakage power consumption, data stability, and area overheads of different sequential MTCMOS circuits are evaluated with a 90-nm CMOS technology. The peak amplitude of ground bouncing noise is reduced by up to 94.16% with the noise-aware MTCMOS techniques as compared to the conventional Mutoh flip-flop. The application space of different data retention MTCMOS circuit techniques is identified with various design metrics in this paper.

New multi threshold voltage (multi-Vth) brute-force FinFET sequential circuits with independent-gate bias, work-function engineering, and gate-drain/source overlap engineering techniques are presented in this paper. The total active mode power consumption, the clock power, and the average leakage power of the multi-Vthsequential circuits are reduced by up to 55%, 29%, and 53%, respectively, while maintaining similar speed and data stability as compared to the circuits in a single threshold voltage (single-Vth) tied-32 nm-gate FinFET technology. Furthermore, the area is reduced by up to 21% with the new sequential circuits as compared to the circuits with single-Vthtied-gate FinFETs.

Ground bouncing noise produced during the sleep to active mode transitions is an important reliability concern in multi-domain Multi-Threshold CMOS (MTCMOS) integrated circuits. Ground bouncing noise, leakage power consumption, and data stability of MTCMOS flip-flops are evaluated in this paper. The effectiveness of different circuit techniques is discussed for achieving lower noise during the reactivation events while maintaining robust and low-leakage data retention capability in MTCMOS flip-flops.

Ground bouncing noise produced during reactivation events is an important challenge in multi-threshold CMOS (MTCMOS) circuits. A threshold voltage tuning technique based on forward body bias is proposed in this paper to alleviate the ground bouncing noise in sequential MTCMOS circuits. With the new threshold voltage tuning technique, the peak ground bouncing noise is reduced by up to 91.70% as compared to the previously published sequential MTCMOS circuits in a UMC 80nm CMOS technology. The design tradeoffs among various important design metrics are evaluated with different data preserving sequential MTCMOS circuits in this paper.

Two new clocking methodologies based on supply voltage and frequency scaling are proposed in this paper for lowering the power consumption and the temperature-fluctuation-induced skew without degrading the clock frequency. The clock signal is distributed globally at a scaled supply voltage with a single clock frequency with the first clocking methodology. Alternatively, dual supply voltages and dual signal frequencies are employed with the second methodology that provides enhanced power savings. The optimum supply voltage that minimizes clock skew is 44% lower than the nominal supply voltage in a 0.18 ¿m TSMC CMOS technology. Novel multi-threshold voltage level converters and frequency multipliers are employed at the leaves of the clock trees in order to maintain the synchronous system performance. The temperature-fluctuation-induced skew and the power consumption are reduced by up to 80% and 76%, respectively, with the proposed dual supply voltage and dual frequency clock distribution networks as compared to a standard clock tree operating at the nominal supply voltage with a single clock frequency.

Employing multiple supply voltages (multi- VDD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The new multi-Vthlevel converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.

Data stability of static random access memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also important sources of leakage since the majority of transistors are utilized for on-chip memory in today's high performance microprocessors and systems-on-chips. The use of work-function engineering to control the threshold voltage of FinFETs is explored in this paper for achieving minimum sized multi-threshold-voltage (multi-Vt) six transistor (6T) SRAM cells with sufficient data stability and lower leakage power consumption characteristics. A work-function optimization methodology for designing low power and high speed memory circuits is presented. With the proposed multi-Vt design methodology based on gate work-function engineering, the leakage power is reduced by up to 65X as compared to a standard single low threshold voltage (single- low-Vt) SRAM circuit sized for similar data stability in a 32 nm FinFET technology.

A new seven transistors (7T) dual threshold voltage SRAM cell is proposed in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the read speed. With the new 7T SRAM cell, the storage nodes are isolated from the bitlines during a read operation, thereby enhancing the data stability as compared to the standard six transistors (6T) SRAM circuits. The transistors of the cross-coupled inverters are not on the critical read delay path with the new technique. Minimum sized dual-threshold-voltage transistors are therefore conveniently used in the cross-coupled inverters for significantly reducing the leakage power consumption without causing a degradation in the read speed. With the proposed 7T SRAM circuit, the static noise margin and the read speed are enhanced by up to 87% and 17%, respectively, as compared to the conventional 6T SRAM circuits. Furthermore, the leakage and the write power consumptions of the proposed dual-V, SRAM circuit are reduced by up to 66% and 35%, respectively, as compared to the conventional 6T SRAM circuits in a 65 nm CMOS technology.

A new SRAM circuit technique based on dynamically adjusting the wordline voltage swing is proposed in this paper for reducing the leakage power consumption and enhancing the data stability in static memory banks. With the proposed technique, the wordline voltage swing is reduced in order to suppress the voltage disturbance at the data storage nodes during a read operation. The stability of a minimum sized standard six transistors (6T) SRAM cell is thereby significantly enhanced. Alternatively, during a write operation the wordline signal has a full voltage swing in order to achieve write-ability with a high write margin. With the proposed circuit technique, the static noise margin is enhanced by up to 122% as compared to the conventional full-voltage-swing 6T SRAM circuits with minimum sized transistors. Furthermore, the leakage power consumption with the proposed technique is reduced by 51% as compared to the conventional full-voltage-swing circuits sized for data stability in a 65nm CMOS technology.

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.

In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-Vt) and multi-oxide-thickness (multi-tox) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.

Multi-threshold voltage CMOS (MTCMOS) has emerged as an increasingly popular technique for reducing the leakage energy consumption of idle circuits. The MTCMOS circuits, however, suffer from high energy overhead during the transitions between the active and standby modes. A new circuit technique is proposed in this paper to lower the energy overhead of these mode transitions for effective energy reduction with the MTCMOS circuits. The charge stored at the virtual lines is recycled during the active-to-sleep-to-active mode transitions with the proposed technique. Applying the charge recycling MTCMOS circuit technique to a 32-bit Brent-Kung adder reduces the energy overhead of mode transitions by up to 36.3% as compared to the conventional MTCMOS circuits. Furthermore, the standby mode power consumption is reduced by 91.1% as compared to a standard Brent-Kung adder in a 65nm CMOS technology.

Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines during a read operation. A new nine transistor (9T) SRAM cell is proposed in this paper for simultaneously enhancing read stability and reducing leakage power consumption. The proposed 9T SRAM cell isolates the data from the bit lines during a read operation. The read static-noise-margin (SNM) of the proposed circuit is enhanced by 2times as compared to a standard 6T SRAM cell in a 65 nm CMOS technology. Furthermore, leakage power consumption of the new 9T SRAM cell is reduced by 22.9% as compared to the 6T SRAM cell. The read stability enhancement and leakage power reduction provided by the new circuit technique are also verified under process parameter variations.

A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a lower optimum supply voltage. To maintain the speed of the system, a dual supply voltage (dual-VDD) clock distribution network is presented. Level converters are utilized to restore the standard full swing clock signal at the leaves of the low voltage clock distribution network. A novel level converter with low skew, propagation delay, and power consumption characteristics is presented. The optimum supply voltage that minimizes clock skew is 44% lower than the nominal supply voltage in a 0.18μm CMOS technology. The temperature fluctuations induced skew and power consumption of the proposed dual-VDDclock distribution network are 74% and 50.8% lower, respectively, as compared to a standard clock distribution network operating at the nominal supply voltage.

Employing multiple supply voltages (multi-VDD) is attractive for reducing the power consumption without sacrificing the speed of an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The proposed level converters are compared with the previously published circuits for different values of the lower supply voltage. When the circuits are individually optimized for minimum power consumption in a 0.18μm CMOS technology, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, speed is enhanced by up to 78% with the proposed circuits.

A methodology based on supply voltage and frequency scaling for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in this paper. The clock signal is distributed globally at a scaled supply voltage and frequency. The optimum supply voltage that minimizes clock skew is 44% less than the nominal supply voltage in a 0.18μm CMOS technology. Combined frequency multiplier and level converter circuits are utilized at the leaves of the clock tree for restoring the standard full voltage swing clock signal with the higher target clock frequency in order to maintain the performance of the system. A novel dual-threshold-voltage frequency doubler with voltage level conversion capability, suppressed temperature fluctuations sensitivity, and low power consumption characteristics is presented. The temperature fluctuations induced skew and power consumption of the proposed dual-VDD/dual-frequency clock distribution network are reduced by up to 80% and 76%, respectively, as compared to a standard distribution network operating at the nominal supply voltage with the target system clock frequency.

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.

Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. Circuits display temperature variation insensitive delay characteristics when operated at a supply voltage 45% to 53% lower than the nominal supply voltage (V DD = 1.8V) in a 180nm CMOS technology. Integrated circuits operating at scaled supply voltages consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive in low power applications with relaxed speed requirements. The energy, delay, and energy-delay product (EDP) are compared at the supply voltages that yield temperature variation insensitive circuit performance and minimum energy-delay product. Results indicate that low-power integrated circuits can also be made insensitive to temperature fluctuations with a modest amount of increase in energy-delay product.

A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in idle domino logic circuits. In the sleep mode, the output inverter and keeper transistor of a domino gate are disconnected from the power supply by turning off a high threshold voltage sleep switch. The dynamic and output nodes are discharged by the initially high subthreshold and gate oxide leakage currents produced by the NMOS transistors in the pull-down network, output inverter, and fan-out gates. After the node voltages settle, the circuit is placed into a low subthreshold and gate oxide leakage state. The effectiveness of the circuit technique for suppressing leakage current is verified under significant fluctuations of channel length, gate oxide thickness, and channel doping concentration due to process variations. The proposed circuit technique lowers the total leakage power by 67.7% to 98.8% as compared to standard dual threshold voltage domino logic circuits. Similarly, an 11.7% to 84.1% reduction in total leakage power is observed as compared to a previous sleep switch scheme in a 45nm CMOS technology.

Temperature fluctuations alter threshold voltage, carrier mobility, and saturation velocity of a MOSFET. Temperature fluctuation induced variations in individual device parameters have unique effects on MOSFET drain current. Device parameters that characterize the variations in MOSFET current due to temperature fluctuations are identified in this paper for 180 nm and 65nm CMOS technologies. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature variations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented. Circuits display a temperature variation insensitive behavior when operated at a supply voltage 45% to 53% lower than the nominal supply voltage in a 180 nm CMOS technology. Similarly, the optimum supply voltages are 68% to 69% lower than the nominal supply voltage for circuits in a 65nm CMOS technology. The optimum supply voltages are similar for a diverse set of circuits in both technologies. The proposed technique of operating large scale designs at an optimum supply voltage for diminishing the performance sensitivity to temperature fluctuations is demonstrated to be feasible

A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors are utilized along with a dual threshold voltage CMOS technology to place an idle domino circuit into a low leakage state. The effectiveness of the circuit technique is evaluated for a wide-temperature spectrum, considering both long and short idle periods. Assuming a short idle period at a temperature of 110/spl deg/C, up to 95.6% reduction in leakage power is observed as compared to standard dual threshold voltage domino circuits. Alternatively, assuming a long idle period at the room temperature, the circuit technique reduces the leakage power by up to 96.9% as compared to the standard dual threshold voltage domino logic circuits. Furthermore, by employing PMOS-only sleep transistors, the presented circuit technique reduces the total leakage power by up to 43.8% as compared to a previously published sleep scheme based on NMOS sleep transistors in a 45nm CMOS technology.

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed by up to 60% while reducing power dissipation by 35% as compared to a standard domino (SD) logic circuit. The keeper size can be increased with the proposed technique while preserving the same delay or power characteristics as compared to a SD circuit. The proposed domino logic circuit technique offers 14% higher noise immunity as compared to a SD circuit with the same evaluation delay characteristics. Forward body biasing the keeper transistor is also proposed for improved noise immunity as compared to a SD circuit with the same keeper size. It is shown that by applying forward and reverse body biased keeper circuit techniques, the noise immunity and evaluation speed of domino logic circuits are simultaneously enhanced.

An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm/sup 2/ assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dual-V/sub DD/ microprocessor is demonstrated to be feasible.

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-Vt) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-Vt technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation.

Static energy due to subthreshold leakage current is projected to become a major component of the total energy in high performance microprocessors. Many studies so far have examined and proposed techniques to reduce leakage in on-chip storage structures. In this study, static energy is reduced in the integer functional units by leveraging the unique qualities of dual threshold voltage domino logic. Domino logic has desirable properties that greatly reduce leakage current while providing fast propagation times. However due to the energy cost of entering the low leakage current state (sleep mode), domino logic has thus far been used only for leakage reduction in the longterm standby mode. We examine the utility of the sleep mode (while considering the aforementioned costs) when idle times are relatively short, one to a few hundred cycles, as is often the case for functional units. Using an analytical energy model suitable for architecture-level analysis, we explore the interaction of the application and technology, and the effect on energy and performance as the underlying parameters are varied, on a set of benchmarks. Our results show that if the leakage approaches the magnitude as projected in the literature, even for short idle intervals as few as ten cycles, an aggressive policy of activating the sleep mode at every idle period performs well and a more complex control strategy may not be warranted. We also propose a simple design, called Gradual Sleep, to reduce the energy impact of using the sleep mode for smaller idle periods.