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Murat Bilgic

dblp:70/3946 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Logic in computer science · 100%
Computer graphics and multimedia
1 paper
Multimedia systems and quality of experience · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 62% Processor architecture and microarchitecture · 38%
Computer networks
1 paper
Internet architecture and protocols · 100%
Software engineering, system software, and programming languages
1 paper
Program verification · 100%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Multimedia systems and quality of experience
multimedia synchronization		 0.011996
Using Timed CSP for Specification Verification and Simulation of Multimedia Synchronization · IEEE J. Sel. Areas Commun. 1996
Logic in computer science
process algebra		 0.011996
Using Timed CSP for Specification Verification and Simulation of Multimedia Synchronization · IEEE J. Sel. Areas Commun. 1996
Logic in computer science › process algebra
timed CSP		 0.011996
Using Timed CSP for Specification Verification and Simulation of Multimedia Synchronization · IEEE J. Sel. Areas Commun. 1996
Internet architecture and protocols › protocol implementation
protocol processing		 0.011992
High Performance PDU Processing for Application Layer · HPDC 1992
Program verification
temporal logic verification		 0.011996
Using Timed CSP for Specification Verification and Simulation of Multimedia Synchronization · IEEE J. Sel. Areas Commun. 1996
Processor architecture and microarchitecture
instruction-level parallelism		 0.011992
High Performance PDU Processing for Application Layer · HPDC 1992
Processor architecture and microarchitecture › instruction set architecture › RISC
RISC processor		 0.011992
High Performance PDU Processing for Application Layer · HPDC 1992

Methods — techniques the papers use, named apart from their topics

temporal logic · 0.0simulation modeling · 0.0type-value matching · 0.0pipelining · 0.0parsing · 0.0parallelization · 0.0
YearPublicationVenuePosition
1996 Using Timed CSP for Specification Verification and Simulation of Multimedia Synchronization
abstract
Timed communicating sequential processes (TCSP) language is used to specify fine-grain and coarse-grain multimedia synchronization. A lip synchronization system is an example of fine-grain synchronization. Several groupware scenarios are examples of coarse-grain synchronization. The formal specifications are used as the basis of verification and simulation. Safety and liveness timing requirements of the synchronization system are stated in terms of temporal logic formulas. Correctness analysis of the specification is shown using the temporal formulas and TCSP proof theory. It is shown that TCSP is powerful enough to be used in multimedia system design and verification. Next, simulation of multimedia synchronization is discussed. Various simulation models are developed for fine- and coarse-grain synchronization systems. It is shown that simulation modeling can lead to early detection of possible synchronization violations. The buffering requirements of a given synchronization mechanism can be effectively studied using simulation.
Ahmet Feyzi Ates, Murat Bilgic, Senro Saito, Behçet Sarikaya
 IEEE J. Sel. Areas Commun.2
1993 Performance comparison of ASN.1 encoder/decoders using FTAM
Murat Bilgic, Behçet Sarikaya
 Comput. Commun.1
1992 High Performance PDU Processing for Application Layer
abstract
Encoding/decoding is a functionality which takes about half of the protocol processing. ASN.1 is a standard language to define messages of the application/layer. BER is the standard that describes encoding/ decoding of PDUs defined in ASN.1. The authors show that decoding can be divided into two phases: parsing and type-value matching. Algorithms are developed for these transformations. Distributed implementation of these algorithms can be achieved with specialized encoders/decoders. Four different architectures are defined for single-layer encoding/decoding. One of these architectures defined as VLSI-based ASN.1 encoder/decoder (VASN1) achieves better parallelisation as well as pipelining of parsing with type-alue matching subphases. VASN1 is composed of 16 instruction RISC processors. The processors used as execution units perform subphase transformations while the processor used as central controller assigns workload to the execution units. The processor used as interface unit takes care of input/output.>
Murat Bilgic, Behçet Sarikaya
 HPDC1