Agriculture not only plays a significant role in a nation’s economic development but is also the key to the survival of all life forms on this planet. Crop production has been immensely affected by global warming and the drastic changes in overall climate and rainfall patterns. Farmers who used to manually choose which crop to grow in a specific region given the soil, water, and atmospheric conditions can no longer do so owing to this change. Emerging technologies can be used to improve crop productivity by switching from traditional farming practices to relying on Machine Learning algorithms to monitor the soil and water quality along with the atmospheric conditions and to recommend the crops suitable to be grown based on these monitored factors. Having Internet of Things (IoT) work alongside Artificial Intelligence in our “Smart Farming System” has resulted in a powerful tool that will help farmers choose the right crop to grow. The soil parameters like soil nitrogen, soil phosphorus, soil potassium, soil moisture, and soil pH are gathered from the sensors using IoT. Similarly, atmospheric temperature is collected from another sensor using IoT. These values are fed into a chosen Machine Learning model, which performs the crop prediction. This prediction result is then sent to the mobile application, which acts as the User Interface (UI). This mobile application recommends suitable crops to farmers based on the parameter values collected from their fields and displayed on the application.

Convolutional Neural Networks (CNNs) have been explored to detect forced oscillations in windfarm systems in the past. However, these CNNs require a significant amount of data samples between inference queries and a significant amount of computational power and time. This leads to systems that have a large delay between a forced oscillation occurring and detecting the forced oscillation. This paper presents a novel approach applying Hyperdimensional Computing (HDC) as an effective solution for the first time in forced oscillation detection to overcome the problems of CNNs. HDC is able to reduce the time to detect forced oscillations in two ways: First, by reducing the time needed to collect data to create a new inference sample by reducing the number of data points required. Second, by providing a significantly smaller, more energy efficient, and faster model for detection than current state-of-the-art. Our results show that HDC, with an FPGA implementation, is able to achieve $ 55\times$ faster detection of forced oscillations in windfarms while achieving the same accuracy as the best current CNN models using software solutions.

This paper looks at performance bottlenecks of real-time object detection on edge devices. The "You only look once v4" (YOLOv4) is currently one of the leading state-of-the-art models for real-time object detection, and its tiny version: YOLOv4-tiny, is designed for edge devices. To improve object detection accuracy without sacrificing detection speed, we propose an object detection method based on YOLOv4-tiny and VGG-Net. First, we implement the mosaic data augmentation and Mish activation function to increase the generalization ability of the proposed model, making it more robust. Secondly, to enhance the richness of the features extracted, an extra 3x3 convolution layer is added in a way that two successive 3x3 convolutions are used to obtain 5x5 receptive fields. This would enable us to extract global features in the first CSP (Cross Stage Partial Network) Block and restructure the connections of the subsequent layers to have the same effect on the next CSP blocks. Evaluation results show that the proposed model has comparable performance and memory footprint but significantly greater accuracy than YOLOv4-tiny. Also, the proposed tiny model has similar performance to YOLOv4-tiny, and improves accuracy with much lower memory overhead, which makes it an ideal solution for real-time object detection, especially on edge devices.

Despite recent advances in deep learning, object detection and tracking still require considerable manual and computational effort. First, we need to collect and create a database of hundreds or thousands of images of the target objects. Next we must annotate or curate the images to indicate the presence and position of the target objects within those images. Finally, we must train a CNN (convolution neural network) model to detect and locate the target objects in new images. This training is usually computationally intensive, consists of thousands of epochs, and can take tens of hours for each target object. Even after the model training in completed, there is still a chance of failure if the real-time tracking and object detection phases lack sufficient accuracy, precision, and/or speed for many important applications. Here we present a system and approach which minimizes the computational expense of the various steps in the training and real-time tracking process outlined above of for applications in the development of mixed-reality science laboratory experiences by using non-intrusive object-encoding 2D QR codes that are mounted directly onto the surfaces of the lab tools to be tracked. This system can start detecting and tracking it immediately and eliminates the laborious process of acquiring and annotating a new training dataset for every new lab tool to be tracked.

Authentic hands-on laboratory research is essential for undergraduate STEM education. Yet the tactile authenticity required to impact affective, cognitive, or psychomotor learning outcomes associated with laboratory training remains underexplored. Virtual and mixed reality (VR/MR) have enabled increasingly realistic hands-on STEM training experiences. However, they still lack authenticity with regard to user manipulation of fully functional and realistic laboratory tools, analysis of realistic (i.e. user-acquired) noisy data, and the application of critical thinking skills to draw conclusions from such noisy (and possible faulty) data. Here we present efforts to develop such an approach while also providing faculty content experts tools for code-free customization of VR/MR training experiences via structured spreadsheets. This approach enables nuanced real-time user feedback on laboratory skills such as proper pipetting or sterile technique which are otherwise difficult to provide. It also offers complete safety from chemical, biological, and radiological hazards and is more cost-effective than a traditional lab. This Hands-On Virtual-Reality (HOVR) Lab platform is uniquely enabling and will be valuable in the physical and life sciences for both research and instructional applications.

Distributed cameras have been used widely for real-time image recognition. There are two main approaches in distributed camera systems: 1. The cameras are equipped with a powerful high-end processor for local image processing, 2. Low-cost cameras with resource-constrained processors are used for capturing the images and transferring them to a cloud server for classification purposes. The first approach is costly and not scalable. The second approach is too slow for real-time object detection due to the transfer delays to a remote server. These problems exacerbate in multi-view image recognition, where a central platform is required for collective image processing of multiple images from the same scene. So, there is a need for a scalable intelligent engine that can adapt itself based on the communication and processing delays and energy level of cameras (if battery operated) to accomplish real-time object recognition. This paper proposes to move from the traditional cognitive services based on training models in the cloud and requesting inference locally at cameras to a hierarchical bandwidth-efficient machine learning structure spread across cameras, edge devices and the cloud server for handling high density data streams.

In this paper, we present a new neural network architecture, MobileNet-Tiny that can be used to harness the power of GPU based real-time object detection in raspberry-pi and also in devices with the absence of a GPU and limited graphic processing capabilities such as mobile phones, laptops, etc. MobileNet-Tiny trained on COCO dataset running on a non-Gpu laptop dell XPS 13, achieves an accuracy of 19.0 mAP and a speed of 19.4 FPS which is 3 times as fast as MobileNetV2, and when running on a raspberry pi, it achieves a speed of 4.5 FPS which is up to 7 times faster than MobileNetV2. MobileNet-Tiny was modeled to offer a compact, quick, and well-balanced object detection solution to a variety of GPU restricted devices.

Building energy management systems (BEMSs) monitor and control the heating ventilation and air conditioning (HVAC) of buildings in addition to many other building systems and utilities. Wireless sensor networks (WSNs) have become the integral part of BEMS at the initial implementation phase or latter when retro fitting is required to upgrade older buildings. WSN enabled BEMS, however, have several challenges which are managing data, controllers, actuators, intelligence, and power usage of wireless components (which might be battery powered). The wireless sensor nodes have limited processing power and memory for embedding intelligence in the sensor nodes. In this paper, we present a random neural network (RNN)-based smart controller on a Internet of Things (IoT) platform integrated with cloud processing for training the RNN which has been implemented and tested in an environment chamber. The IoT platform is modular and not limited to but has several sensors for measuring temperature, humidity, inlet air coming from the HVAC duct and PIR. The smart RNN controller has three main components: 1) base station; 2) sensor nodes; and 3) the cloud with embedded intelligence on each component for different tasks. This IoT platform is integrated with cloud processing for training the RNN. The RNN-based occupancy estimator is embedded in sensor node which estimates the number of occupants inside the room and sends this information to the base station. The base station is embedded with RNN models to control the HVAC on the basis of setpoints for heating and cooling. The HVAC of the environment chamber consumes 27.12% less energy with smart controller as compared to simple rule-based controllers. The occupancy estimation time is reduced by our proposed hybrid algorithm for occupancy estimation that combines RNN-based occupancy estimator with door sensor node (equipped with PIR and magnetic reed switch). The results show that accuracy of hybrid RNN occupancy estimator is 88%.

Smart homes reduce human intervention in controlling the heating ventilation and air conditioning (HVAC) systems for maintaining a comfortable indoor environment. The embedded intelligence in the sensor nodes is limited due to the limited processing power and memory in the sensor node. Cloud computing has become increasingly popular due to its capability of providing computer utilities as internet services. In this study, a model for the intelligent controller by integrating internet of things (IoT) with cloud computing and web services is proposed. The wireless sensor nodes for monitoring the indoor environment and HVAC inlet air, and wireless base station for controlling the actuators of HVAC have been developed. The sensor nodes and base station communicate through RF transceivers at 915 MHz. Random neural network (RNN) models are used for estimating the number of occupants, and for estimating the predicted-mean-vote-based setpoints for controlling the heating, ventilation, and cooling of the building. Three test cases are studied (Case 1-Data storage and implementation of RNN models on the cloud, Case 2-RNN models implementation on base station, Case 3-Distributed implementation of RNN models on sensor nodes and base stations) for determining the best architecture in terms of power consumption. The results have shown that by embedding the intelligence in the base station and sensor nodes (i.e., Case 3), the power consumption of the intelligent controller was 4.4% less than Case 1 and 19.23% less than Case 2.

Hybrid wired-wireless Network-on-Chip (WiNoC) has emerged as an alternative solution to the poor scalability and performance issues of conventional wireline NoC design for future System-on-Chip (SoC). Existing feasible wireless solution for WiNoCs in the form of millimeter wave (mm-Wave) relies on free space signal radiation which has high power dissipation with high degradation rate in the signal strength per transmission distance. Moreover, over the lossy wireless medium, combining wireless and wireline channels drastically reduces the total reliability of the communication fabric. Surface wave has been proposed as an alternative wireless technology for low power on-chip communication. With the right design considerations, the reliability and performance benefits of the surface wave channel could be extended. In this paper, we propose a surface wave communication fabric for emerging WiNoCs that is able to match the reliability of traditional wireline NoCs. First, we propose a realistic channel model which demonstrates that existing mm-Wave WiNoCs suffers from not only free-space spreading loss (FSSL) but also molecular absorption attenuation (MAA), especially at high frequency band, which reduces the reliability of the system. Consequently, we employ a carefully designed transducer and commercially available thin metal conductor coated with a low cost dielectric material to generate surface wave signals with improved transmission gain. Our experimental results demonstrate that the proposed communication fabric can achieve a 5 dB operational bandwidth of about 60 GHz around the center frequency (60 GHz). By improving the transmission reliability of wireless layer, the proposed communication fabric can improve maximum sustainable load of NoCs by an average of 20:9 and 133:3 percent compared to existing WiNoCs and wireline NoCs, respectively.

Security and privacy of data are one of the prime concerns in today’s Internet of Things (IoT). Conventional security techniques like signature-based detection of malware and regular updates of a signature database are not feasible solutions as they cannot secure such systems effectively, having limited resources. Programming languages permitting immediate memory accesses through pointers often result in applications having memory-related errors, which may lead to unpredictable failures and security vulnerabilities. Furthermore, energy efficient IoT devices running on batteries cannot afford the implementation of cryptography algorithms as such techniques have significant impact on the system power consumption. Therefore, in order to operate IoT in a secure manner, the system must be able to detect and prevent any kind of intrusions before the network (i.e., sensor nodes and base station) is destabilised by the attackers. In this article, we have presented an intrusion detection and prevention mechanism by implementing an intelligent security architecture using random neural networks (RNNs). The application’s source code is also instrumented at compile time in order to detect out-of-bound memory accesses. It is based on creating tags, to be coupled with each memory allocation and then placing additional tag checking instructions for each access made to the memory. To validate the feasibility of the proposed security solution, it is implemented for an existing IoT system and its functionality is practically demonstrated by successfully detecting the presence of any suspicious sensor node within the system operating range and anomalous activity in the base station with an accuracy of 97.23%. Overall, the proposed security solution has presented a minimal performance overhead.

Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore, the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the existing solutions.

Artificial intelligence (AI)/machine learning (ML) based cognitive solutions have widely been applied to deal with downlink inter-cell interference coordination (ICIC) in long-term evolution (LTE) systems. This paper presents a random neural network (RNN) based novel framework to improve ICIC and radio resource management (RRM) in LTE-Uplink system. The RNN based cognitive engine (CE) is embedded within the eNodeB which allocates optimal radio parameters to attached users and also suggests acceptable transmit power to users served by adjacent cells, in order to reduce inter-cell interference (ICI). The proposed CE concurrently achieves long-term learning, fast decision making, and less computational complexity. These three CE design features are essential for the development and practical deployment of any real-time cognitive communication system and most of the existing AI/ML based cognitive solutions in literature lack them. The performance of RNN based optimization framework is compared with artificial neural network (ANN) and state-of-the-art fractional power control (FPC) scheme. In six different test-cases, simulation results have shown an improvement of 53.88%-87.53% in decision making accuracy and a decrease of 44.22% in scheduling delay as compared to ANN. In addition, throughput gain of 16.13% and 18.62% has been achieved as compared to ANN and FPC schemes respectively.

In this paper, we critically analyze the performance of an intelligent Long-Term Evolution-Uplink (LTE-UL) system having a cognitive engine (CE) embedded in e-NodeB. Performance characterization, optimal radio parameters prediction, and inter-cell-interference coordination (ICIC) are studied. The embedded CE allocates the optimal radio parameters to serving users and suggests the acceptable transmit power to users served by adjacent cells for ICIC. The desired cognition has been achieved with a novel random neural network (RNN) based CE architecture. To achieve the best learning performance, we critically analyzed three learning algorithms, gradient descent (GD), adaptive inertia weight particle swarm optimization (AIW-PSO) and differential evolution (DE). The analysis showed that AIW-PSO was 10.57% better than GD and 8.012% better than DE in terms of learning accuracy (based on MSE), but with considerable compromise on computational time as compared to GD. Moreover, in terms of convergence time (to achieve the MSE less than 1.04E-03), AIW-PSO took 60% less iterations than GD and 50% less than DE.

Security is becoming the primary concern in today's embedded systems. Network-on-Chip (NoC) based communication architectures have emerged as an alternative to shared bus mechanism in Multiprocessor System-on-Chip (MPSoC) devices, and the increasing number and functionality of processing cores has made such systems vulnerable to security attacks. In this paper an id and address verification (IAV) security module is presented, which is embedded in each router at the communication level. IAV verifies the identity and address range to be accessed by incoming and outgoing data packets in a NoC-based many-core shared memory architecture. Our IAV architecture is implemented on a FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyse the performance overhead for different network configurations. The proposed IAV module has reduced area and power consumption overhead when compared with similar existing solutions.

Here we present our multi-core architectures for object detection. We move away from the traditional architecture of Multi-Processors (MPs) by using cacheable accesses to main memory to create atomic cores and utilising local memory for all program data. Main memory is partitioned through software into dedicated data regions to allow atomic accesses by cores, without the need for synchronisation primitives. In doing this, we demonstrate how multi-threading techniques such as Interleaved Task Reordering (ITR) can be utilised to balance the processing loads on available cores. We implement and test up to 7 soft-cores with the Viola Jones face detection algorithm and achieve a performance increase of up to 9.14x with a 100% detection rate: surpassing the theoretical performance increase of multi-core processors for all designs and test images. Furthermore, we surpass the performance increases of multi-core implementations from the literature, thus proving our custom designs to be a more viable solution for multi-core object detection applications. Finally, resource and power consumption estimates indicate our designs to be suitable for embedded systems deployment.

Network-on-Chip (NoC) is considered to be the solution for the communication demands of future multi-core systems. Efficient buffer management is not only instrumental in the overall performance of the on-chip networks but also greatly affects the network energy consumption. To increase the quality of service in NoCs and to efficiently utilize the available hardware resources, a novel adaptive router is proposed. Exploiting the notion of adaptivity, the proposed router adapts itself in terms of buffer size allocation for each input channel according to their corresponding traffic rate at run time, thus utilizing the maximum available buffer resources and improving quality of service in NoCs. For this reason, a flexible ring buffer architecture is proposed, which can be used by all input channels in the router. Implementation results show up to 50% in reducing power consumption and up to five times reduction in memory utilization in router architectures when compared with a traditional router. Moreover, our extensive simulation study shows that the proposed router architecture enhances the network performance by increasing the acceptance traffic rate and decreasing the average message latency.

Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by proposing an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a 2D strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve 2D defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances. We also discuss a simple strategy for dealing with online scenarios, called ldquoleast-interference fitrdquo (LIF); we give a number of analytic results that allow a comparison of LIF with the best offline solution, and demonstrate that it works well on benchmark instances of moderate size.

A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and co-simulated in a C-based WiMAX system. Area and power consumption of main blocks in WiMAX are analysed.

Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, the authors propose a heterogeneous power model to estimate the power utilized by complete processor based reconfigurable system-on-chip (SoC) platform. The proposed model estimates the power consumed by the SoC platform using instruction-based model as well as transaction-based model. In addition the authors estimate the power consumed by various bus arbitration policies used in the on-chip communication

We describe algorithmic results on two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a method that allows correct maintenance of free and occupied space of a set of n rectangular modules in time O(n log n); previous approaches needed a time of O(n2) for correct results and O(n) for heuristic results. We also show a matching lower bound of Omega (n log n), so our approach is optimal. We also show that finding an optimal feasible communication-conscious placement (which minimizes the total weighted Manhattan distance between the new module and existing demand points) can be computed with Theta(n log n). Both resulting algorithms are practically easy to implement and show convincing experimental behavior

We present a new concept as well as the implementation of an FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). The main advantages of this platform are: first, the possibility for each module to access its peripheries independent from its location through a programmable crossbar, and distributed SRAMs among slices. This allows an unrestricted relocation of modules on the device. Second, the intermodule structure allows an unlimited communication among running modules.

A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at run-time is presented. Based on the network on chip (NoC) infrastructure, we developed a dynamic communication infrastructure as well as routing methodologies capable to handle routing in a NoC with obstacles created by dynamically placed components. We prove the unrestricted reachability of components and pins, the deadlock-freeness and we finally show the feasibility of our approach by means on real life example applications.

The focus in This work is put onto extensions to typical FPGA hardware architectures in order to support some operating system functions. In particular, we examine the problem of preemptive multitasking and hardware defragmentation on a reconfigurable system based on FPGAs with a dynamically changing set of hardware tasks that can be replaced considering internal states.

Summary form only given. By increasing the amount of resources on reconfigurable platforms with the ability of partial reconfigurability, the issues of the management of these resources and their sharing among different tasks will become more of a concern. Online placement is one of these management issues that are investigated. We present a new approach for online placement of modules on reconfigurable devices, by managing the occupied space rather the free space on the device. Also an optimization of communication between running modules themselves and outside of the chip is proposed. The experimental results show a considerable decrease in communication and routing costs.

Summary form only given. Xilinx Virtex FPGAs have the possibility of dynamical partial run-time reconfiguration. If a system uses this feature with many different configuration bitstreams for substitution of parts in reconfiguration memory, the amount of necessary memory increases. The sum of memory amount which has to be provided for the configuration data is not negligible. This fact suggests the investigation of compressing data before they are stored in memory modules of a system. The compressed bitstream data has to be decompressed before transferring it to the FPGA. We show an approach of compressing configuration data at design time and decompressing them with a hardware module implemented on FPGA while run-time.

Partial reconfiguration allows for mapping and executing several tasks on an FPGA during run time. One of the challenging problems in multitasking systems is high amount of communication costs. In this paper, we present two clustering methodologies that temporally cluster real-time tasks for a partially reconfigurable hardware and reduce communication overhead. The first algorithm aims at efficient use of resources by clustering close run-time tasks, and the second one makes the clustering with respect to a trade off between inter-task communication and resource utilization efficiency. The results show significant reduction communication costs.

We present a new approach for reconfigurable massively parallel computers. The approach uses FPGA as reconfigurable device to build parallel computers which can adapt their physical topology to match the virtual topology used to model the parallel computation paradigm of a given application. We use a case study in which a virtual ring topology is first simulated on a tree topology and then directly implemented in an FPGA configuration. Preliminary results show that we can increase the performance of the parallel computers which make use of message passing interface by a factor of up to 20% if a reconfigurable topology approach is used.