A tool capable of extracting structure from a logical design was implemented, and the effect of structure on placement was studied. Results demonstrate that structure can reduce the problem complexity of a traditional placement tool when the structured portion of a design is clustered and/or seeded, thereby giving the traditional placement tool fewer cells to place. The reduction in complexity depends on the amount of structure in the logic design. In addition, placing structure may lead to better circuit performance by reducing bit-slice length, the distance a signal must travel as it traverses the combinational logic of a bit slice. The number of layer changes for clock lines and control signals can be reduced by aligning the modules connected by these signals. By strategically placing the drivers of key control signals, the lengths of their longest stubs can be reduced, thereby improving clock speed. Experiments demonstrate that structurally directed placement can reduce bit-slice length by up to 96% and clock stub length by up to 67% with negligible impact on traditional routing metrics, such as track count and wirelength.>

An algorithm for extracting structure from a logical design is presented. It uses a data structure which explicitly represents not only connectivity, but also a variety of information that is generated during logical design. The algorithm is applied to a small design and used to determine the layout. Work is in progress to increase the number of functional cluster types that can be extracted and to develop additional heuristics for automatically mapping the structure onto the chip.>