This paper investigates and resolves in-channel/quadrature channel (I/Q) imbalances in quadrature band pass delta sigma modulators. These mismatches result in image interference and noise being aliased into the desired signal band, thus degrading the dynamic range of the modulators. A novel dynamic element match shaping scheme is proposed to cancel the aliasing of image interference, noise, and self-image. The simulation results for the proposed scheme show that the SNDR is only degraded by 1.6 dB from the ideal case (without I/Q mismatch). Meanwhile, using the I/Q channel multiplexing technique, operational amplifiers, quantizers, and digital-analog converters can be shared between I/Q channels. As a result, silicon area can be reduced with the same power consumption.

This paper presents a current-mode analog-to-quaternary (A/Q) converter using a 0.35/spl mu/m CMOS process. Redundant signed digit (RSD) technique is used to improve the resolution to 6 digits, which is equivalent to 12 binary bits. Simulations results show that the converter dissipates 382mW at 2.5V supply and 20MHz sampling rate. The converter achieves SNDR of 66.8dB, SFDR of 76.33dB and THD of -75.73dB. The effective number of bit is equal to 5.4 digits or 10.8 bits (binary).

This paper introduces a new algorithm of extracting MFCC for speech recognition. The new algorithm reduces the computation power by 53% compared to the conventional algorithm. Simulation results indicate the new algorithm has a recognition accuracy of 92.93%. There is only a 1.5% reduction in recognition accuracy compared to the conventional MFCC extraction algorithm, which has an accuracy of 94.43%. However, the number of logic gates required to implement the new algorithm is about half of the MFCC algorithm, which makes the new algorithm very efficient for hardware implementation.

This paper presents a fully differential OTA with a supply of 0.5V in a 0.18/spl mu/m CMOS process that has threshold voltages of 0.5V under zero body-source biasing. Unlike a recent two-stage 0.5V OTA architecture, this OTA employs two common mode feedback loops for obtaining a stable operating condition and thus a robust performance against process variations. Body terminals of the input differential pairs of each stage are used for common mode control. Simulation results indicate that this OTA has an open-loop gain of greater than 61dB, a unity gain-bandwidth of 41MHz with a load of 10pF. The power consumption is 510/spl mu/W.

In this paper a 173-bit type II ONB ECC processor for inductive RFID applications is described. Compared with the standard mathematical expressions provided by A. J. Menezes (1993), the formula expressions adopted in the design can save one field multiplication operation in the curve addition. Therefore, the encryption/decryption time is reduced by approximately 7%. Furthermore, the system level architecture of the ECC processor is specially structured and optimized, which makes it faster and less power consuming, and is more favorable for inductive RFID systems.

In this paper, a CMOS low noise amplifier (LNA) employing the switched-capacitors is proposed to perform multi-band tuning for an MB-OFDM ultra-wideband (UWB) hopping system. By using the fully differential topology, the switching noise generated during each frequency transition interval is greatly suppressed. The proposed UWB LNA is implemented in a standard 0.18-/spl mu/m CMOS process. The simulation results show that it is capable of performing the fast switching with a settling time of less than 3 ns. Furthermore, the switching noise voltage at the output is rapidly reduced to less than 1 /spl mu/V within 5 ns. The designed circuit is optimized in each center frequency, achieving the maximum power gain of 16.2 dB and the minimum noise figure of 2.63 dB.

In this paper, we propose a power-efficient bitstream parsing for H.264/AVC baseline profile decoding. It parses the input bitstream syntaxes and controls the following decoding steps. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, clock gating etc., have been adopted in our design. The VLSI implementation results show that under UMC130nm technology with 1.08V supply voltage, the core power consumption is only 1.98mW@20MHz for real-time decoding. Total hardware costs are 49k gates and 1.2 /spl times/ 1.2mm/sup 2/ chip area. The power-efficient and real-time features make our design ideal for low-power video transmission applications such as mobile phone and PDA where video quality is often traded off for energy.

This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

This work examines the inherent self-checking property of a latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic (DCVSL). Consequently, a highly efficient self-checking (SC) dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve self-checking. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

This paper investigates the inherent totally self-checking (TSC) property of one type of dynamic asynchronous datapath based on Differential Cascode Voltage Logic (DCVSL). As a result, a totally self-checking dynamic asynchronous datapath architecture is proposed. It is simpler than other similar approaches and represents a new approach to fault tolerant design.

In this paper, we present a new configuration of an asynchronous micropipeline, called locally distributed asynchronous (LDA) micropipeline, using a new control circuit. The control circuit generates local control signals according to the 4-phase signaling protocol. The control circuit is used to control the dynamic logic in the datapath. Comparisons based on simulations with other earlier published asynchronous micropipelines are also presented.

No abstract available.

This paper presents a new type of adiabatic logic. The new adiabatic circuit is named Adiabatic Quasi-Static CMOS (AqsCMOS), because the output is quasi-static. The AqsCMOS is totally compatible with conventional CMOS. Designers can easily reduce the power budget by replacing all or part of an existing CMOS circuit with AqsCMOS circuits to achieve for low power operation. We have designed and fabricated an 8/spl times/8 AqsCMOS multiplier to demonstrate the operation of AqsCMOS. The simulation results have indicated that the new AqsCMOS 8/spl times/8 multiplier consume 90% less power compare with a conventional 8/spl times/8 multiplier of similar architecture.

This paper presents a design of a 16-bit pipeline ALU. The ALU is implemented by using a novel asynchronous pipeline architecture. The architecture has simple handshake cells and these cells are embedded in the pipeline stage as normal logic cells. As a result, the speed of the ALU can be very fast.

This paper describes an asynchronous one-dimensional order-8 integer cosine transform chip, which can calculate either the forward or inverse transforms. The chip's performance is maximized with a fast computation algorithm and the self-timed circuit technique. The basic self-timed block is a microcoded programmable processor. Eight of these processors are used and achieve a data rate of up to 50 MHz in 0.7-/spl mu/m CMOS technology. If the delay in the handshake circuit can be minimized, the design suggests that asynchronous techniques are a feasible alternative to synchronous designs.

This paper describes a LSI implementation of 1-D order-8 integer cosine transform (ICT) which can calculate either forward or reverse transformation. It is a standard-cell based design using 0.7 /spl mu/m CMOS SLP DLM process. The chip's performance is maximized with the fast computation algorithm and self-timed circuit technique. It consists of eight parallel self-timed pipelines. Each self-timed block is designed based on 2-phase handshaking protocol and variable delay concept. The die size is 5.7/spl times/4.1 mm with about 76 K transistors. This chip supports 16-bit I/O data and its data rate is up to 60 MHz.

High observability testing environment allows internal circuit nodes to be used as test points. However, such flexibility requires the development of new ATPG algorithm. Previous reported algorithm does not guarantee full fault-coverage and assumes all internal circuit nodes are test points. The new algorithm described in this paper will generate a full fault-coverage test set for a fanout free combinational circuit. The main characteristic of the algorithm is that it generates test vectors as well as probe points. As a result, the probe points are different for each test vector, and the number of probe points is the minimum for test set generated. Results obtained show that an average of 30% test vector reduction is achieved compared with the conventional test method which uses only output pins as test points.

In today's sub-micron CMOS integrated circuit technology, high speed output switching signals interacting with external inductance and capacitance produce noise which contaminates output signals and power buses. A Feedback Control Slew Rate Output Driver (FCSROD) which reduces the noise spike down to approximately 64% of a conventional output buffer without incurring the penalty of the propagation delay and even the rise/fall time is described. This effective power noise suppression is achieved by using distributed and weighted switching driver segments in conjunction with feedback control to control the output driver's slew rate. Dynamic short circuit current which is generated while both pFET and nFET are conducting is also minimized to reduce di/dt noise. FCSROD was compared with a conventional and the controlled slew rate output buffer, showing 64% noise reduction comparing to the conventional driver, and 22% improvement in both propagation delay and rise/fall time comparing with the controlled slew rate output driver.

Describes a hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnect switches to overcome the limitations of traditional verifications for ASIC designs. Both hardwired buses and programmable buses, via switches, contribute to the interconnection between the FPGAs. With a microprocessor and two EPROMs, the board is designed so that the microprocessor itself can be a part of emulation, in addition to downloading configuration data and testing. Finally presented is the software tool tailored to this board. It automatically partitions the design among multiple FPGAs, programs the switches and facilitates the design and verification process.>