Zhirong Chen, Kaiyan Chang, Zhuolin Li, Cangyuan Li, Xinyang He, Chujie Chen, Mengdi Wang, Haobo Xu, Yinhe Han, Huawei Li, Ying Wang. Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers). 2026.

Assertion-based verification (ABV) is a key approach to checking whether a logic design complies with its architectural specifications. Existing assertion generation methods based on design specifications typically produce only top-level assertions, overlooking verification needs on the implementation details in the modules at the micro-architectural level, where design errors occur more frequently. To address this limitation, we present AssertMiner, a module-level assertion generation framework that leverages static information generated from abstract syntax tree (AST) to assist LLMs in mining assertions. Specifically, it performs AST-based structural extraction to derive the module call graph, I/O table, and dataflow graph, guiding the LLM to generate module-level specifications and mine module-level assertions. Our evaluation demonstrates that AssertMiner outperforms existing methods such as AssertLLM and Spec2Assertion in generating high-quality assertions for modules. When integrated with these methods, AssertMiner can enhance the structural coverage and significantly improve the error detection capability, enabling a more comprehensive and efficient verification process.

Large language models (LLMs) hold promise for automating integrated circuit (IC) engineering using register transfer level (RTL) hardware description languages (HDLs) like Verilog. However, challenges remain in ensuring the quality of Verilog generation. Complex designs often fail in a single generation due to the lack of targeted decoupling strategies, and evaluating the correctness of decoupled sub-tasks remains difficult. While the chain-of-thought (CoT) method is commonly used to improve LLM reasoning, it has been largely ineffective in automating IC design workflows, requiring manual intervention. The key issue is controlling CoT reasoning direction and step granularity, which do not align with expert RTL design knowledge. This paper introduces VeriBToT, a specialized LLM reasoning paradigm for automated Verilog generation. By integrating Top-down and design-for-verification (DFV) approaches, VeriBToT achieves self-decoupling and self-verification of intermediate steps, constructing a Backtrack Tree of Thought with formal operators. Compared to traditional CoT paradigms, our approach enhances Verilog generation while optimizing token costs through flexible modularity, hierarchy, and reusability.

In-situ training architectures based on resistive random-access memory (ReRAM) have attracted significant attention due to their exceptional energy efficiency. However, the inherent stochasticity of ReRAM devices severely degrades training convergence. To address this challenge, this work proposes a ReRAM-based in-situ training accelerator (ReBIT) architecture. The ReBIT integrates ReRAM with static random-access memory (SRAM) devices, leveraging the deterministic characteristics of SRAM-based computations to suppress the inherent stochasticity of ReRAM devices. Experimental results demonstrate that the ReBIT architecture achieves convergence performance comparable to full-precision software training.

Point cloud diffusion models, as an emerging 3D generation method, hold broad prospects in 3D modeling, AR/VR, and so on. However, their reliance on costly full-precision neural network computations during extended denoising process limits their practical application. To address this challenge, we propose RAPID, an accelerator co-designed with a space-aware quantization method. First, RAPID uses K-means to partition points into groups and computes scaling factors in each, mitigating accuracy issues caused by uneven distribution. Second, it employs a mixed-precision quantization scheme that uses low precision for internal point groups and high precision for detail-rich edge groups, ensuring generation quality while minimizing bit-width. Third, it reuses computation results for groups with little change between timesteps, reducing redundant calculations. Moreover, RAPID’s hardware features a mixed-precision PE array for efficient computations at various bit-widths, and a filter for dynamic bit-width allocation and result reuse. Evaluations show that, compared to the NVIDIA RTX A5000 GPU and state-of-the-art accelerators, RAPID achieves average speedups of 9.22×, 4.66×, 3.69×, and 3.01×, and energy savings of 61.74×, 4.30×, 3.94×, and 2.76×, with negligible accuracy loss.

LLMs can generate SystemVerilog assertions (SVAs) from natural language specs, but single-pass outputs often lack functional coverage due to limited IC design understanding. We propose CoverAssert, an iterative framework that clusters semantic and AST-based structural features of assertions, maps them to specifications, and uses functional coverage feedback to guide LLMs in prioritizing uncovered points. Experiments on four open-source designs show that integrating CoverAssert with AssertLLM and Spec2Assertion improves average improvements of 9.57% in branch coverage, 9.64% in statement coverage, and 15.69% in toggle coverage.

Transformer-based models dominate modern AI workloads but exacerbate memory bottlenecks due to their quadratic attention complexity and ever-growing model sizes. Existing accelerators, such as Groq and Cerebras, mitigate off-chip traffic with large on-chip caches, while algorithmic innovations such as FlashAttention fuse operators to avoid materializing large attention matrices. However, as off-chip traffic decreases, our measurements show that on-chip SRAM accesses account for over 60% of energy in long-sequence workloads, making cache access the new bottleneck. We propose 3D-Flow, a hybrid-bonded, 3D-stacked spatial accelerator that enables register-to-register communication across vertically partitioned PE tiers. Unlike 2D multi-array architectures limited by NoC-based router-to-router transfers, 3D-Flow leverages sub-10 μm vertical TSVs to sustain cycle-level operator pipelining with minimal overhead. On top of this architecture, we design 3D-FlashAttention, a fine-grained scheduling method that balances latency across tiers, forming a bubble-free vertical dataflow without on-chip SRAM round-trips. Evaluations on Transformer workloads (OPT and QWEN models) show that our 3D spatial accelerator reduces 46–93% energy consumption and achieves 1.4×–7.6× speedups compared to state-of-the-art 2D and 3D designs.

The decomposition-based chiplet design paradigm, which breaks monolithic system-on-chips (SoCs) into smaller chiplets, has proven effective in reducing costs and accelerating development. The vast design space of multi-chiplet systems necessitates automated techniques to maximize their benefits while minimizing overheads. However, current chiplet decomposition flows lack support for exploring reusable chiplets, missing opportunities to efficiently amortize non-recurring engineering costs. To fully unleash the economic potential of chiplets, we propose CHIPLETIZER 2.0, a cost-driven framework that guides SoC decomposition and enables chiplet reuse across a line of products. This early-stage chiplet planning framework determines critical system parameters involving the partition, floorplan, and D2D interface, based on user-specified optimization goals. Experimental results demonstrate that, compared with the existing chiplet decomposition techniques, our proposed framework achieves significant cost improvements on realistic product lines with acceptable overheads.

Boolean equivalence allows Boolean networks with identical functionality to exhibit diverse graph structures. This gives more room for exploration in logic optimization, while also posing a challenge for tasks involving consistency between Boolean networks. To tackle this challenge, we introduceBoolSkeleton, a novel Boolean network skeletonization method that improves the consistency and reliability of design-specific evaluations.BoolSkeletoncomprises two key steps: preprocessing and reduction. In preprocessing, the Boolean network is transformed into a defined Boolean dependency graph, where nodes are assigned the functionality-related status. Next, the homogeneous and heterogeneous patterns are defined for the node-level pattern reduction step. Heterogeneous patterns are preserved to maintain critical functionality-related dependencies, while homogeneous patterns can be reduced. ParameterKof the pattern further constrains the fanin size of these patterns, enabling fine-tuned control over the granularity of graph reduction. To validateBoolSkeleton’s effectiveness, we conducted four analysis/downstream tasks around the Boolean network: compression analysis, classification, critical path analysis, and timing prediction, demonstrating its robustness across diverse scenarios. Furthermore, it improves above 55% in the average accuracy compared to the original Boolean network for the timing prediction task. These experiments underscore the potential ofBoolSkeletonto enhance design consistency in logic synthesis.

Gate-level fault simulation is a critical step in design for test and functional safety verification of the chip design process, essential to ensuring circuit reliability. As chip complexity grows for mission-critical applications such as autonomous vehicles, medical devices, and military systems, the efficiency of fault simulation increasingly becomes a bottleneck in the chip’s time-to-market. However, existing methods often suffer from computational redundancy, inefficiencies in memory access, or failure to optimize performance for specific CPU hardware platforms. This paper proposes DomSim, a hardware-aware hybrid fault simulation method that combines compiled simulation and event-driven simulation with an optimized computation-to-memory-access ratio. By utilizing circuit information and hierarchical structure provided by dominator trees, DomSim achieves high-quality circuit partitioning, optimizing hardware resource utilization and memory access locality. Furthermore, a parameter adjustment strategy tailored to hardware capabilities and circuit characteristics enables adaptive optimization. Extensive experiments show that DomSim surpasses a commercial tool by 10.29× on average. Further experiments demonstrate that DomSim exhibits good adaptability across different hardware platforms and circuits, highlighting the superiority of our method.

Mixed-precision neural network (MPNN) that utilizes just enough data width for the neural network processing is an effective approach to meet the stringent resources constraints including memory and computing of MCUs. Nevertheless, there is still a lack of sub-byte and mixed-precision SIMD operations in MCU-class ISA and the limited computing capability of MCUs remains underutilized, which further aggravates the computing bound encountered in neural network processing. As a result, the benefits of MPNNs cannot be fully unleashed. In this work, we propose to pack multiple low-bitwidth arithmetic operations within a single instruction multiple data (SIMD) instructions in typical MCUs, and then develop an efficient convolution operator by exploring both the data parallelism and computing parallelism in convolution along with the proposed SIMD packing. Finally, we further leverage Neural Architecture Search (NAS) to build a HW/SW co-designed MPNN design framework, namely MCU-MixQ. This framework can optimize both the MPNN quantization and MPNN implementation efficiency, striking an optimized balance between neural network performance and accuracy. According to our experiment results, MCU-MixQ achieves 2.1× and 1.4× speedup over CMix-NN and MCUNet respectively under the same resource constraints. MCU-MixQ is also open sourced on GitHub. 1

This is a corrigendum for the article “A data-centric chip design agent framework for Verilog code generation” published in ACM Trans. Des. Autom. Electron Syst. 30, 6, Article 93 (October 2025), 27 pages.

The globalization of the integrated circuit supply chain has introduced untrustworthy entities at various stages, arousing increasing attention to hardware security research from both academia and industry. Some tasks in hardware security research require matching two hardware designs. For example, in gate-level netlist reverse engineering, after recovering module boundaries and hierarchical structure from a netlist, one must match each candidate module against known library components to validate its functionality. Likewise, in Intellectual Property (IP) piracy detection, a suspected infringing IP can be matched against its original counterpart to determine whether infringement has occurred. We design and implement a hardware similarity evaluation framework called Twins. We develop two versions of the framework, called Twins-v1 with the basic Graph Neural Network (GNN) model and Twins-v2 with the node-independent GNN model, respectively. Twins employs a more effective training approach that substantially reduces training time and improves evaluation metrics compared to the current state-of-the-art models. Furthermore, to the best of our knowledge, Twins-v2 represents the first work to use independent graph convolutional network layers based on different node types in the context of hardware security research. The novel netlist graph extraction method has also been experimentally demonstrated to outperform the previously employed data flow graph approach in hardware similarity evaluation tasks. After conducting experimental evaluations on a dataset comprising 305 circuits, both Twins-v1 and Twins-v2 significantly surpass existing methods in terms of prediction accuracy and efficiency.

With the slowdown of Moore’s Law, conventional monolithic chip architectures face challenges such as excessive die sizes and prohibitive manufacturing costs. Consequently, chiplets have emerged as a pivotal technology in the post-Moore era, attracting significant attention from both academia and industry. Multi-chiplet systems offer compelling advantages over monolithic ones, including enhanced integration density, reduced cost, and shortened time-to-market. However, realizing these benefits necessitates design flows capable of optimizing parameters across logical, physical, and circuit layers, which introduces substantial design complexity. Numerous design automation technologies have been proposed to address these challenges. This article provides a comprehensive overview of related advancements, categorizing chiplet design methodologies into two primary types: (i) top-down flows disintegrating existing hardware designs into chiplets and subsequently reintegrating them into multi-chiplet systems, and (ii) bottom-up flows combining existing chiplets into multi-chiplet systems based on user applications. This article begins by introducing foundational concepts, technical characteristics, and evaluation models relevant to multi-chiplet systems. We then systematically summarize the problem formulations, design spaces, and optimization techniques associated with top-down and bottom-up design flows. Finally, we discuss key challenges and potential future research directions in chiplet design automation, aimed at further harnessing the potential of chiplet-based integration.

With the advancement of integrated circuit (IC) technology, the sensitivity to delay defects has significantly increased, rendering Transition Fault (TF) testing crucial for ensuring chip quality. However, as the complexity of IC designs increases, existing pattern parallelization methods are not flexible in detecting multi-cycle faults. In addition, the growing demand for simulation memory exacerbates inefficient memory access, becoming another critical bottleneck. This paper introduces ETPG (Efficient Transition fault simulation via dual-strategy Pattern parallelism and Gate restructuring), a novel TF simulation algorithm based on multi-dimensional optimization. The key innovations include an adaptive dual-strategy pattern parallel strategy that dynamically optimizes parallelization based on test pattern characteristics, enhancing efficiency and multi-cycle fault detection capability; a dual-dimension gate restructuring method that optimizes memory storage order, significantly reducing memory access time, particularly beneficial for large-scale circuits; and a collaborative mechanism between pattern processing and circuit storage optimization, achieving comprehensive performance improvements at both algorithmic and memory access levels. Experimental results demonstrate ETPG's significant performance improvements across various circuit scales, particularly for larger circuits. Compared to the synopsys commercial tool testmax (TMAX), ETPG achieves average speedups of 2.846× for circuits below 100k gates and 4.428× for circuits above 100k gates.

Large language models (LLMs) are widely used for natural language understanding and text generation. An LLM model relies on a time-consuming step called LLM decoding to generate output tokens. Several prior works focus on improving the performance of LLM decoding using parallelism techniques, such as batching and speculative decoding. State-of-the-art LLM decoding has both compute-bound and memory-bound kernels. Some prior works statically identify and map these different kernels to a heterogeneous architecture consisting of both processing-in-memory (PIM) units and computation-centric accelerators (e.g., GPUs). We observe that characteristics of LLM decoding kernels (e.g., whether or not a kernel is memory-bound) can change dynamically due to parameter changes to meet user and/or system demands, making (1) static kernel mapping to PIM units and computation-centric accelerators suboptimal, and (2) one-size-fits-all approach of designing PIM units inefficient due to a large degree of heterogeneity even in memory-bound kernels.

Assertion-based verification (ABV) serves as a crucial technique for ensuring that register-transfer level (RTL) designs adhere to their specifications. While Large Language Model (LLM) aided assertion generation approaches have recently achieved remarkable progress, existing methods are still unable to effectively identify the relationship from the behavioral interactions of signals across different layers, which leads to the insufficiency of the generated assertions. To address this issue, we propose AssertGen, an assertion generation framework that automatically generates SystemVerilog assertions (SVA). AssertGen first extracts verification objectives from specifications using a chain-of-thought (CoT) reasoning strategy, then bridges corresponding signals between these objectives and the RTL code to construct a cross-layer signal chain, and finally generates SVAs based on the LLM. Experimental results demonstrate that AssertGen outperforms the existing state-of-the-art methods across several key metrics, such as pass rate of formal property verification (FPV), cone of influence (COI), proof core and mutation testing coverage.

In automatic test pattern generation (ATPG), SAT-based methods are typically used to complement structural approaches, especially for addressing hard-to-detect faults. However, as the size and complexity of circuits grow, SAT-based ATPG faces challenges like pattern inflation and excessive runtime, limiting its overall performance. The key problem lies in the fact that current mainstream SAT solvers perform complete assignments for all primary inputs of the fault’s transitive fanin cone without considering the detection of other faults, making test compaction extremely difficult and time consuming. In this paper, a novel SAT solver PA-MiniSat is proposed, which is capable of generating partial assignments for solving variables and significantly reduces the number of specified bits in test cubes. As an extension of MiniSat, it employs a full-literal watching technique and a circuit-adapted heuristic branching strategy, achieving overall improved performance in ATPG. Based on PA-MiniSat, a hybrid ATPG framework PastATPG is proposed for better test compaction, which tightly integrates structural algorithms with the SAT solver into the unified test compaction flow. Experimental results demonstrate that our method outperforms other SAT solvers in pattern compaction and, in some cases, even surpasses commercial ATPG tools in terms of speed. The code is available at https://github.com/sklp-eda-lab/PastATPG.

Deep learning has significantly advanced Electronic Design Automation (EDA), with circuit representation learning emerging as a key area for modeling the relationship between a circuit’s structure and functionality. Existing methods primarily use either Large Language Models (LLMs) for Register Transfer Level (RTL) code analysis or Graph Neural Networks (GNNs) for netlist modeling. While LLMs excel at high-level functional understanding, they struggle with detailed netlist behavior. GNNs, however, face challenges when scaling to larger sequential circuits due to long-range information dependencies and insufficient functional supervision, leading to decreased accuracy and limited generalization. To address these challenges, we propose MOSS, a multimodal framework that integrates GNNs with LLMs for sequential circuit modeling. By enhancing D-type Flip-Flop (DFF) node features with embeddings from fine-tuned LLMs on RTL code, we focus the GNN on critical anchor points, reducing reliance on long-range dependencies. The LLM also provides global circuit embeddings, offering efficient supervision for functionality-related tasks. Additionally, MOSS introduces an adaptive aggregation method and a two-phase propagation mechanism in the GNN to better model signal propagation and sequential feedback within the circuit. Experimental results demonstrate that MOSS significantly improves the accuracy of functionality and performance predictions for sequential circuits compared to existing methods, particularly in larger circuits where previous models struggle. Specifically, MOSS achieves a $\mathbf{9 5. 2 \%}$ accuracy in arrival time prediction.

As functional safety of electronic chips gains importance in autonomous vehicles and aerospace, standards like ISO 26262 mandate high diagnostic coverage, requiring extensive gate-level fault simulations. However, for large-scale industrial sequential circuits, these simulations are time-consuming, creating a significant bottleneck in chip development. Prior approaches have focused on reducing computational complexity and optimizing CPU hardware usage by minimizing redundant computations during fault propagation and leveraging bit-level parallel processing capabilities. Techniques like parallel-pattern and event-driven simulations have improved performance in combinational circuits but face limitations in sequential circuits due to timing dependencies within loops. The challenge lies in parallelizing simulations across different cycles without violating these dependencies, which is exacerbated by the complex feedback structures in SCCs. In this work, we propose a novel parallel-pattern fault simulation framework that combines loop fusion with efficient event traversal to accelerate sequential circuit simulations. By compiling simple loops into larger nodes, we reduce the number of feedback events without introducing excessive redundancy. For larger SCCs, we develop specialized algorithms for selecting loop entrance nodes based on indegree analysis and implement the lazy propagation strategy for internal nodes. This approach minimizes simulation events caused by inaccurate predictions and reduces overhead associated with false event propagation. We integrate these techniques into our simulation framework, EPICS, which strategically mixes compiled and event-driven simulations to optimize performance. Experimental results demonstrate that EPICS achieves a $5.94 \times$ speedup over state-of-the-art commercial tool while maintaining the same fault coverage.

Fault simulation targeting functional patterns emerges as an essential mechanism within functional safety, crucial for validating the effectiveness of safety mechanisms. The acceleration of fault simulation for functional patterns is imperative for boosting the efficiency and adaptability of functional safety verification, presenting a significant yet unresolved challenge. In the paper, we propose an efficient fault simulator for functional patterns, utilizing three techniques including fault filtering, fault grouping, and CPU-based parallelism. The integration of these three techniques, tailored to the characteristics of functional patterns, reduces the runtime of fault simulation from different perspectives. The experimental results show that on a 48-core system, an average 79x speedup can be achieved by our parallel fault simulator against a commercial tool.

As intelligent computing devices increasingly integrate into human life, ensuring the functional safety of the corresponding electronic chips becomes more critical. A key metric for functional safety is achieving a sufficient fault coverage. To meet this requirement, extensive time-consuming fault simulation of the RTL code is necessary during the chip design phase. The main overhead in RTL fault simulation comes from simulating behavioral nodes (always blocks). Due to the limited fault propagation capacity, fault simulation results often match the good simulation results for many behavioral nodes. A key strategy for accelerating RTL fault simulation is the identification and elimination of redundant simulations. Existing methods detect redundant executions by examining whether the fault inputs to each RTL node are consistent with the good inputs. However, we observe that this input comparison mechanism overlooks a significant amount of implicit redundant execution: although the fault inputs differ from the good inputs, the node's execution results remain unchanged. Our experiments reveal that this overlooked redundant execution constitutes nearly half of the total execution overhead of behavioral nodes, becoming a significant bottleneck in current RTL fault simulation. The underlying reason for this overlooked redundancy is that, in these cases, the true execution paths within the behavioral nodes are not affected by the changes in input values. In this work, we propose a behavior-level redundancy detection algorithm that focuses on the true execution paths. Building on the elimination of redundant executions, we further developed an efficient RTL fault simulation framework, Eraser. Experimental results show that compared to commercial tools, under the same fault coverage, our framework achieves a 3.9 × improvement in simulation performance on average.

Neural Vector Search (NVS) has exhibited superior search quality over traditional key-based strategies for information retrieval tasks. An effective NVS architecture requires high recall, low latency, and high throughput to enhance user experience and cost-efficiency. However, implementing NVS on existing neural network accelerators and vector search accelerators is sub-optimal due to the separation between the embedding stage and vector search stage at both algorithm and architecture levels. Fortunately, we unveil that Product Quantization (PQ) opens up an opportunity to break separation. However, existing PQ algorithms and accelerators still focus on either the embedding stage or the vector search stage, rather than both simultaneously. Simply combining existing solutions still follows the beaten track of separation and suffers from insufficient parallelization, frequent data access conflicts, and the absence of scheduling, thus failing to reach optimal recall, latency, and throughput. To this end, we propose a unified and efficient NVS accelerator dubbed NeuVSA based on algorithm and architecture co-design philosophy. Specifically, on the algorithm level, we propose a learned PQ-based unified NVS algorithm that consolidates two separate stages into the same computing and memory access paradigm. It integrates an end-to-end joint training strategy to learn the optimal codebook and index for enhanced recall and reduced PQ complexity, thus achieving smoother acceleration. On the architecture level, we customize a homogeneous NVS accelerator based on the unified NVS algorithm. Each sub-accelerator is optimized to exploit all parallelism exposed by unified NVS, incorporating a structured index assignment strategy and an elastic on-chip buffer to alleviate buffer conflicts for reduced latency. All sub-accelerators are coordinated using a hardware-aware scheduling strategy for boosted throughput. Experimental results show that the joint training strategy improves recall by 4.6% over the separated strategy and accuracy by 43.5% over LUT-NN. NeuVSA achieves $2.82 \times$ to $416.17 \times$ lower latency over CPU, GPU, DFX+ANNA, and PQA+ANNA, and up to $49.60 \times$ and $10.57 \times$ higher average throughput over CPU and GPU, respectively. NeuVSA also reduces chip area by 65.2% over PQA+ANNA.

With the rise of fully homomorphic encryption-based private inference, data centers are anticipated to simultaneously handle two disparate computational demands: plaintext-based non-private inference (NPI) and ciphertext-based private inference (PI). Unfortunately, current solutions face challenges in addressing this trend. They either depend on costly, inflexible dedicated accelerators or utilize general-purpose hardware with inferior performance. This limitation underscores the urgent need for a unified architecture capable of serving both normal and privacy-sensitive users with high efficiency.However, the fundamental disparities in computation patterns and resource management between NPI and PI make their architectural fusion intricate. To bridge this gap, we explore their inherent similarities and apply fine-grained reconfiguration to maximize resource sharing. We propose RTPU, a reconfigurable multi-core architecture that can seamlessly switch between tensor-based plaintext and polynomial ring-based ciphertext computations. Building upon its reconfigurable computing fabric and parallelization mechanism, we introduce a kernel group-based scheduling strategy to optimize hardware utilization and QoS. Experimental results show that: i) The RTPU architecture achieves near-ASIC performance and beyond-ASIC flexibility with substantial silicon reuse between NPI and PI. ii) The RTPU scheduler sustains high resource utilization for multi-tenant workloads with varying privacy requirements.

Dynamic power analysis in digital integrated circuits (ICs) conventionally relies on gate-level synthesis and simulation, creating a critical bottleneck in iterative design flows. We propose VIRTUAL, a multi-modality learning framework for rapid post-synthesis dynamic power estimation directly from Register-Transfer Level (RTL) implementations and input waveform vectors, eliminating the need for gate-level synthesis and extensive simulation. By decoupling features from input port waveforms and RTL implementations, VIRTUAL employs a transformer-based encoder to extract temporal patterns from input port waveforms and a graph neural network (GNN) to capture structural and functional dependencies within RTL implementations. Through self-supervised contrastive learning across sequential and graph modalities, the framework learns robust power-relevant representations with minimal labeled data. Subsequently, VIRTUAL refines the multi-modality embeddings using a lightweight fusion module and a power prediction head, enabling dynamic power estimation for fixed clock periods within seconds or minutes. Experimental evaluations demonstrate approximately a Pearson correlation coefficient (PCC) of 0.842 and a mean absolute percentage error (MAPE) of 23.43%, while achieving 14.27×speedup compared to traditional gate-level power analysis workflows. Experimental results across diverse RTL designs and input port waveforms validate that our proposed learning-based approach maintains the accuracy while significantly reducing design iteration time, transforming hours of synthesis and simulation into minutes of direct prediction.

With the rapid development of safety-critical applications such as autonomous driving and embodied intelligence, the functional safety of the corresponding electronic chips becomes more critical. Ensuring chip functional safety requires performing a large number of time-consuming RTL fault simulations during the design phase, significantly increasing the verification cycle. To meet time-to-market demands while ensuring thorough chip verification, parallel acceleration of RTL fault simulation is necessary. Due to the dynamic nature of fault propagation paths and varying fault propagation capabilities, task loads in RTL fault simulation are highly imbalanced, making traditional single-dimension parallel methods, such as structural-level parallelism, ineffective. Through an analysis of fault propagation paths and task loads, we identify two types of tasks in RTL fault simulation: tasks that are few in number but high in load, and tasks that are numerous but low in load. Based on this insight, we propose a two-dimensional parallel approach that combines structural-level and fault-level parallelism to minimize bubbles in RTL fault simulation. Structural-level parallelism combining with work-stealing mechanism is used to handle the numerous low-load tasks, while fault-level parallelism is applied to split the high-load tasks. Besides, we deviate from the traditional serial execution model of computation and global synchronization in RTL simulation by proposing a unified computation/global synchronization scheduling approach, which further eliminates bubbles. Finally, we implemented a parallel RTL fault simulation framework, RIROS. Experimental results show a performance improvement of 7.0× and 11.0× compared to the state-of-the-art RTL fault simulation and a commercial tool.

Graph processing suffers from severe locality challenges due to considerable inefficient irregular memory accesses, which mainly originate from random accesses to neighbors of active vertices (a.k.a frontiers). Graph reordering, which assigns continuous IDs to vertices that are more likely to be accessed consecutively, can improve access locality effectively and has demonstrated significant speedups across various architectures and systems. Existing graph reordering methods primarily explore the overlapping intensity of in-neighbor vertices for the data access locality characterization. However, many graph algorithms often activate a fraction of the vertices across the graphs, which vary substantially over different inputs and processing iterations. Many of these vertices are neither connected nor have any shared neighbors, but they are actually processed at the same time and exhibit potential data access locality, which is generally overlooked in prior graph reordering methods. We notice that the data locality between concurrently activated vertices are usually attributed to the overlapped$k$-order in-neighbors. As the number of$k$-order in-neighbors grows explosively, it is unacceptably time-consuming to analyze the overlapping of$k$-order in-neighbors for graph reordering directly. In this case, we propose to replace the overlapping calculation of$k$-order in-neighbors with frontier distribution analysis of a few BFS samplings. Specifically, we profile the frontiers distributed across iterations of different BFS samplings first and build a feature vector based on the activated iteration order of each vertex in the BFS samplings. On top of the feature vectors, we propose FrontOrder, which has a customized distance metric to characterize the locality between different vertices and leverages$K$-means to cluster vertices with high locality to guide graph reordering. In addition, FrontOrder also takes the load balance into consideration by predicting the runtime computing intensity with the learned clusters of vertices. According to our experiments, FrontOrder delivers an average performance speedup of${2.33\times}$and${1.57\times}$on Ligra and GPOP, respectively, and consistently outperforms the state-of-the-art graph reordering methods on a set of representative graph algorithms and datasets with moderate preprocessing overhead.

Accurate and efficient timing prediction at the register-transfer level (RTL) remains a fundamental challenge in electronic design automation (EDA), particularly in striking a balance between accuracy and computational efficiency. While static timing analysis (STA) provides high-fidelity results through comprehensive physical parameters, its computational overhead makes it impractical for rapid design iterations. Conversely, existing RTL-level approaches sacrifice accuracy due to the limited physical information available. We propose RTLDistil, a novel cross-stage knowledge distillation framework that bridges this gap by transferring precise physical characteristics from a layout-aware teacher model (Teacher GNN) to an efficient RTL-level student model (Student GNN), both implemented as graph neural networks (GNNs). RTLDistil efficiently predicts key timing metrics, such as arrival time (AT), and employs a multi-granularity distillation strategy that captures timing-critical features at node, subgraph, and global levels. Experimental results demonstrate that RTLDistil achieves significant improvement in RTL-level timing prediction error reduction, compared to state-of-the-art prediction models. This framework enables accurate early-stage timing prediction, advancing EDA’s “left-shift” paradigm while maintaining computational efficiency. Our code and dataset will be publicly available at https://github.com/sklp-eda-lab/RTLDistil.

Out-of-core graph processing systems are severely bottlenecked by I/O to the external storage because of the low compute-to-I/O ratio and the substantial amount of irregular data accesses. In order to alleviate the I/O bottleneck, prior works either focus on improving the bandwidth utilization by converting random I/O requests into sequential ones, or improving the data utilization by fetching only the required data to avoid the I/O redundancy. However, the former usually loads massive unused data, while the latter can induce frequent finegrained I/O requests, wasting the parallelism of the I/O channels and leading to under-utilization of the limited I/O bandwidth. Different from prior works, we systematically explore the use of computational storage devices (CSDs), which offer in-storage computing facilities with higher I/O bandwidth, to improve both the bandwidth utilization and data utilization for higher I/O efficiency. Specifically, we first introduce a graph-semanticaware data organization to enable the loading of only active graph partitions at the granularity of a physical page, reducing redundant I/O and enhancing data utilization. Additionally, we propose to coalesce parallel I/O requests of graph partitions distributed across different flash dies to maximize the parallelism of internal I/O channels, thereby fully utilizing the internal I/O bandwidth of CSDs. In addition, we capture the dynamic status of graph processing tasks across the iterations and partitions at runtime to dynamically offload I/O-intensive workloads into the instorage processors with restricted computing resources but higher I/O bandwidth to further improve the I/O efficiency. With the above techniques, we implement an out-of-core graph processing system prototype, namely TaijiGraph, on an open-channel CSD. According to our experiments on a set of representative graph datasets and algorithms, TaijiGraph achieves average speedups of$2.43 \times, 3.81 \times, 2.21 \times$and$7.89 \times$, respectively, when compared to state-of-the-art out-of-core graph processing systems including GridGraph, LUMOS, Blaze, and GraphSSD.

Emerging ReRAM-based accelerators process neural networks via in-memory computing (IMC) for ultra-high energy efficiency. However, significant overhead in peripheral circuits and complex nonlinear activation modes constrain system energy efficiency improvements. This work explores the hardware implementation of the Sigmoid and SoftMax activation functions of neural networks with stochastically binarized neurons by utilizing sampled noise from ReRAM devices to achieve a stochastic effect. We propose a complete ReRAM-based Analog Computing Accelerator (RACA) that accelerates neural network computation by leveraging stochastically binarized neurons in combination with ReRAM crossbars. The novel circuit design removes significant sources of energy/area efficiency degradation, i.e., the Digital-to-Analog and Analog-to-Digital Converters (DACs and ADCs) as well as the components to explicitly calculate the activation functions. Experimental results show that our proposed design outperforms traditional architectures across all overall performance metrics without compromising inference accuracy.

The "Shift-Left" Design-for-Test (DFT) paradigm has gained significant attention in recent years, enabling early-stage testability enhancement at the Register Transfer Level (RTL) to optimize Power-Performance-Area-Testability (PPAT) trade-offs and accelerate Time-to-Market (TTM). However, existing methods struggle to perform quantitative testability analysis at the RTL stage, particularly in Partial Scan Selection (PSS) and Test Point Insertion (TPI), due to the lack of structured netlist representations and cross-stage optimization. To address this challenge, we propose TESLA, a multi-LLM collaboration framework that autonomously performs PSS and TPI at the RTL stage. TESLA leverages the semantic understanding capabilities of Large Language Models (LLMs) to analyze RTL Verilog code and optimize testability without requiring synthesis. Two key data augmentation strategies are introduced for efficient Instruction Tuning: (1) back-annotating heuristic PSS results from the synthesized netlist to RTL, and (2) utilizing advanced LLMs guided by DFT knowledge to generate synthetic RTL TPI training data. Furthermore, we integrate Direct Preference Optimization (DPO) to refine LLM decision-making, incorporating real feedback from commercial EDA tools to align optimization objectives with practical testability metrics. The experimental results demonstrate that our proposed approach achieves better test coverage compared to other RTL stage PSS and TPI combination schemes on the majority of circuits in the RTLLM benchmark, while also reducing the number of patterns for a significant portion of the circuits. On the larger, hierarchical OpenCores benchmark, our approach surpasses the solution combining heuristic PSS and commercial DFT tool’s TPI, achieving improvements on the same two test metrics.

Precise and rapid performance prediction for dataflow-based accelerators is essential for efficient hardware design and design space exploration.However, existing methods often fall short due to limited generalization across hardware architectures, applications, and input-dependent control flows.Considering the rich program semantic knowledge contained in pre-trained large language models (LLMs), which is used for text and code generation, we propose a progressive numeric modeling paradigm based on pre-trained LLMs.This is an approach to achieve hardware, application, and control flow-sensitive generalization in dataflow accelerator performance prediction.Specifically, to make accurate performance estimates for unseen applications beyond the scope of the training data, we propose a numeric prediction model capable of estimating any performance range.This is achieved by treating the numerical data of the dataflow program as separate tokens and using categorical output for performance values, allowing us to observe confidence at each numerical position.Second, LLMulator supports input-adaptive performance prediction by introducing a reinforcement learning-based dynamic calibration framework, enabling accurate modeling of applications whose control flow varies with input-unlike prior methods that * Corresponding author.

Graph reordering is an effective technique for improving the access locality of graph processing. However, existing methods often overlook the data access locality among concurrently activated vertices (a.k.a. frontiers). These vertices, while lacking direct connections or shared neighbors, can exhibit significant locality attributed to their overlapped k-order in-neighbors. However, calculating such overlaps directly is computationally prohibitive. We propose to estimate the overlapped k-order in-neighbors through frontier distribution analysis based on a few BFS samples. Our proposed graph reordering method, FrontOrder, constructs feature vectors from the frontier distribution of BFS samples, and employs K-means clustering with a custom distance metric to group vertices with high locality. Additionally, the learned clusters can predict runtime computing intensity, enabling load balancing through vertex reordering. FrontOrder achieves average speedups of 2.65× on Ligra and 1.73× on GPOP, outperforming state-of-the-art methods.

Approximate nearest neighbor search (ANNS) is essential for applications like recommendation systems and retrieval-augmented generation (RAG) but is highly I/O-intensive and memory-demanding. CPUs face I/O bottlenecks, while GPUs are constrained by limited memory. DRAM-based Processing-in-Memory (DRAM-PIM) offers a promising alternative by providing high bandwidth, large memory capacity, and near-data computation. This work introduces DRIM-ANN, the first optimized ANNS engine leveraging UPMEM’s DRAM-PIM. While UPMEM scales memory bandwidth and capacity, it suffers from low computing power because of the limited processor embedded in each DRAM bank. To address this, we systematically optimize ANNS approximation configurations and replace expensive squaring operations with lookup tables to align the computing requirements with UPMEM’s architecture. Additionally, we propose load-balancing and I/O optimization strategies to maximize parallel processing efficiency. Experimental results show that DRIM-ANN achieves a 2.46× speedup over a 32-thread CPU and up to 2.67× over a GPU when deployed on computationally enhanced PIM platforms.

As integrated circuits grow in complexity, test point insertion (TPI) has become vital for enhancing testability and improving reliability in design for test (DFT). Recent studies have shown the effectiveness of deep learning-based TPI using graph neural networks (GNNs) in improving test quality. However, the high cost of collecting training data, incomplete capture of the intrinsic characteristics of circuits, and the vast search space in large circuits hinder the performance of existing intelligent approaches. This paper introduces HighTPI, a two-stage learning approach for TPI to effectively reduce the number of test patterns, which leverages hierarchical graph representation by constructing a hypergraph based on hypernodes in fanout-free regions (FFRs). HighTPI better captures multi-fanout reconvergence information while lowering the cost of obtaining ground-truth labels due to the smaller scale of the FFR-based hypergraph. Two specialized GNNs are designed in stage I to select candidate insertion points for observation and control points, respectively. This integration of expert knowledge through supervised learning helps guide the reinforcement learning process in stage II, mitigating the challenges of sparse rewards and a large decision space. The experimental results demonstrate that HighTPI outperforms other TPI methods in terms of the trade-off between pattern reduction and fault coverage enhancement.

Modern processors integrate carefully designed micro-architectural components within the front-end to optimize performance. These components include instruction cache, micro-operation cache, and instruction prefetcher. Through experimentation, we observed that the rate of instruction generation in the fetch unit markedly exceeds the execution rate in the decode unit. However, existing frameworks of processors fail to explain this phenomenon. Consequently, we empirically validate the presence of an optimization feature, referred to as the Fetch Target Queue (FTQ), within the Intel processor. To the best of our knowledge, our study represents the first empirical validation of FTQ across various Intel processors and provides a comprehensive characterization of unrecorded FTQ micro-structural details on Intel processors. Our analysis uncovers overlooked insights that front-end rollbacks caused by the incorrectly ordered instructions or mismatched instruction lengths stored in FTQ introduce specific execution latencies. Based on these observations, we introduce the Oxpecker attack, consisting of two attack primitives, which leverages the FTQ to construct novel side-channel attacks. We construct two distinct exploitation scenarios for each attack primitive to demonstrate the Oxpecker attack’s capability to leak secret control flow information and break Kernel Address Space Layout Randomization.

This article introduces OpenLS-DGF, an adaptive logic synthesis dataset generation framework, to enhance machine-learning (ML) applications within the logic synthesis process. Previous dataset generation flows were tailored for specific tasks or lacked integrated ML capabilities. While OpenLS-DGF supports various ML tasks by encapsulating the three fundamental steps of logic synthesis: 1) Boolean representation; 2) logic optimization; and 3) technology mapping. It preserves the original information in both Verilog and ML-friendly GraphML formats. The Verilog files offer semi-customizable capabilities, enabling researchers to insert additional steps and incrementally refine the generated dataset. Furthermore, OpenLS-DGF includes an adaptive circuit engine that facilitates the final dataset management and downstream tasks. The generated OpenLS-D-v1 dataset comprises 46 combinational designs from established benchmarks, totaling over 966 000 Boolean circuits. OpenLS-D-v1 supports integrating new data features, making it more versatile for new tasks. This article demonstrates the versatility of OpenLS-D-v1 through four distinct downstream tasks: circuit classification, circuit ranking, quality of results (QoR) prediction, and probability prediction. Each task is chosen to represent essential steps of logic synthesis, and the experimental results show the generated dataset from OpenLS-DGF achieves prominent diversity and applicability. The source code and datasets are available athttps://github.com/Logic-Factory/ACE/blob/master/OpenLS-DGF.

Recent advances in large language models (LLMs) have demonstrated significant potential for automated hardware description language (HDL) code generation from high-level specifications. However, two critical challenges limit further progress in this domain: the scarcity of quality Verilog training data and the inability of current approaches to generate RTL code optimized for power, performance, and area (PPA) metrics. This article presents a comprehensive data-centric framework that addresses these limitations through innovations in both pre-fine-tuning data preparation and after-fine-tuning optimization strategies. In the pre-fine-tuning phase, we tackle the data scarcity problem with an automated design-data augmentation framework that generates high-volume, high-quality natural language specifications aligned with corresponding Verilog code and EDA scripts. Our approach creates a complete RTL-level feedback loop by augmenting EDA scripts, RTL code, and EDA tool feedback. In the after-fine-tuning phase, we focus on generating PPA-aware RTL code through a novel search and prompt framework. Our approach implements iterative filtering and selection of LLM-generated Verilog variants while providing high-quality predefined prompts, including composition and interface specifications. To evaluate the effectiveness of our data augmentation method, we fine-tune Llama 2-13B and Llama 2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data. Additionally, to evaluate the effectiveness of the our agent framework, we compare the PPA on the GPT-3.5, where the results show that the agent refined RTL code can have a better quality than the generated RTL code only with GPT-3.5.

Gate-level fault simulation is essential for automatic test pattern generation (ATPG). The traditional event-driven simulation is time-consuming due to the large number of faults. While parallel fault simulation with GPGPUs shows promise, it faces reduced parallel efficiency on large circuits. This is mainly due to the increased space required to store fault values, limiting the number of faults that can be processed in parallel and preventing full utilization of the GPU’s capabilities. In this study, we propose a memory-efficient fault machine implementation FM gpu based on a circular vector, which is tailored for GPU fault simulation with some sacrifices of time efficiency and a variable length limit. We also propose a fully adaptive parallel fault simulation framework based on the CPU-GPU heterogeneous system, which includes two stages on the GPU and performs CPU simulation at the same time. All parameters related to GPU memory optimization and workload balancing in the framework can be adjusted adaptively. The experimental results demonstrate that our method achieves better memory efficiency and speedup compared to the previous GPU fault simulation methods, a maximum speedup of 137.48× compared to the baseline open-source simulator with 32 threads, and a maximum speedup of 2.52× compared to a 32-thread commercial tool.

Hardware description language (HDL) code designing is a critical component of the chip design process, requiring substantial engineering and time resources. Recent advancements in large language models (LLMs), such as GPT series, have shown promise in automating HDL code generation. However, current LLM-based approaches face significant challenges in meeting real-world hardware design requirements, particularly in handling complex designs and ensuring code correctness. Our evaluations reveal that the functional correctness rate of LLM-generated HDL code significantly decreases as design complexity increases. In this article, we propose the AutoSilicon framework, which aims to scale up the hardware design capability of LLMs. AutoSilicon incorporates an agent system, which (1) allows for the decomposition of large-scale, complex code design tasks into smaller, simpler tasks; (2) provides a compilation and simulation environment that enables LLMs to compile and test each piece of code it generates; and (3) introduces a series of optimization strategies. Experimental results demonstrate that AutoSilicon can scale hardware designs to projects with code equivalent to over 10,000 tokens. In terms of design quality, it further improves the syntax correctness rate and functional correctness rate compared with approaches that do not employ any extensions. For example, compared to directly generating HDL code using GPT-4-turbo, AutoSilicon enhances the syntax correctness rate by an average of 35.8% and improves functional correctness by an average of 35.6%.

Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our observation, the test patterns generated by commercial ATPG tools in test compression mode still contain redundancy. To tackle this obstacle, we propose a post-flow static test compaction method that utilizes a partial fault dictionary instead of a full fault dictionary, and leverages a dedicated Pure-MaxSAT solver to re-compact the test patterns generated by commercial ATPG tools. We also observe that commercial ATPG tools offer a more comprehensive selection of candidate patterns for compaction in the “n-detect” mode, leading to superior compaction efficacy. In experiments on ISCAS89, ITC99, and open-source RISC-V CPU benchmarks, our method achieves an average reduction of 21.58% and a maximum of 29.93% in test cycles evaluated by commercial tools while maintaining fault coverage. Furthermore, our approach demonstrates improved performance compared with existing methods.

Graph-based deep learning point cloud processing has gained increasing popularity but its performance is dragged by the dominating graph construction (GC) phase with irregular computation and memory access. Existing works that accelerate GC by tailoring architecture for a single GC algorithm fail to maintain efficiency because they neglected the best GC algorithm variation incurred by the point-cloud density variation in changing scenarios. Therefore, we propose APoX, a unified architecture with an adaptive GC scheme that can identify the optimum GC approach according to the point cloud variation. Experiments indicate that APoX achieves higher performance and energy efficiency over existing accelerators.

By leveraging the power of open-source software, the EDA tool offers a cost-effective and flexible solution for designers, researchers, and hobbyists alike. Open-source EDA promotes collaboration, innovation, and knowledge sharing within the EDA community. It emphasizes the role of the toolchain in accelerating the development of electronic systems, reducing design costs, and improving design quality. This paper presents an open-source EDA project, iEDA, aiming to build a basic infrastructure for EDA technology evolution and closing the industrial-academic gap in the EDA area. As the foundation for developing EDA tools and researching EDA algorithms and technologies, iEDA is mainly composed of file system, database, manager, operator and interface. To demonstrate the effectiveness of iEDA, we implement and tape out four chips of different scales (from 700k to 500M gates) on different process nodes (110nm and 28nm) with iEDA. iEDA is publicly available on the project home page https://github.com/OSCC-Project/iEDA.

The stagnation of Moore’s law stimulates the concept of breaking monolithic chips into smaller chiplets. However, tactic design partitioning remains an unaddressed issue despite its crucial role in chip product cost reduction. In this paper, we propose Chipletizer, a framework to guide the design partitioning for those who would benefit from chiplet reuse across a line of SoC products. The proposed generic framework supports the repartitioning of multiple SoCs into reusable chiplets economically and efficiently with user-specified parameters. Experimental results show that, compared with existing partitioning strategies, our proposed framework achieves notable cost improvement on realistic products with acceptable power and latency overheads.

Fast simulation is vital for efficient digital design, especially for safety-critical applications, where functional safety verification is paramount. However, existing gate-level event-driven simulators often encounter performance challenges attributed not only to inefficient memory access, but also to redundancy events in sequential elements during event-driven algorithms. In this paper, we introduce a memory-efficient, low-redundancy event-driven simulation framework to accelerate sequential circuit simulation. Firstly, we propose an event-based memory layout approach that fully considers memory access characteristics within and between logic levels to enhance the spatial locality of simulators. Secondly, we present an event trace approach tailored for flip-flops to reduce event redundancies that hinder simulator performance. Comparative experiments demonstrate that our proposed optimization strategies deliver an average performance improvement of 1.9× for logic simulation and 1.4× for fault simulation.

Recent advances in large language models have demonstrated their potential for automated generation of hardware description language (HDL) code from high-level prompts. Researchers have utilized fine-tuning to enhance the ability of these large language models (LLMs) in the field of Chip Design. However, the lack of Verilog data hinders further improvement in the quality of Verilog generation by LLMs. Additionally, the absence of a Verilog and electronic design automation (EDA) script data augmentation framework significantly increases the time required to prepare the training dataset for LLM trainers. This paper proposes an automated design-data augmentation framework, which generates high-volume and high-quality natural language aligned with Verilog and EDA scripts. For Verilog generation, it translates Verilog files to an abstract syntax tree and then maps nodes to natural language with a predefined template. For Verilog repair, it uses predefined rules to generate the wrong verilog file and then pairs EDA Tool feedback with the right and wrong verilog file. For EDA Script generation, it uses existing LLM(GPT-3.5) to obtain the description of the Script. To evaluate the effectiveness of our data augmentation method, we finetune Llama2--13B and Llama2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model (ChipGPT-FT1) has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data.

Fully Homomorphic Encryption (FHE) is one of the most promising privacy-preserving techniques that has drawn increasing attention from academia and industry due to its ideal security. Chiplet-based designs integrate multiple dies into the package delivering high performance and thereby are embraced by the resources-hungry FHE. Despite the chiplet-based system with various specialized accelerators, it falls short in supporting FHE with the novel polynomial operations. For a chiplet-based system that is not tailored for FHE, one common approach to support FHE is designing a new dedicated accelerator, However, this full design-and-build approach overlooks the existing abundant resources of accelerators in the system and incurs repeated customization and resource waste.

Automatic test pattern generation (ATPG) is a critical technology in integrated circuit testing. It searches for effective test vectors to detect all possible faults in the circuit as entirely as possible, thereby ensuring chip yield and improving chip quality. However, the process of searching for test vectors is NP-complete. At the same time, the large amount of backtracking generated during the search for test vectors can directly affect the performance of ATPG. In this paper, a learning-based ATPG framework, SmartATPG, is proposed to search for high-quality test vectors, reduce the number of backtracking during the search process, and thereby improve the performance of ATPG. SmartATPG utilizes graph convolutional network (GCN) to fully extract circuit feature information and efficiently explore the ATPG search space through reinforcement learning (RL). Experimental results indicate that the proposed SmartATPG outperforms traditional and artificial neural network (ANN)-based heuristic strategies on most benchmark circuits.

Quantization is one of the most hardware-efficient ways to reduce inference costs for deep neural network (DNN) models. Nevertheless, with the continuous increase of DNN model sizes (240× in two years) and the emergence of large language models, existing static quantization methods fail to utilize the sparsity and redundancy of models sufficiently. Motivated by the pervasive dynamism in data tensors across DNN models, we propose a dynamic precision quantization algorithm to further reduce computational costs beyond statically quantized DNN models. Furthermore, we find that existing precision-flexible accelerators cannot support the DNN models with dynamic precision. To this end, we design a novel accelerator, Drift, and achieve online scheduling to efficiently support dynamic precision execution. We conduct experiments with various DNN models, including CNN-based and Transformer-based models. Evaluation results show that Drift achieves 2.85× speedup and 3.12× energy saving compared to existing precision-flexible accelerators with statically quantized models.

The use of cross-scheme fully homomorphic encryption (FHE) in privacy-preserving applications present to be a new challenge to hardware accelerator design. Existing accelerator architectures with customized polynomial-level operator abstraction fail to efficiently handle hybrid FHE schemes due to the mismatch between computational demands and available hardware resources under various parameter settings. In this work, we propose a new accelerator architecture that consists of a novel finer-grained low-level operator, i.e., Meta-OP, that not only mathematically supports a diverse range of polynomial operations, but is also hardware-friendly for accelerator design without complex topological logic. We then design a new slot-based data management scheme to efficiently handle the distinct memory access patterns over the Meta-OP. With a slot-based data management approach, Alchemist can accelerate both arithmetic and logic FHE workloads with high hardware utilization rates. In the experiment, we show that Alchemist is up to 24,829X faster than CPU. For arithmetic FHE, compared with the SOTA ASIC accelerators, Alchemist achieves a 29.4X performance per area improvement on average. For logic FHE, compared with the SOTA ASIC accelerators, Alchemist achieves a 7.0X overall speed up on average.

Graph convolutional network (GCN) has been proven powerful in various tasks for it combines both neural networks and graph processing operators. However, this characteristic makes GCN exhibit hybrid execution patterns, which is unfavorable for CPUs and GPUs. Therefore, designing specialized GCN accelerators is becoming a prevalent paradigm. Unfortunately, as graph scale continues to grow, existing GCN accelerators suffer from significant bandwidth consumption and memory footprint as they neglect the inherent semantic redundancy of vertex features. Although applying Product Quantization to GCN is a promising solution to reduce the sizeable graph data via distilling semantic redundancy, it introduces novel operations with unique patterns that existing GCN accelerators cannot support. In this paper, we propose GPACE, an energy-efficient GCN accelerator that can fully harness the potential of PQ to reduce bandwidth consumption and data movement. GPACE is designed with a lookup-efficient architecture and well-optimized dataflow to support the unique data access and computation pattern of PQ-GCN. In addition to leveraging PQ to distill semantic redundancy, we exploit the operation redundancy and propose a redundancy-aware architecture to detect and reduce types of redundant operations to achieve higher energy efficiency. Evaluations show GPACE achieves high speedup and energy saving compared with CPU, GPU, and specialized GCN accelerators.

ReRAM-based accelerator of bit-slicing architecture is a promising solution to neural network inference, which allows ineffectual bit-operation removal for greater potential gains. However, existing techniques mostly exploit the removal of weight-associated ineffectual operations, which cannot eliminate the activation-induced ineffectual operations. Alternatively, some approaches adopt an isolated two-stage approach to remove at the weight and activation-level, which leaves a big proportion of ineffectual bit-level operations. Therefore, in contrast to all these coarse-grained operation removal techniques, it is challenging to jointly eliminate ineffectual bit-operation induced by either activation or weight bit-slices for ReRAM-based accelerators. This work presents a novel ineffectual bit-operation removal approach and the accompanied ReRAM-based bit-operation clipping architecture that skips all those bit-level operations that make negligible impacts on neural network outputs. In experiments, the proposed bit-operation clipping ReRAM accelerator, Bit-Trimmer, achieves$5.28 \times$energy efficiency and$2.04 \times$speedup on average. Besides, compared with two SOTA ReRAM accelerator designs with bit-operation removal, it outperforms by$1.56 \times$and$1.88 \times$energy efficiency.

An Large Language Model (LLM)-based question-answering (QA) system has gained attention for its conversational ability. However, domain knowledge limitations, time lag, high training costs, and security concerns suggest building on-premise QA systems with embedding techniques. However, deploying embedding-based QA systems on existing GPUs or domain-specific accelerators is sub-optimal as they only address high computation costs and ignore large memory footprint and data movement costs, which impact response latency and user experience. To address these issues, we propose a hybrid near-data processing platform, HyQA, which collaboratively optimizes response latency, memory footprint, and data movement cost by exploiting the benefit of near-memory and near-storage computing simultaneously. First, HyQA analyzes computational patterns of sub-tasks in embedding-based QA systems, tailors domain-specific hardware accelerators, and assigns suitable computational paradigms. Second, these dedicated accelerators are designed to communicate directly with flash memory, avoiding additional data movement. The experiment shows that HyQA significantly improves performance and reduces energy over CPU, GPU, Cognitive SSD, and DeepStore platforms.

Elliptic curve cryptography (ECC) is widely used in public key encryption, but its high-speed deployment faces challenges due to algorithmic and arithmetic complexity. In this paper, we present a high-performance ECC processor for the elliptic curve point multiplication (ECPM) of NIST P-256. Our approach employs a fully pipelined architecture featuring a 7-stage, 256-bit multiplier operating at a high frequency. To manage the data flow of the ECPM operation process, we devise a controller equipped with configurable instructions, which provides ECPM operations with higher flexibility to meet diverse contextual requirements. Additionally, we introduce a compact pipeline schedule to reduce ECPM computation clock cycles. The proposed LUT-based design achieves ECPM computation in 0.039 ms on FPGA (Virtex-7 platform) and 0.037 ms on ASIC (90nm technology), requiring only 10712 clock cycles.

Natural language interfaces have exhibited considerable potential in the automation of Verilog generation derived from high-level specifications through the utilization of large language models, garnering significant attention. Nevertheless, this paper elucidates that visual representations contribute essential contextual information critical to design intent for hardware architectures possessing spatial complexity, potentially surpassing the efficacy of natural-language-only inputs. Expanding upon this premise, our paper introduces an open-source benchmark1 for multi-modal generative models tailored for Verilog synthesis from visual-linguistic inputs, addressing both singular and complex modules. Additionally, we introduce an open-source visual and natural language Verilog query language framework to facilitate efficient and user-friendly multi-modal queries. To evaluate the performance of the proposed multi-modal hardware generative AI in Verilog generation tasks, we compare it with a popular method that relies solely on natural language. Our results demonstrate a significant accuracy improvement in the multi-modal generated Verilog compared to queries based solely on natural language. We hope to reveal a new approach to hardware design in the large-hardware-design-model era, thereby fostering a more diversified and productive approach to hardware design.

The advancements in learning-based embedding models have propelled the embedding vector to become a vital data structure for various semantic search applications. The graph-based vector search method, which relies on the k-nearest neighbor (k-NN) graph, has gained immense popularity due to its superior performance in recall and throughput compared to other vector search methods. However, the construction of the k-NN graph is a time-consuming process, which not only affects the efficiency of identifying the optimal k-NN graph but also impacts data updates, especially for large-scale vector datasets. Despite the availability of various software-level optimization methods, such as iterative, refinement, and incremental methods, their peak performance is still limited to the underlying CPU platform. Furthermore, the existing GPU and specialized accelerator solutions only focus on partial k-NN graph construction methods and still encounter low efficiency when executing iterative methods due to irregular memory access, low data reuse, and redundant distance calculations.

Fault simulation is a fundamental component in the design for testability (DFT) processes, especially in automatic test pattern generation (ATPG). Various approaches have been proposed to enhance the efficiency of fault simulation on multi-core systems. However, these approaches have not taken full consideration of the intrinsic characteristics of deterministic patterns. Deterministic patterns are generated by ATPG and are predominantly employed in practical applications rather than random patterns. In this paper, we introduce DDP-Fsim, a fast and scalable fault simulator on multi-core systems. DDP-Fsim capitalizes on the distinctive nature of deterministic patterns, wherein a small subset of patterns can effectively detect the majority of faults. Initially, DDP-Fsim parallels in fault dimension by dynamically scheduling fanout-free regions (FFR) to handle easy-to-detect faults. Subsequently, it parallels in pattern dimension by dynamically scheduling patterns to address the remaining hard-to-detect faults. Experiments demonstrate that on a 24-core system, DDP-Fsim is 10× faster than the commercial tools for full-scan circuits and deterministic patterns. Additionally, DDP-Fsim with 24 cores achieves an average speed-up of 16× compared to its single-core execution, while the commercial tools with 24 cores achieves only 3×-6× speed-up than their single-core execution. This indicates the significantly superior scalability for DDP-Fsim.

Large language models (LLMs) have catalyzed an upsurge in automatic code generation, garnering significant attention for register transfer level (RTL) code generation. Despite the potential of RTL code generation with natural language, it remains error-prone and limited to relatively small modules because of the substantial semantic gap between natural language expressions and hardware design intent. In response to the limitations, we propose a methodology that reduces the semantic gaps by utilizing C/C++ for generating hardware designs via High-Level Synthesis (HLS) tools. Basically, we build a set of C-to-HLS optimization strategies catering to various code patterns, such as nested loops and local arrays. Then, we apply these strategies to sequential C/C++ code through in-context learning, which provides the LLMs with exemplary C/C++ to HLS prompts. With this approach, HLS designs can be generated effectively. Since LLMs still face problems in determining the optimized pragma parameters precisely, we have a design space exploration (DSE) tool integrated for pragma parameter tuning. Furthermore, we also employ profiling tools to pinpoint the performance bottlenecks within a program and selectively convert bottleneck components to HLS code for hardware acceleration. By combining the LLM-based profiling, C/C++ to HLS translation, and DSE, we have established HLSPilot---the first LLM-enabled high-level synthesis framework, which can fully automate the high-level application acceleration on hybrid CPU-FPGA architectures. According to our experiments on real-world application benchmarks, HLSPilot achieve comparable performance in general and can even outperform manually crafted counterparts, thereby underscoring the substantial promise of LLM-assisted hardware designs.

Static test compaction aims to reduce the number of generated test patterns after automatic test pattern generation (ATPG) to enable one pattern to detect more faults. However, existing traditional algorithms require the establishment and maintenance of a fault detection profile to obtain essential faults, identified as those detectable exclusively by a single pattern (denoted as 1-D), incurring substantial computational overhead. We propose a novel fault gates classification approach based on graph convolutional network (GCN). By categorizing fault gates into with and without hard-to-detect faults, we selectively construct a partial fault detection profile only for the fault gates with hard-to-detect faults. Partial fault detection profile effectively reduces the time spent on establishing and maintaining it, as well as the time cost of obtaining essential faults. The experiment shows that our improved method can increase pattern reduction efficiency while accelerating, and its impact on fault coverage can be ignored. Compared with the original algorithm, the maximum acceleration ratio is 6.44×, and the number of patterns is reduced by up to 20.68%.

In applications such as automotive chips that require high service responsiveness, ensuring the functional safety of electronic systems is crucial. The prevalent method involves conducting Failure Modes, Effects, and Diagnostic Analysis (FMEDA) and fault simulation at the design verification stage to assess safety levels. However, existing approaches primarily analyze at the register transfer level (RTL), which does not reflect the actual structure of chips where faults occur at the gate level, resulting in inaccuracies. This is due to the slower analysis speed at the gate level, making it challenging to balance precision with speed, thus defaulting to RTL for simulation. To address these challenges, we propose an innovative method for functional safety analysis and verification that integrates advanced gate-level fault simulation technology with FMEDA techniques. Our approach is based on an enhanced gate-level FMEDA framework, enabling deeper and more accurate safety performance analysis. Through experimental verification, our method has proven to be over 3 times faster than commercial tools in fault simulation, significantly enhancing the reliability and speed of the functional safety process. Ultimately, our research provides rapid and precise safety analysis and verification at the gate level for high-risk applications like automotive chips, offering robust technical support and practical guidelines for advancing functional safety technology in this sector.

Graph is widely utilized as a key data structure in many applications such as social network and recommendation systems. However, many real-world graphs are constructed with large-scale correlated data, which typically involves massive random memory accesses and distance calculation resulting in considerable processing time and energy consumption on CPUs and GPUs. In this work, we present GCiM, a specialized processing-in-memory architecture for efficient graph construction and updating. By directly deploying the computing units on the logic layer of the 3D stacked memory, GCiM benefits from memory-level parallelism and further improves the memory access efficiency with both optimized processing ordering and data layout. In addition, we notice that the computing engines for graph updating suffer from dramatic utilization imbalance and integrate a power gating module to cut down the power supply of the idle computing engines at runtime and further enhance the energy efficiency. According to our experiments, GCiM shows 634.64X and 56.27X speedup while consuming 1194.14X and 505.07X less energy compared to CPU and GPU respectively.

ReRAM-based Computing-in-Memory (CiM) architecture has been considered a promising solution to high-efficiency neural network accelerator, by conducting in-situ matrix multiplications and eliminating the movement of neural parameters from off-chip memory to computing units. However, we observed specific features of Graph Convolutional Network (GCN) tasks pose design challenges to implement a high-efficiency ReRAM GCN accelerator. The ultra-large input feature data in some GCN tasks incur massive data movements, the extremely sparse adjacency matrix and input feature data involve the valid computation, and the super-large adjacency matrix that exceeds available ReRAM capacity causes frequent expensive write operations. To address the above challenges, we propose TARe, a Task-Adaptive CiM architecture, which consists of a hybrid in-situ computing mode to support the input feature in crossbar computing, a compact mapping scheme for efficient sparse matrix computing, and a write-free mapping to eliminate write activities in the computations with the super-large adjacency matrix. Additionally, TARe is facilitated with a task adaptive selection algorithm to generate optimized design schemes for graph neural network tasks that have various operand sizes and data sparsity. We evaluate TARe on 11 diverse graph neural network tasks and compare it with different design counterparts, and the results show that achieves 168.06× speedup and 10.95× energy consumption reduction on average over the baseline in common graph convolutional network workloads.

Static learning is a learning algorithm for finding additional implicit implications between gates in a netlist. In automatic test pattern generation (ATPG) the learned implications help recognize conflicts and redundancies early, and thus greatly improve the performance of ATPG. Though ATPG can further benefit from multiple runs of incremental or dynamic learning, it is only feasible when the learning process is fast enough. In this article, we study the performance optimization of static learning through parallelization on heterogeneous computing architectures, which includes multicore microprocessors (CPUs), and graphics processing units (GPUs). We discuss the advantages and limitations of each of these architectures. With their specific features in mind, we propose two different parallelization strategies that are tailored to multicore CPUs and GPUs. Speedup and performance scalability of the two proposed parallel algorithms are analyzed. It is demonstrated that for million-gate designs, close to linear performance gain is achieved on multicore CPUs, and up to$260\times $speedup over a commercial tool can be obtained on a single graphic card.

Efficient deep learning models, especially optimized for edge devices, benefit from low inference latency to efficient energy consumption. Two classical techniques for efficient model inference are lightweight neural architecture search (NAS), which automatically designs compact network models, and quantization, which reduces the bit-precision of neural network models. As a consequence, joint design for both neural architecture and quantization precision settings is becoming increasingly popular. There are three main aspects that affect the performance of the joint optimization between neural architecture and quantization: quantization precision selection (QPS), quantization aware training (QAT), and neural architecture searching (NAS). However, existing works focus on at most twofold of these aspects, and result in secondary performance. To this end, we proposed a novel automatic optimization framework, DAQUDAQU is an ancient liquor fermentation process., that allows jointly searching for Pareto-optimal neural architecture and quantization precision combination among more than 1047 quantized subnet models. To overcome the instability of the conventional automatic optimization framework, DAQU incorporates a warm-up strategy to reduce the accuracy gap among different neural architectures, and a precision-transfer training approach to maintain flexibility among different quantization precision settings. Our experiments show that the quantized lightweight neural networks generated by DAQU consistently outperform state-of-the-art NAS and quantization joint optimization methods.

Amid growing concerns about hardware security, comprehensive security testing has become essential for chip certification. This paper proposes a deep-testing method for identifying Trojans of particular concern to middle-to-high-end users, with a focus on illegal instructions. A hidden instruction Trojan can employ a low-probability sequence of normal instructions as a boot sequence, which is followed by an illegal instruction that triggers the Trojan. This enables the Trojan to remain deeply hidden within the processor. It then exploits an intrusion mechanism to acquire Linux control authority by setting a hidden interrupt as its payload. We have developed an unbounded model checking (UMC) technique to uncover such Trojans. The proposed UMC technique has been optimized with slicing based on the input cone, head-point replacement, and backward implication. Our experimental results demonstrate that the presented instruction Trojans can survive detection by existing methods, thus allowing normal users to steal root user privileges and compromising the security of processors. Moreover, our proposed deep-testing method is empirically shown to be a powerful and effective approach for detecting these instruction Trojans.

Dynamic graphs can be utilized to model many real-world applications like social media analysis in which the connections and entities evolve continuously. Hence, the processing of dynamic graphs is gaining increasing popularity. However, prior dynamic graph processing systems mainly focus on the optimization of graph analytics but overlook graph updating which manages the evolving graph structure and presents a unified view to graph analytics. Since graph updating operates on evolving graphs and involves a large number of irregular memory accesses, it poses a substantial influence on the performance of dynamic graph processing systems. In this work, we observe that graph updating is mainly bottlenecked by a frequent indirect memory access pattern *(*(BAi+offset)). The pattern is inherent to the typical graph updating from the incoming edge stream to the base data store organized with either an adjacent list or a compressed sparse row. With this observation, we propose a novel Prefetcher for Dynamic Graph updating abbreviated as PDG. PDG is a lightweight pipelined instruction-based prefetcher specialized for graph updating and it is also compatible with the irregular memory access pattern BAi widely used in graph analytics. In addition, it leverages a monitor of the instruction queue to decide the appropriate timing of prefetching to make the best use of the cache. According to our experiments, PDG achieves 1.60×, 1.26× and 1.30× performance speedup compared to three representative prefetchers respectively with negligible hardware overhead in graph updating.

While Federated learning (FL) is attractive for pulling privacy-preserving distributed training data, the credibility of participating clients and non-inspectable data pose new security threats, of which poisoning attacks are particularly rampant and hard to defend without compromising privacy, performance or other desirable properties. In this paper, we propose a self-purified FL (SPFL) method that enables benign clients to exploit trusted historical features of locally purified model to supervise the training of aggregated model in each iteration. The purification is performed by an attention-guided self-knowledge distillation where the teacher and student models are optimized locally for task loss, distillation loss and attention loss simultaneously. SPFL imposes no restriction on the communication protocol and aggregator at the server. It can work in tandem with any existing secure aggregation algorithms and protocols for augmented security and privacy guarantee. We experimentally demonstrate that SPFL outperforms state-of-the-art FL defenses against poisoning attacks. The attack success rate of SPFL trained model remains the lowest among all defense methods in comparison, even if the poisoning attack is launched in every iteration with all but one malicious clients in the system. Meantime, it improves the model quality on normal inputs compared to FedAvg, either under attack or in the absence of an attack.

To ensure resilient neural network processing on even unreliable hardware, comprehensive reliability analysis against various hardware faults is generally required before the neural network models are deployed, and efficient fault injection tools are highly demanded. However, many existing fault injection tools remain limited to basic fault injection and fail to provide fine-grained vulnerability analysis capability. In addition, many of the fault injection tools also need to change the neural network models and make the fault injection closely coupled with normal neural network processing, which complicates the use of these tools and slows down the fault simulation. The various fault injection implementations and error metrics make the comparison between different fault-tolerant studies difficult. To this end, we propose MRFI, a highly configurable multiresolution fault injection tool for deep neural networks. It enables users to modify an independent fault configuration file rather than neural network models for fault injection and vulnerability analysis. Particularly, it integrates extensive fault analysis functionalities from different perspectives and enables multiresolution investigation of the vulnerability of neural networks. In addition, it does not modify the major neural network computing framework of PyTorch. Hence, it allows parallel processing on GPUs naturally and exhibits fast fault simulation according to our experiments. Moreover, we also have the fault injection calibrated with fault simulation with architectural details and validate the accuracy of the proposed fault injection. Finally, MRFI is also open-sourced on GitHub (MRFI https://github.com/fffasttime/MRFI).

As the target of test synthesis is to obtain highly compacted test patterns with acceptable fault coverage, automatic test pattern generation (ATPG) plays an important role in the design for test (DFT) process. Distributed ATPG systems have been designed to harness the parallelism of computer architectures to accelerate this process. However, due to delayed communication among distributed nodes, the redundancy of certain computations and substantial pattern expansion issues may arise. To tackle this problem, this paper proposes a test compaction module based on Pure MaxSAT to re-compact the patterns generated by the distributed ATPG system, significantly reducing the number of patterns without loss of fault coverage. Techniques such as partial fault-dropping, two-stage compaction, and building a fault dictionary with machine word all-fill are integrated to reduce the cost of test compaction and internal communication overhead within the distributed framework. Experimental results indicate that the number of patterns generated by the distributed ATPG system integrated with the test compaction module is greatly reduced within an acceptable time overhead.

Automatic Test Pattern Generation (ATPG) is a crucial technology in the testing of digital circuits. The excessive backtracks during the ATPG process can consume considerable computational resources and deleteriously affect performance. In this study, we introduce an intelligent ATPG method based on reinforcement learning to reduce the number of backtracks and enhance performance. Specifically, the Q-learning algorithm is employed to learn an optimal backtracing strategy pattern from the ATPG data produced through path-oriented decision-making (PODEM). The learned model is then utilized to guide the backtracing decisions within the PODEM, thereby improving the performance of the ATPG process. Experimental results demonstrate that, compared with traditional heuristic strategies and the backtrace path selection strategy based on artificial neural network (ANN), the proposed method can reduce backtrack occurrences and enhance performance more effectively.

Deep neural networks have shown outstanding performance on complex tasks. Recently, various researches have been developed to pursue fast and energy-efficient deep learning accelerators. However, devices may suffer from hard defects and hardware variability during its lifetime, which poses severe challenges to deep learning accelerators. To protect edge deep learning accelerators from fault-induced failures, we leverage the adversarial deep learning technique to tailor a lightweight online fault detection method for neural network accelerator chips. The proposed Adversarial Testing scheme (AT) is a function-level testing method outcompeting conventional test in several ways: negligible run-time overhead, super sensitivity to subtle hardware variations, which reduces chip over-kills and also the unnecessary diagnosis operations. The evaluation results show that AT can accurately detect fault occurrence and ensure the normal use of deep learning accelerator during its lifetime.

Greetings and a warm welcome to the 2023 32nd IEEE Asian Test Symposium (ATS 2023)!

Number Theoretic Transform (NTT) and Secure Hash Algorithm 3 (SHA3), are the two main operators in the lattice-based Post-Quantum Cryptography (PQC) algorithms. Lattice-based PQC algorithms have different parameter settings, e.g., the length and modulus of NTT polynomials and the different hash functions. Motivated by the demands for more versatile NTT and SHA3 hardware accelerators, we implement the NTT and SHA3 designs that can accommodate to different parameters at run-time. Furthermore, to reduce the running cycles of the whole NTT operation and whole SHA3 operation including data transferring and calculation, we propose a pipelined architecture to optimize the gap between data transfer and calculation process in high-level. The designed configurable accelerators can be embedded in SoC to accelerate different lattice-based PQC algorithms efficiently. The experimental results show that our high-level pipelined and configurable NTT and SHA3 designs have good area-time efficiency. In specific, for the NTT design, our architecture is 4.1 times more area-time efficient compared with the state-of-the-art. For SHA3, our architecture is 1.4 times more area-time efficient over the existing configurable SHA3 designs.

In July 2022, the National Institute of Standards and Technology (NIST) announced its selection of four algorithms for post-quantum cryptography standardization in advance. Among these algorithms, Kyber was chosen as the only key encapsulation mechanism (KEM). In the Kyber KEM, the modular reduction function is utilized in numerous areas. We have discovered that by modeling controllable modular reduction functions, unknown modular reduction functions can be targeted. And attacks can then be constructed. Henceforth, profiling can be mounted on the target device. In this paper, we present a machine-learning-based key recovery attack on Kyber, without needing a reference device. We have effectively attacked the modular reduction function. Furthermore, this vulnerability that enables the reuse of the same function could be utilized in other attacks.

Application-specific instruction-set processors (ASIP) has been widely used to speedup specific applications based on general-purpose processor (CPU) ISA-extension and scalar/vector units customization. However, as deep neural processing unit (NPU) becomes a dominant IP in nowadays system-on-chip (SoC) designs, the rich computational and memory resource of the NPUs integrated into advanced CPUs should also be utilized to achieve an even better application performance boost than vector/scalar compute-unit customization only. In this paper, we propose APPEND, a novel framework that tries to enrich the ASIP design methodology by taking the co-designing of both NPU and RISC-V CPU into consideration. To fully utilize and customize the resources of CPU and NPU, APPEND automatically (1) identifies the NPU-compatible kernels from the target application and partition the applications in between the NPU and RISC-V CPU core, (2) based on the application performance specification, applies the necessary hardware parameterization and customization based on the RISC-V CPU and NPU templates, and also (3) generates the extended NPU instructions to accelerate the critical and compatible kernels of the target application.

In Number Theoretic Transform (NTT) operation, more than half of the active energy consumption stems from memory accesses. Here, we propose a generalized design method to improve the energy efficiency of NTT operation by considering the effect of processing element (PE) geometry and memory organization on the data flow between PEs and memory. To decrease the number of data bits that are required to be accessed from the memory, a two-dimensional (2-D) PE array architecture is used. A pair of ping-pong buffers are proposed to transposed swap the coefficients to enable a single bank of memory to be used with the 2-D PE array to reduce the average memory bit access energy without compromising the throughput. Our experimental results show that this design method can produce NTT accelerators with up to 69.8% saving in average energy consumption compared with the existing designs based on multi-bank SRAM and one-bank SRAM with one-dimensional PE array with the same number of PEs and total memory size.

NPN classification is an essential problem in the design and verification of digital circuits. Most existing works explored variable symmetries and cofactor signatures to develop their classification methods. However, cofactor signatures only consider the face characteristics of Boolean functions. In this paper, we propose a new NPN classifier using both face and point characteristics of Boolean functions, including cofactor, influence, and sensitivity. The new method brings a new perspective to the classification of Boolean functions. The classifier only needs to compute some signatures, and the equality of corresponding signatures is a prerequisite for NPN equivalence. Therefore, these signatures can be directly used for NPN classification, thus avoiding the exhaustive transformation enumeration. The experiments show that the proposed NPN classifier gains better NPN classification accuracy with comparable speed.

Physical Unclonable Function (PUF) is a hardware security primitive with broad application prospects. Variants of the arbiter PUF have been proposed to resist modeling attacks. However, their low reliability issue limits their applications. To solve the low reliability issue, this paper proposes an Online Reliability Evaluation (ORE) design for the arbiter PUF and its variants. Moreover, a corresponding machine learning method to select reliable Challenge Response Pairs (CRPs) for applications is proposed. Based on the ORE design, a small number of CRPs and their reliability levels are collected during the enrollment phase. Then they are trained to build reliability models for predicting the responses and reliability levels of other challenges. Since the ORE design does not change the security structures of the arbiter PUF and its variants, the resistance to modeling attacks of PUF designs equipped with it is maintained. Compared to the previous work that tests 100,000 times per CRP, our design is time-saving in the enrollment phase since each CRP is only tested three times for training reliability models. The proposed design is implemented under the 40nm process. Experimental results on real chips show that all the CRPs selected by our reliability models are indeed reliable for applications, verifying the effectiveness of our method.

Mixed-precision neural networks (MPNNs) that enable the use of just enough data width for a deep learning task promise significant advantages of both inference accuracy and computing overhead. FPGAs with fine-grained reconfiguration capability can adapt the processing with distinct data width and models, and hence, can theoretically unleash the potential of MPNNs. Nevertheless, commodity DPUs on FPGAs mostly emphasize generality and have limited support for MPNNs especially the ones with lower data width. In addition, primitive DSPs in FPGAs usually have much larger data width than that is required by MPNNs and haven't been sufficiently co-explored with MPNNs yet. To this end, we propose an open source MPNN accelerator design framework specifically tailored for FPGAs. In this framework, we have a systematic DSP-packing algorithm to pack multiple lower data width MACs in a single primitive DSP and enable efficient implementation of MPNNs. Meanwhile, we take DSP packing efficiency into consideration with MPNN quantization within a unified neural network architecture search (NAS) framework such that it can be aware of the DSP overhead during quantization and optimize the MPNN performance and accuracy concurrently. Finally, we have the optimized MPNN fine-tuned to a fully pipelined neural network accelerator template based on HLS and make best use of available resources for higher performance. Our experiments reveal the resulting accelerators produced by the proposed framework can achieve overwhelming advantages in terms of performance, resource utilization, and inference accuracy for MPNNs when compared with both handcrafted counterparts and prior hardware-aware neural network accelerators on FPGAs.

NPN classification has many applications in the synthesis and verification of digital circuits. The canonical-form-based method is the most common approach, designing a canonical form as representative for the NPN equivalence class first and then computing the transformation function according to the canonical form. Most works use variable symmetries and several signatures, mainly based on the cofactor, to simplify the canonical form construction and computation. This paper describes a novel canonical form and its computation algorithm by introducing Boolean influence to NPN classification, which is a basic concept in analysis of Boolean functions. We show that influence is input-negation-independent, input-permutation-dependent, and has other structural information than previous signatures for NPN classification. Therefore, it is a significant ingredient in speeding up NPN classification. Experimental results prove that influence plays an important role in reducing the transformation enumeration in computing the canonical form. Compared with the state-of-the-art algorithm implemented in ABC, our influence-aided canonical form for exact NPN classification gains up to 5.5x speedup.

Graph convolutional neural network (GCN) extends deep learning to process graph data and demonstrates superior performance. However, due to the irregularity, graphs show inconsistent patterns across different regions, which leads to distinctions in data reusability and edge processing activity, and consequently poses impacts on hardware efficiency and resource utility. Prior accelerators seldom explore the distinct patterns across graph regions and adopt a fixed strategy for the whole graph without consideration for region-specific characteristics. In this paper, we identify the inconsistent patterns of graphs and characterize the distinctions between graph regions. Then, we propose an adaptive dataflow to adapt the region-specific patterns. Third, we implement PANG, a pattern-aware accelerator that can dynamically adjust the dataflow to exploit the reusability and alleviate the frequent destination switching. Evaluated on real-world datasets, PANG achieves significant performance improvement.

Rewriting is a common procedure in logic synthesis aimed at improving the performance, power, and area (PPA) of circuits. The traditional reconvergence-driven And-Inverter Graph (AIG) rewriting method focuses solely on optimizing the reconvergence cone through Boolean algebra minimization. However, there exist opportunities to incorporate other node-rewriting algorithms that are better suited for specific cones. In this paper, we propose an adaptive reconvergence-driven AIG rewriting algorithm that combines two key techniques: multi-strategy-based AIG rewriting and strategy learning-based algorithm selection. The multi-strategy-based rewriting method expands upon the traditional approach by incorporating support for multi-node-rewriting algorithms, thus expanding the optimization space. Additionally, the strategy learning-based algorithm selection method determines the most suitable node-rewriting algorithm for a given cone. Experimental results demonstrate that our proposed method yields a significant average improvement of 5.567% in size and 5.327% in depth.

It has recently become trendy for neural network accelerators to scale from single-core to chiplet-based multichip architecture, as the growth of neural network depth and complexity are calling for the promotion of computation and memory capabilities. However, the unintended extensive inter-chip communication of chiplet-based accelerator may bottleneck the parallelism of deep learning inference, which is undesirable for many real-time applications and energy-efficient devices. Although it is imperative for novel schemes to be devised to alleviate this problem, related works are scarce. In this work, we present CampQ, a fine-grained communication-aware mixed-precision quantization method to accelerate inference parallelization by reducing the major inter-chiplet communication overhead. By leveraging the AutoML technique, CampQ is capable of determining different bit-width to activation groups according to thier transmission distances in on-package network. The experimental results show 1.4×-2.6× performance benefits and 29%-60% energy reduction over the 16-bit models for various neural networks and parallelism approaches.

Recently, complex process of production forces Integrated Circuit (IC) to be designed by third-party Electronic Design Automation (EDA) tool or outsourcing, which will create an opportunity for malicious circuits to be inserted into ICs, known as Hardware Trojan (HT). Up to now, there are still challenges in existing researches, such as dependence on the golden model, unclear position of HTs, and difficulty in unknown HT detection. In this paper, a HT detection model called BGNN-HT based on bidirectional graph neural network is proposed, which can detect HT cells by assessing the structure of its surrounding cells at gate level. BGNN-HT can precisely detect HT cells in ICs, and it does not require the golden model or manual feature extraction, which greatly reduces the difficulty of detection and can adapt to unknown HTs. Experiments are conducted on Trust-hub benchmarks including TRIT-TC and TRIT-TS to evaluate our model. The results show that when detecting unknown circuits and HTs, BGNN-HT can reach 96% True Positive Rate (TPR) and 99% True Negative Rate (TNR) in various datasets, and even 99% TPR and TNR in TRIT-TC and TRIT-TS.

The emerging Resistive RAM (ReRAM) technology significantly boosts the performance and the energy efficiency of the deep learning accelerators (DLAs) via the Computing-in-Memory (CiM) architecture. However, ReRAM-based DLA also suffers a high occurrence rate of memory faults. How to detect and protect against the faults in ReRAM devices poses great challenges to ReRAM-based DLA design. In this work, we propose RRAMedy, an in-situ fault detection and network remedy framework for ReRAM-based DLAs. With the proposed Adversarial Example Testing, which is a lifetime on-device and on-line fault detection technique, it achieves high detection coverage of both hard faults and soft faults at a low run-time cost. In addition, it employs an edge-cloud collaborative model retraining method to tolerate the detected faults by leveraging the inherent fault-adaptive capability of DNNs. Meanwhile, to enable in-situ model remedy when the cloud assistance is absent due to security or overhead issues, we propose to accelerate the fault-masking retraining process on edge devices with parallelized Knowledge Transfer. Our experimental results show that the proposed fault detection technique achieves high fault detection accuracy and delivers real-time testing performance. Meanwhile, the proposed retraining approach greatly alleviates the accuracy degradation problem and achieves excellent performance speedups over the baselines.

Soft errors in large VLSI circuits have a significant impact on computing- and memory-intensive neural network (NN) processing. Understanding the influence of soft errors on NNs is critical to protect against soft errors for reliable NN processing. Prior work mainly relies on fault simulation to analyze the influence of soft errors on NN processing. They are accurate but usually specific to limited configurations of errors and NN models due to the prohibitively slow simulation speed especially for large NN models and datasets. With the observation that the influence of soft errors propagates across a large number of neurons and accumulates as well, we propose to characterize the soft error-induced data disturbance on each neuron with a normal distribution model using the central limit theorem and develop a series of statistical models to analyze the behavior of NN models under soft errors in general. The statistical models reveal not only the correlation between soft errors and the accuracy of NN models but also how NN parameters, such as quantization and architecture affect the reliability of NNs. The proposed models are compared with fault simulations and verified comprehensively. In addition, we observe that the statistical models that characterize the soft error influence can also be utilized to predict fault simulation results in many cases and we explore the use of the proposed statistical models to accelerate fault simulations of NNs. Our experiments show that the proposed accelerated fault simulation provides almost two orders of magnitude speedup with negligible loss of simulation accuracy compared to the baseline fault simulations.

Number theoretic transform (NTT) is useful for the acceleration of polynomial multiplication, which is the main performance bottleneck in the next-generation cryptographic schemes. Different NTT-based cryptographic algorithms have different security settings. The diverse application scenarios introduce different cost-performance tradeoffs and hardware constraints. Motivated by the emerging demand for more versatile NTT hardware accelerators, we propose a new design methodology that can generate area-efficient and high-performance NTT accelerators for any length and modulus of NTT polynomials and single processing element (PE) or PE array with a varying number of layers. The proposed NTT accelerator architecture pivots on a conflict-free memory access pattern for adaptation to different combinations of security and PE array configuration parameters. The proposed memory access pattern is formally proved to be conflict-free for any parametric configurations. The criterion for read-after-write conflict without pipeline stall is also established. Our proposed design methodology can produce NTT accelerators with single PE or multilayer PE array for different polynomial size and modulus, with hardware area and computational efficiency comparable to accelerators customized for a fixed set of parameters. Our proposed methodology produces parameterized accelerator with higher scalability than the existing parameterized accelerator design. On average, the accelerators generated by our proposed method are 71.4% more area-time efficient. Up to 30.7% area-time reduction over the most area-time efficient state-of-the-art scalable NTT accelerator can be achieved for the same security parameters.

Deformable convolution networks (DCNs) proposed to address image recognition with geometric or photometric variations typically involve deformable convolution that convolves on arbitrary locations of input features. The locations change with different inputs and induce considerable dynamic and irregular memory accesses that cannot be handled by classic neural network accelerators (NNAs). Moreover, bilinear interpolation (BLI) operation, which is required to obtain deformed features in DCNs, also cannot be deployed on existing NNAs directly. Although a general purposed processor (GPP) seated along with classic NNAs can process the deformable convolution, the processing on GPP can be extremely slow due to the limited parallel computing capability and massive additional data movement. To address the problem, we develop a DCN accelerator on existing NNAs to support both the standard convolution and deformable convolution. Specifically, for the dynamic and irregular accesses in DCNs, we have both the input and output features divided into tiles and build a tile dependency table (TDT) to track the irregular tile dependency at runtime. With the TDT, we further develop an on-chip tile scheduler to handle the dynamic and irregular accesses efficiently. In addition, we propose a novel mapping strategy to enable parallel BLI processing on NNAs and apply layer fusion techniques for more energy-efficient DCN processing. According to our experiments, the proposed accelerator achieves orders of magnitude higher performance and energy efficiency compared to the typical computing architectures including ARM, ARM+TPU, and GPU with 6.6% chip area penalty to a classic NNA.

Winograd is generally utilized to optimize convolution performance and computational efficiency because of the reduced multiplication operations, but the reliability issues brought by winograd are usually overlooked. In this work, we observe the great potential of winograd convolution (WG-Conv) in improving neural network (NN) fault tolerance. Based on the observation, we evaluate WG-Conv fault tolerance comprehensively from different granularities ranging from models, layers, and operation types for the first time. Then, we explore the use of inherent fault tolerance of WG-Conv for cost-effective NN protection against soft errors. Specifically, we mainly investigate how WG-Conv can be effectively incorporated with classical fault-tolerant design approaches including triple modular redundancy (TMR), fault-aware retraining, and constrained activation functions. According to our experiments, WG-Conv can reduce the fault-tolerant design overhead by 55.77% on average without any accuracy loss compared to standard convolution (ST-Conv), and further reduce the computing overhead by 17.24% when the inherent fault tolerance of WG-Conv is considered. When it is applied on fault-tolerant NNs enhanced with fault-aware retraining and constrained activation functions, the resulting model accuracy generally shows significant improvement in the presence of various faults.

Vision transformers (ViTs) that leverage self-attention mechanism have shown superior performance on many classical vision tasks compared to convolutional neural networks (CNNs) and gain increasing popularity recently. Existing ViTs’ works mainly optimize performance and accuracy, but ViTs’ reliability issues induced by soft errors in large-scale VLSI designs have generally been overlooked. In this work, we mainly study the reliability of ViTs and investigate the vulnerability from different architecture granularities ranging from models, layers, modules, and patches for the first time. The investigation reveals that ViTs with the self-attention mechanism are generally more resilient on linear computing including general matrix–matrix multiplication (GEMM) and full connection (FC) and show a relatively even vulnerability distribution across the patches. ViTs involve more fragile non-linear computing such as softmax and GELU compared to typical CNNs. With the above observations, we propose a lightweight block-wise algorithm-based fault-tolerance (LB-ABFT) approach to protect the linear computing implemented with distinct sizes of GEMM and apply a range-based protection scheme to mitigate soft errors in non-linear computing. According to our experiments, the proposed fault-tolerant approaches enhance ViTs’ accuracy significantly with minor computing overhead in the presence of various soft errors.

Kyber is one of the four final Key Encapsulation Mechanism (KEM) competitors of the National Institute of Standards and Technology PostQuantum Cryptography standardization competition. This paper reveals the vulnerability of Kyber under a voltage template side channel attack: the modular polynomial subtraction operation in Kyber.CCAKEM.Dec. In this paper, by splicing data under different selected ciphertexts, a small number of traces are required to recover the secret key. Experiments show that the recovering accuracy of secret key achieves 100% when using 330 traces, and it still achieves 98% when only using 44 traces.

Most proposed studies focus on detecting the entire hardware Trojan (HT) in one step, which is very difficult. Since the results of most proposed method have false positive, it is still necessary to check the detection results manually in real-world application. Therefore, what we need is an accurate and efficient method to locate the core part of HTs, which can assist designers to the follow-up verification and modification. In this paper, we define several RTL features based on hardware Trojan trigger control flow characteristics, and then use these features to train a decision tree-based hardware Trojan trigger localization model. The experimental results on Trust-Hub show that our method can obtain 100% true positive rate on all benchmarks and average 98.20% true negative rate. And our method can complete feature extraction and HT trigger localization within 0.1s on average.

ReRAM-based accelerators have shown great potential in neural network acceleration via in-memory analog computing. However, high-precision analog-to-digital converters (ADCs), which are required by the ReRAM crossbars to achieve high-accuracy network model inference, play an essential role in the energy-efficiency of the accelerators. Based on the discovery that the ADC precision requirements of crossbars are different, we propose the model-aware crossbarwise ADC precision assignment and the accompanied information-lossless low-bit ADCs to reduce energy overhead without sacrificing model accuracy. In experiments, the proposed information-lossless ReRAM accelerator, InfoX, only consumes 8.97% ADC energy of the SOTA baseline with no accuracy degradation at all.

Graph-based vector search that finds best matches to user queries based on their semantic similarities using a graph data structure, becomes instrumental in data science and AI application. However, deploying graph-based vector search in production systems requires high accuracy and cost-efficiency with low latency and memory footprint, which existing work fails to offer. We present VStore, a graph-based vector search solution that collaboratively optimizes accuracy, latency, memory, and data movement on large-scale vector data based on in-storage computing. The evaluation shows that VStore exhibits significant search efficiency improvement and energy reduction while attaining accuracy over CPU, GPU, and ZipNN platforms.

Network-on-Chips (NoCs) have been viewed as a promising alternative to traditional on-chip communication architecture for the increasing number of IPs in modern chips. To support the vast design space exploration of application-specific NoC characteristics with arbitrary topologies, in this paper, we propose a fast estimation framework to predict power, performance, and area (PPA) of NoCs based on graph neural networks (GNNs). We present a general way of modeling the application and the NoC with user-defined parameters as an attributed graph, which can be learned by the GNN model. Experimental results show that on the unseen realistic applications, the proposed method achieves the accuracy of 97.36% on power estimation, 97.83% on area estimation, and improves the accuracy of the network-level and system-level performance predictor over the topology-constrained baseline method by 6.52% and 4.73% respectively.

2.5D chiplet technology is gaining popularity for the efficiency of integrating multiple heterogeneous dies or chiplets on interposers, and it is also considered an ideal option for agile silicon system design by mitigating the huge design, verification, and manufacturing overhead of monolithic SoCs. Although it significantly reduces development costs by chiplet reuse, the design and fabrication of interposers also introduce additional high non-recurring engineering (NRE) costs and development cycles which might be prohibitive for application-specific designs having low volume.

Memory sub-system including the data memory and instruction memory in a typical CGRA often takes up considerable chip area and even dominates the performance of CGRAs. Observing the common phenomenon that instruction memory in CGRAs is highly under-utilized while the data memory is over-committed or vice versa, we propose a CGRA with unified memory architecture, UM-CGRA, to enable flexible on-chip memory sharing between data and instructions. Furthermore, PEs are also augmented to share data between neighbors working in parallel. Also, an on-chip memory sharing-aware mapping algorithm is developed to unleash the potential of the proposed architecture. Our experimental results show that UM-CGRA achieves 77% performance improvement on average over the baseline CGRA given the same amount of total on-chip memory. When setting the same performance goal, UM-CGRA achieves 10.7% chip area-saving and 28.6% energy efficiency improvement on average.

To prevent private training data leakage in Federated Learning systems, we propose a novel secure aggregation scheme based on seed homomorphic pseudo-random generator (SHPRG), named SASH. SASH leverages the homomorphic property of SHPRG to simplify the masking and demasking scheme, which for each of the clients and for the server, entails a overhead linear w.r.t model size and constant w.r.t number of clients. We prove that even against worst-case colluding adversaries, SASH preserves training data privacy, while being resilient to dropouts without extra overhead. We experimentally demonstrate SASH significantly improves the efficiency to 20× over baseline, especially in the more realistic case where the numbers of clients and model size become large, and a certain percentage of clients drop out from the system.

With the rapid advancements of deep learning in the past decade, it can be foreseen that deep learning will be continuously deployed in more and more safety-critical applications such as autonomous driving and robotics. In this context, reliability turns out to be critical to the deployment of deep learning in these applications and gradually becomes a first-class citizen among the major design metrics like performance and energy efficiency. Nevertheless, the back-box deep learning models combined with the diverse underlying hardware faults make resilient deep learning extremely challenging. In this special session, we conduct a comprehensive survey of fault-tolerant deep learning design approaches with a hierarchical perspective and investigate these approaches from model layer, architecture layer, circuit layer, and cross layer respectively.

Real-time inference of deep learning models on embedded and energy-efficient devices becomes increasingly desirable with the rapid growth of artificial intelligence on edge. Specifically, to achieve superb energy-efficiency and scalability, efficient parallelization of single-pass deep neural network (DNN) inference on chip multiprocessor (CMP) architectures is urgently required by many time-sensitive applications. However, as the number of processing cores scales up and the performance of cores has grown much fast, the on-chip inter-core data movement is prone to be a performance bottleneck for computation. To remedy this problem and further improve the performance of network inference, in this work, we introduce a communication-aware DNN parallelization technique called CAP, by exploiting the elasticity and noise-tolerance of deep learning algorithms on CMP. Moreover, in the hope that the conducted studies can provide new design values for real-time neural network inference on embedded chips, we also have evaluated the proposed approach on both multi-core Neural Network Accelerators (NNA) chips and general-purpose chip-multiprocessors. Our experimental results show that the proposed CAP can achieve 1.12×-1.65× system speedups and 1.14×-2.70× energy efficiency for different neural networks while maintaining the inference accuracy, compared to baseline approaches.

In-memory computing (IMC) is recognized as one of the most promising architecture solution to realize energy-efficient neural network inference. Amongst many memory technology, resistive RAM (RRAM) is a very attractive device to implement the IMC-based neural network accelerator architecture, which is particularly suitable for power-constrained IoT systems. Due to the nature of low leakage and in-situ computing, the dynamic power consumption of dot-production operations in RRAM crossbars dominates the chip power, especially when applied to low-precision neural networks. This work investigates the correlation between the cell resistance state and the crossbar operation power, and proposes a state-aware RRAM accelerator (SARA) architecture for energy-efficient low-precision neural networks. With the proposed state-aware network training and mapping strategy, crossbars in the RRAM accelerator can perform in a lower power state. Furthermore, we also leverage the proposed RRAM accelerator architecture to reduce the power consumption of high-precision network inference with both single-level or multilevel RRAM. The evaluation results show that for binary neural networks, our design saves 40.53% RRAM computing energy on average over the baseline. For high precision neural networks, the proposed method reduces 11.67% computing energy on average without any accuracy loss.

Hardware faults on the regular 2-D computing array of a typical deep learning accelerator (DLA) can lead to dramatic prediction accuracy loss. Prior redundancy design approaches typically have each homogeneous redundant processing element (PE) to mitigate faulty PEs for a limited region of the 2-D computing array rather than the entire computing array to avoid the excessive hardware overhead. However, they fail to recover the computing array when the number of faulty PEs in any region exceeds the number of redundant PEs in the same region. The mismatch problem deteriorates when the fault injection rate rises and the faults are unevenly distributed. To address the problem, we propose a hybrid computing architecture (HyCA) for fault-tolerant DLAs. It has a set of dot-production processing units (DPPUs) to recompute all the operations that are mapped to the faulty PEs despite the faulty PE locations. According to our experiments, HyCA shows significantly higher reliability, scalability, and performance with less chip area penalty when compared to the conventional redundancy approaches. Moreover, by taking advantage of the flexible recomputing, HyCA can also be utilized to scan the entire 2-D computing array and detect the faulty PEs effectively at runtime.

Due to the nonvolatility nature of resistive RAM (ReRAM), dynamic operations in the arrays contribute to a much larger portion of power in ReRAM-based neural networks than static power. To reduce the dynamic power ofin-situoperations with neural parameters, precision-tuning is considered a viable approach of approximate computing to tradeoff excessive computation exactness for power and efficiency gains. However, the switching overhead of precision tuning in hardware severely impacts its effectiveness when the systems need to quickly react to the change of environment, user constraint or input quality. This work for the first time investigates the feasibility of agile precision tuning for neural network accelerators to benefit from approximate computing. The proposed computing in memory (CiM) CNN accelerators fully utilize the normally off characteristics of memristor crossbars to achieve instant network precision tuning without worrying about the model reloading penalty. The ReRAM-based accelerator, with the proposed neural parameter mapping policy and the novel mixed-model training method, induces negligible precision-switching latency and power consumption when compared with traditional variable precision accelerators. In evaluation with state-of-the-art workloads, the proposed ReRAM deep learning and neural network architecture saves 58.3%–62.47% area overhead over the baseline design. We also leverage the proposed ReRAM accelerator architecture to build a novel always-on key-word spotting (KWS) system. The KWS design can switch between different precision modes to capture the relevant sound with high accuracy. The experimental results show the precision-adjustable KWS architecture saves considerable operating energy when fed with realistic test-sets of audio data.

Previous neural network accelerators tailored to video analysis only accept data of RGB/YUV domain, requiring decompressing the video that are often compressed before transmitted from the edge sensors. A compressed video processing accelerator can alleviate the decoding overhead, and gain performance speedup by operating on more compact input data. This work proposes a novel deep learning accelerator architecture, Alchemist, which is able to predict results directly from the compressed video bitstream instead of reconstructing the full RGB images. By utilizing the metadata of motion vector and critical blocks extracted from bitstreams, Alchemist contributes to a remarkable performance speedup of 5x with negligible accuracy loss. Nevertheless, we still find that the original compressed video coded by standard algorithms such as H.264 is not suitable to be directly manipulated, due to diverse compressed structures. Although obviating the requirement to recover all RGB frames, the accelerator must parse the entire compressed video bitstream to locate reference frames and extract useful metadata. If we combine the video codec with the proposed compressed video analysis, additional optimizations can be obtained. Therefore, to cope with the mismatch between current video coding algorithms, such as H.264 and neural network-based video analysis, we propose a specialized coding strategy to generate compressed video bitstreams more suitable for transmission and analysis, which further simplifies the decoding stage of video analysis and is capable of achieving significant storage reduction.

Carbon nanotube field-effect transistors (CNFETs) emerge as a promising alternative to CMOS transistors for the much higher speed and energy efficiency, which makes the technology particularly suitable for building the energy-hungry last-level cache (LLC). However, the process variations (PVs) in CNFET caused by the imperfect fabrication lead to large timing variations, and the worst case timing dramatically limits the LLC operation speed. Particularly, we observe that the CNFET-based cache latency distribution is closely related to the LLC layouts. For the two typical LLC layouts that have the CNT growth direction aligned to the cache way direction and cache set direction, respectively, we proposed variation-aware set aligned (VASA) cache and variation-aware way aligned (VAWA) cache in combination with corresponding cache optimizations, such as data shuffling and page mapping to enable low-latency cache for frequently used data. According to our experiments, the optimized LLC reduces the average access latency by 32% and 45% compared to the baseline designs on the two different CNFET layouts, respectively, while it improves the overall performance by 6% and 9%, and reduces the energy consumption by 4% and 8%, respectively. In addition, with both the architecture-induced latency variation and PV-incurred latency variation considered in a unified model, we extended the VAWA and VASA cache designs for the CNFET-based NUCA, and the proposed NUCA achieves both significant performance improvement and energy saving compared to the straightforward variation-aware NUCA.

This article presents a bounded model checking (BMC)-based temperature-aware software-based self-testing (SBST) technique to test worst case delay faults within the highest temperature range. The BMC-based SBST method first defines the sequential constraint. It develops a sequentially constrained automatic test pattern generation (ATPG) to ensure that the generated delay test patterns can emerge in functional mode. It then uses the processor’s multiple-level information to reduce the model complexity, avoid aborts due to time-outs during the BMC process, and generate test programs automatically. A temperature-aware SBST method has then been developed to ensure that the test temperature is within the specified range and test the worst case delays under high temperature. Experimental results demonstrate that the proposed technique achieves an extremely high coverage for delay faults and effectively avoids yield loss caused by the overtesting problem. Its test quality also outperforms that of the existing methods. The generated SBST programs are successful and efficient in testing worst case delay faults under high temperature.

Hardware Trojan has always been a major security threat to the integrated circuit industry. In this article, we propose a novel circuit gate embedding method called SeGa, which extracts the “semantic information” of gates in the netlist. The feature vectors that representing each type of gate extracted by SeGa are used as the inputs to the neural network classification model to detect Trojans. The experimental results on TRIT-TC benchmark show that SeGa can improve the performance of the neural network classification model to detect the Trojan gate sequence.

Graph is widely utilized as a key data structure in many applications like social network and recommendation systems. However, real-world graph construction typically involves massive random memory accesses and distance calculation, resulting in considerable processing time and energy consumptions on CPUs and GPUs. In this work, we present GCiM, a specialized processing-in-memory architecture for efficient graph construction and update. By directly deploying the computing units on the logic layer of the 3D stacked memory, GCiM benefits from memory-level parallelism and further improves the memory access efficiency with both optimized processing ordering and data layout. According to our experiments, GCiM shows 634.64X and 53.29X speedup while consuming 1470.7X and 442.56X less energy compared to CPU and GPU respectively.

ReRAM-based Computing-in-Memory (CiM) architecture has been considered an ideal solution to neural networks, by conducting in-situ matrix multiplications without moving the neural parameters from memory cells. However, we found that keeping the parameters static in ReRAM cells, i.e. weight-static processing, is not the sole choice to implement emerging graph neural networks (GNNs) that operate on the input of ultra large graphs. Therefore, we propose TARe, a Task-Adaptive CiM architecture that supports multiple different in-situ computing modes for Graph Learning. With the proposed novel hybrid in-situ computing architecture, TARe achieves 451.98× speedup on average over the baseline in SOTA GNN workloads.

Pixel-level data redundancy in video induces additional memory and computing overhead when neural networks are employed to mine spatiotemporal patterns, e.g. activity and event labels from video streams. This work proposes PixelSieve, to enable highly efficient CNN-based activity analysis directly from video data in compressed formats. Instead of recovering original RGB frames from compressed video, PixelSieve utilizes the built-in metadata in compressed video streams to distill only the critical pixels that render relevant spatiotemporal features, and then conducts efficient CNN inference with the condensed inputs. PixelSieve removes the overhead of video decoding and significantly improves the performance of CNN-based video analysis by 4.5x on average.

Static learning is a learning algorithm for finding additional implicit implications between gates in a netlist. In automatic test pattern generation (ATPG) the learned implications help recognize conflicts and redundancies early, and thus greatly improve the performance of ATPG. Though ATPG can further benefit from multiple runs of incremental or dynamic learning, it is only feasible when the learning process is fast enough. In the paper, we study speeding up static learning through parallelization on heterogeneous computing platform, which includes multi-core microprocessors (CPUs), and graphics processing units (GPUs). We discuss the advantages and limitations in each of these architectures. With their specific features in mind, we propose two different parallelization strategies that are tailored to multi-core CPUs and GPUs. Speedup and performance scalability of the two proposed parallel algorithms are analyzed. As far as we know, this is the first time that parallel static learning is studied in the literature.

This special session focuses on test for artificial intelligence (AI) chips, with important issues from design for test (DFT) to on-line testing. The first talk discusses different DFT implementations and their tradeoffs as well as test access and configuration infrastructure for AI chips with many cores. The second talk discusses low-cost on-line fault detection and hardware salvaging techniques for neural network processors. The last talk gives case studies for testing industrial AI SOC chips, with an emphasis on the automatic test pattern generation (ATPG) methodology.

Graph neural networks (GNNs) emerge as a powerful approach to process non-euclidean data structures and have been proved powerful in various application domains such as social networks and e-commerce. While such graph data maintained in real-world systems can be extremely large and sparse, thus employing GNNs to deal with them requires substantial computational and memory overhead, which induces considerable energy and resource cost on CPUs and GPUs. In this article, we present a specialized accelerator architecture, EnGN, to enable high-throughput and energy-efficient processing of large-scale GNNs. The proposed EnGN is designed to accelerate the three key stages of GNN propagation, which is abstracted as common computing patterns shared by typical GNNs. To support the key stages simultaneously, we propose the ring-edge-reduce(RER) dataflow that tames the poor locality of sparsely-and-randomly connected vertices, and the RER PE-array to practice RER dataflow. In addition, we utilize a graph tiling strategy to fit large graphs into EnGN and make good use of the hierarchical on-chip buffers through adaptive computation reordering and tile scheduling. Overall, EnGN achieves performance speedup by 1802.9X, 19.75X, and 2.97X and energy efficiency by 1326.35X, 304.43X, and 6.2X on average compared to CPU, GPU, and a state-of-the-art GCN accelerator HyGCN, respectively.

3D convolutional neural networks (CNNs) are gaining increasing popularity in the area of video-based action/activity analysis. Compared to 2D convolutions that share the filters in a 2D spatial domain, 3D convolutions further reuse filters in the temporal dimension to capture temporal-domain features in the video. How to exploit the data locality in the temporal dimension directly impacts the energy efficiency of specialized architectures for 3D CNN inference. Prior works on specialized 3D-CNN accelerators employ additional on-chip memories and multicluster architecture to reuse data among the process element (PE) arrays, which is very expensive for low-power chip implementation. Instead of harvesting in-memory data locality, we propose the architecture of systolic cube to exploit the spatial and temporal localities in 3D CNNs, which moves the reusable data in-between PEs connected via a 3D-cube network-on-chip. Furthermore, due to the existence of visual feature reappearance in the temporal domain, there exists a considerable portion of repetitive pixels and activations among the feature maps captured at adjacent time slots. To eliminate such temporal redundancy in 3D CNNs, the proposed accelerator architecture is equipped with a redundancy detection and elimination mechanism, capable of skipping the computations with the same activations and parameters when reusing the convolutional filters along the temporal dimension. In our evaluation, the experimental results show that the systolic-cube architecture contributes to a considerable energy-efficiency boost for state-of-the-art activity-recognition benchmarks and datasets.

Artificial Intelligence of Things (AIoT) processors fabricated with newer technology nodes suffer rising soft errors due to the shrinking transistor sizes and lower power supply. Soft errors on the AIoT processors particularly the deep learning accelerators (DLAs) with massive computing may cause substantial computing errors. These computing errors are difficult to be captured by the conventional training on general-purposed processors such as CPUs and GPUs in a server. Applying the offline trained neural network models to the edge accelerators with errors directly may lead to considerable prediction accuracy loss. To address the problem, we propose a remote retraining framework (R2F) for remote AIoT processors with computing errors. It takes the remote AIoT processor with soft errors in the training loop such that the on-site computing errors can be learned with the application data on the server and the retrained models can be resilient to the soft errors. Meanwhile, we propose an optimized partial triple modular redundancy (TMR) strategy to enhance the retraining. According to our experiments, R2F enables elastic design tradeoffs between the model accuracy and the performance penalty. The top-5 model accuracy can be improved by 1.93%–13.73% with 0%–200% performance penalty at high fault error rate. In addition, we notice that the retraining requires massive data transmission and even dominates the training time and propose a sparse increment compression approach for the data transmission optimization, which reduces the retraining time by 38%–88% on average with negligible accuracy loss over straightforward remote retraining.

Prior works typically conducted the fault analysis of neural network accelerator computing arrays with simulation and focused on the prediction accuracy loss of the neural network models. There is still a lack of systematic fault analysis of the neural network acceleration system that considers both the accuracy degradation and system exceptions, such as system stall and running overtime. To that end, we implemented a representative neural network accelerator and corresponding fault injection modules on a Xilinx ARM-FPGA platform and evaluated the reliability of the system under different fault injection rates when a series of typical neural network models are deployed on the neural network acceleration system. The entire fault injection and reliability evaluation system is open-sourced on GitHub. With comprehensive experiments on the system, we identify the system exceptions based on the various abnormal behaviors of the FPGA-based neural network acceleration system and analyze the underlying reasons. Particularly, we find that the probability of the system exceptions dominates the reliability of the system. The faults also incur accuracy degradation of the neural network models, but the influence depends on the applications of the models and can vary greatly. In addition, we also evaluated the use of conventional triple modular redundancy (TMR) and demonstrated the challenge of TMR with both experiments and analytical models, which may shed light on the reliability design of the FPGA-based neural network acceleration system.

The increasing hardware failures caused by the shrinking semiconductor technologies pose substantial influence on the neural accelerators and improving the resilience of the neural network execution becomes a great design challenge especially to mission-critical applications such as self-driving and medical diagnose. The reliability analysis of the neural network execution is a key step to understand the influence of the hardware failures, and thus is highly demanded. Prior works typically conducted the fault analysis of neural network accelerators with simulation and concentrated on the prediction accuracy loss of the models. There is still a lack of systematic fault analysis of the neural network acceleration system that considers both the accuracy degradation and system exceptions such as system stall and early termination.In this work, we implemented a representative neural network accelerator and fault injection modules on a Xilinx ARM-FPGA platform and conducted fault analysis of the system using four typical neural network models. We had the system open-sourced on github. With comprehensive experiments, we identify the system exceptions based on the various abnormal behaviours of the FPGA-based neural network acceleration system and analyze the underlying reasons. Particularly, we find that the probability of the system exceptions dominates the reliability of the system and they are mainly caused by faults in the DMA, control unit and instruction memory of the accelerators. In addition, faults in these components also incur moderate accuracy degradation of the neural network models other than the system exceptions. Thus, these components are the most fragile part of the accelerators and need to be hardened for reliable neural network execution.

The development of integrated circuit technology is accompanied by potential threats. Malicious modifications to circuits, known as hardware Trojans, are major security concerns. This paper gives a survey of hardware Trojan detection methods towards gate-level netlists. The detection methods are divided into search-based, threshold-based, and machine learning-based ones. This paper compares and analyzes existing works from aspects of feature selection, data balancing techniques, classification criterion, detection range. The experimental results are also selected for comparison.

Public key cryptography is important in the global communication digital infrastructure. However, the emergence of quantum computer and Shor algorithm has greatly threatened the security of public key cryptography. The CRYSTALS-KYBER, as a lattice-based KEM algorithm, passed three rounds of a global solicitation for post-quantum cryptography algorithms held by the National Institute of Standards and Technology (NIST). This paper explores the implementation and optimization space of hardware design according to CRYSTALS-KYBER algorithm. We analyze its software code and try different strategies to optimize the hardware implementation, and conduct comparative analysis in terms of area and speed. The experimental results show that the performance can be greatly improved by moderately optimizing the loops. In comparison with optimal results of the work [12], our optimizations improve the performance by up to 74.6% for encapsulation algorithm and 54.4% for decapsulation algorithm.

Resistive RAM (ReRAM) is a promising device to realize the Computing in Memory (CiM) architecture, suitable for power-constrained IoT systems. Because of low leakage, the dot-production operations in ReRAM crossbars dominate the chip power, especially when implementing low-precision neural networks. This work investigates the correlation between the cell resistance state and the crossbar operation power, and proposes a State-Aware ReRAM Accelerator (SARA) architecture for energy-efficient neural networks. With the proposed state-aware network training and mapping strategy, crossbars in the ReRAM accelerator can perform in a lower-power state. The evaluation shows that our design reduces 47% energy over the baseline without compromising the network accuracy.

Previous neural network accelerators tailored to video analysis only accept data of RGB/YUV domain, requiring decompressing the video that are often compressed before transmitted from the edge sensors. A compressed video processing accelerator can remove the decoding overhead, and gain performance speedup by operating on more compact input data. This work proposes a novel deep learning accelerator architecture, Alchemist, which predicts results directly from the compressed video bitstream instead of reconstructing the full RGB images. By utilizing the metadata of motion vector and critical blocks extracted from bitstream, Alchemist contributes to remarkable performance speedup of 5x with negligible accuracy loss.

Carbon Nanotubu field-effect transistor (CNFET) that promises both higher clock speed and energy efficiency becomes an attractive alternative to the conventional power-hungry CMOS cache. We observe that the CNFET-based cache constructed with typical SRAM cells has distinct energy consumption when reading/writing 0 and 1 from/to it. For instance, the energy consumption of writing 1 to an SRAM cell is almost 10X higher than writing 0. With this observation, we propose an energy-efficient cache design called CNT-Cache to take advantage of this feature. It predicts the cache line access pattern based on the latest cache line access history. On top of the prediction, it decides the optimal cache line encoding to match the cache operation preferences at runtime. According to our experiments on a set of benchmark programs, the optimized CNFET-based D-Cache reduces the dynamic power consumption by 22.2% on average compared to the baseline CNFET cache.

This paper explores an intrusion mechanism to microprocessors using illegal instructions, namely hidden instruction Trojan (HIT). It uses a low-probability sequence consisting of normal instructions as a boot sequence, followed by an illegal instruction to trigger the Trojan. The payload is a hidden interrupt to force the program counter to a specific address. Hence the program at the address has the super privileges. Meanwhile, we use integer programming to minimize the trigger probability of HIT within a given area overhead. The experimental results demonstrate that HIT has an extremely low trigger probability and can survive from the detection of the existing test methods.

Processing-in-Memory (PIM) or Near-Data Processing has been recognized as the most potential solution to resolve the ever-aggravating memory wall especially as the thrive of memory-intensive scale-out workloads such as graph computing and data analytics. However, when the future computing system becomes more and more likely to adopt PIM architectures as a type of the storage and processing component, there is a lack of literature and research work on the general scheduling framework with the emerging heterogeneous system except for some ad-hoc task partitioning methods with specialized PIM designs. This work is the first to propose a formalized model to quantitatively describe the multi-task scheduling problem in PIM+CPU platform without loss of generality, and also an optimized task mapping-and-scheduling algorithm to boost the hardware utility for these novel heterogeneous systems. The proposed scheduling framework is fully aware of the data access bandwidth and processing capability distinction between the CPU and PIM devices, and also the implications of task mapping on the bandwidth contention, data communication intensity and hardware utility for the concurrent workloads. Experimental results show that, compared to the traditional scheduling algorithm for heterogeneous system, the proposed method is able to improve the system performance by over 10% and the energy efficiency by almost 10% for multi-core scale-out applications.

In many realistic applications, the collected inputs of DNN face a big challenge: perturbations. Although the perturbations are imperceptible, they may cause incorrect prediction results. This paper proposes prediction stability to quantitatively evaluate whether the prediction result of an input is instable and easy to be perturbed. Prediction stability can guide the DNN system to cope with the situation where the prediction result has a high confidence but with a low stability. Experimental result shows that, using the proposed metrics to evaluate the stability of prediction results, over 99.8 cases are consistent with the real stable/instable conditions.

Building FPGA-based graph learning accelerators is very time-consuming due to the low-level RTL programming and the complicated design flow of FPGA development. It also requires the architecture and hardware expertise from the Graph Neural Network (GNN) application developers to tailor efficient accelerator designs on FPGAs. This work proposes an automation framework, DeepBurning-GL, which is compatible with state-of-the-art graph learning frameworks such as Deep Graph Library so that the developers can easily generate application-specific GNN accelerators from the software-described models. First, DeepBurning-GL employs a GNN performance analyzer to locate the performance bottleneck of specific GNN applications and decide the major design architectures and parameters that meet the user-specified constraints. Second, DeepBurning-GL provides a series of pre-built design templates such as computing templates and memory templates, which can be parameterized and fused to generate the final accelerator design. It also includes an optimizer that conducts automatic optimization by adjusting the accelerator architectural parameters. In evaluation, we use DeepBurning-GL to generate customized accelerators on three different FPGA platforms for various GNN models and workloads. The experimental results show that the generated accelerators achieve 179.4X and 40.1X energy-efficiency boost over the CPU and GPU solutions on average and deliver a 6.28X speedup and 6.73X energy-efficiency improvement on average compared to the latest GNN accelerator HyGCN on Alveo U50.

Deep Reinforcement Learning (DRL) is substantially resource-consuming, and it requires large-scale distributed computing-nodes to learn complicated tasks, like videogame and Go play. This work attempts to down-scale a distributed DRL system into a specialized many-core chip and achieve energy-efficient on-chip DRL. With the customized Network-on-Chip that handles the communication of on-chip data and control-signals, we proposed a Synchronous Asynchronous RL Architecture (SARLA) and the according many-core chip that completely avoids the unnecessary data duplication and synchronization activities in multi-node RL systems. In evaluation, the SARLA system achieves considerable energy-efficiency boost over the GPU-based implementations for typical DRL workloads built with OpenAI-gym.

Emerging memristor-based architectures are promising for data-intensive applications as these can enhance the computation efficiency, solve the data transfer bottleneck and at the same time deliver high energy efficiency using their normally-off/instant-on attributes. However, their storing devices are more susceptible to manufacturing defects compared to the traditional memory technologies because they are fabricated with new materials and require different manufacturing processes. Hence, in order to ensure correct functionalities for these technologies, it is necessary to have accurate fault modeling as well as proper test methodologies with high test coverage. In this paper, we propose technology specific cell-level defect modeling, accurate fault analysis and yield improvement solutions for memristor-based memory as well as Computation-In-Memory (CIM) architectures. Our overall contributions cover three abstraction levels, namely, device, architecture and system. First, we propose a device-aware test methodology in which we have introduced a key device-level characteristic to develop accurate defect model. Second, we demonstrate a yield analysis framework for memristor arrays considering reliability and permanent faults due to parametric variations and explore fault-tolerant solutions. Third, a lightweight on-line test and repair schemes is proposed for emerging CIM devices in machine learning applications.

With the rapid development of deep learning techniques, the security issue for Neural Network (NN) systems has emerged as an urgent and severe problem. Hardware Trojan attack is one of the threatens, which provides attackers backdoors to control the prediction results of NN systems. This paper proposes a sequence triggered hardware Trojan. Normal images but with specific sequence are used to trigger the hardware Trojan and let attackers fully control the prediction results. This kind of trigger is not only robust to image pre-processing, but also unrecognizable by human beings. In comparison with existing hardware Trojan design, it is more practical and less hardware overhead. The experiments on MNIST, CIFAR100, and ISLVRC show that the proposed hardware Trojan is rarely triggered in normal working status while the hardware cost is reduced by 19X.

Scan-based side-channel attack has become a new threat to cryptographic chips. Many countermeasures are proposed to safeguard scan design against the scan-based attacks. Among which, the methods based on lock and key scheme present more effective and popular. In this paper, we propose a new lock and key scheme which adopts physical unclonable function (PUF) design to generate a unique key for each design. The uniqueness of PUF enables each chip taped out from one mask to possess a different golden key. Once the PUF is invoked for the first time, the PUF response will be hardcoded into the design so that even the environment changes, the PUF-based key maintains. The proposed secure scan design with PUF-based key can protect the cryptographic chips against all known scan-based side-channel attacks while incurring negligible overhead.

Design-for-testability (DfT) techniques have been widely adopted into the integrated circuit (IC) design process to facilitate manufacture testing. The scan-based DfT architecture is a popular DfT feature that provides full testability for the circuit under test. However, this turns into a double-edged sword for some ICs such as cryptographic chips because scan design could be used as a side channel to access the intermediate encryption results, with which the cipher key can be deduced easily. To resist such scan-based side-channel attacks, many countermeasures are proposed to obfuscate the test data in scan chain. Unfortunately, most of the obfuscation logic, due to the performance and resource constraints, cannot be proven to be irreversible and hence suffers a high risk for the correct test data being derived from the obfuscated output. In this article, we propose to utilize the cryptographic hash module for some post-processing of the test responses in order to secure the scan design. Our approach has several clear advantages over existing ones. First, the security is guaranteed based on the preimage resistance of cryptographic hash function and the introduced salt information and data collection scheme. Second, it incurs low overhead because the hash module is normally available on the IC, in particular, those where security is important. Finally, full testability is retained as we are not modifying any test input. We present the implementation of the proposed secure design, report the experimental results, and demonstrate that our approach can resist all known scan-based side-channel attacks with negligible overhead while maintaining the testability and other testing performances.

General-purpose computing on graphics processing units (GPGPUs) is a programming model that uses graphics cards to perform computations traditionally done by CPU. It began to become practical with the advent of programmable shaders and floating-point support on GPU in around 2001. The spread of GPGPU has been accelerated with introduction of CUDA from NVIDIA in 2006 and later OpenCL in 2009. Nowadays GPGPU is widely deployed in various applications, such as data mining, artificial intelligence, and many scientific computations. GPGPU seemingly promises immense parallelism with massive concurrent cores, and thus much shorter run times. This is true for algorithms that bear intrinsic data and task parallelism, such as image and video processing. For an ATPG system where some algorithms are sequential in nature, the speedup is not easy to achieve in the real world. Flaws in setting up speedup evaluation can lead to false promises. Will GPGPU-based ATPG system become a reality? Or it is just a myth. In this paper, we try to provide an answer by surveying state-of-the-art works and by analyzing practical aspects of today's industrial designs.

Inference efficiency is the predominant design consideration for modern machine learning accelerators. The ability of executing multiply-and-accumulate (MAC) significantly impacts the throughput and energy consumption during inference. However, MAC operation suffers from significant ineffectual computations that severely undermines the inference efficiency and must be appropriately handled by the accelerator. The ineffectual computations are manifested in two ways: first, zero values as the input operands of the multiplier, waste time and energy but contribute nothing to the model inference; second, zero bits in nonzero values occupy a large portion of multiplication time but are useless to the final result. In this article, we propose an ineffectual-free yet cost-effective computing architecture, called split-and-accumulate (SAC) with two essential bit detection mechanisms to address these intractable problems in tandem. It replaces the conventional MAC operation in the accelerator by only manipulating the essential bits in the parameters (weights) to accomplish the partial sum computation. Besides, it also eliminates multiplications without any accuracy loss, and supports a wide range of precision configurations. Based on SAC, we propose an accelerator family called Tetris and demonstrate its application in accelerating state-of-the-art deep learning models. Tetris includes two implementations designed for either high performance (i.e., cloud applications) or low power consumption (i.e., edge devices), respectively, contingent to its built-in essential bit detection mechanism. We evaluate our design with Vivado HLS platform and achieve up to 6.96× performance enhancement, and up to 55.1× energy efficiency improvement over conventional accelerator designs.

Generating functional tests for processors has been a challenging problem for decades in the very large-scale integration testing field. This paper presents a method that generates software-based self-tests by leveraging bounded model checking (BMC) techniques and targeting, for the first time, out-of-order [out-of-order execution (OOE)] superscalar processors. To combat the state-space explosion associated with BMC, the proposed method starts by combining module-level abstraction-refinement with slicing to reduce the size of the model under verification. Next, an off-the-shelf BMC solver is used on the obtained extended finite-state machines to generate the leading sequences that are necessary to excite internal processor functions. Finally, constrained automatic test-pattern generation is used to cover all structural faults within every function excited by the obtained leading sequences. Experimental results show that the proposed method leads to extremely high fault coverage on the critical components corresponding to OOE operations in functional mode. The method therefore helps in tackling the over-testing problem that is inherent to the full-scan test approach.

With the advancements of neural networks, customized accelerators are increasingly adopted in massive AI applications. To gain higher energy efficiency or performance, many hardware design optimizations such as near-threshold logic or overclocking can be utilized. In these cases, computing errors may happen and the computing errors are difficult to be captured by conventional training on general purposed processors (GPPs). Applying the offline trained neural network models to the accelerators with errors directly may lead to considerable prediction accuracy loss. To address this problem, we explore the resilience of neural network models and relax the accelerator design constraints to enable aggressive design options. First of all, we propose to train the neural network models using the accelerators' forward computing results such that the models can learn both the data and the computing errors. In addition, we observe that some of the neural network layers are more sensitive to the computing errors. With this observation, we schedule the most sensitive layer to the attached GPP to reduce the negative influence of the computing errors. According to the experiments, the neural network models obtained from the proposed training outperform the original models significantly when the CNN accelerators are affected by computing errors.

This work is oriented at the edge computing scenario that terminal deep learning accelerators use pre-trained neural network models distributed from third-party providers (e.g. from data center clouds) to process the private data instead of sending it to the cloud. In this scenario, the network model is exposed to the risk of being attacked in the unverified devices if the parameters and hyper-parameters are transmitted and processed in an unencrypted way. Our work tackles this security problem by using on-chip memory Physical Unclonable Functions (PUFs) and Processing-In-Memory (PIM). We allow the model execution only on authorized devices and protect the model from white-box attacks, black-box attacks and model tampering attacks. The proposed PUFs-and-PIM based Protection method for neural Models (P3M), can utilize unstable PUFs to protect the neural models in edge deep learning accelerators with negligible performance overhead. The experimental results show considerable performance improvement over two state-of-the-art solutions we evaluated.

Carbon Nanotube field-effect transistors (CNFET) emerge as a promising alternative to the conventional CMOS for the much higher speed and power efficiency. It is particularly suitable for building the power-hungry last level cache (LLC). However, the process variation (PV) in CNFET substantially affects the operation stability and thus the worst-case timing, which limits the LLC operation frequency dramatically given a fully synchronous design. To address this problem, we developed a variation-aware cache such that each part of the cache can run at its optimal frequency and the overall cache performance can be improved significantly.

Hardware Trojan (HT) has paid more and more attention to the academia and industry because of its significant potential threat. In this paper, we propose a novel approach, named GramsDet, to detect HT through capturing suspicious circuit connection structure using recurrent neural network. GramsDet considers that HT usually be inserted into the regions with low transition probability, so the circuit fragments associated with HT should have special connection structures. GramsDet models the target circuit using n-gram circuit segmentation technique, and implements the "gate embedding" by the order-sensitive co-occurrence matrix. Then, a stacked long short-term memory network is designed to build a robust HT detection model. The experimental results on different benchmarks show that GramsDet can detect effectively Trojan logic without the "Golden model" of the circuit under detection (CUD).

Prior research on energy-efficient Convolutional Neural Network (CNN) inference accelerators mostly focus on exploiting the model sparsity, i.e., zero patterns in weight and activations, to reduce the on-chip storage and computation overhead. In this work, we found in addition to zero patterns, a larger group of repetitive patterns and values exists in the working-set of CNN inference task, which is defined as computation redundancy and induces unnecessary performance and storage overhead in CNN accelerators. Based on this observation, we proposed a redundancy-free architecture that detects and eliminates the repetitive computation and storage patterns in CNN for more efficient network inference. The architecture consists of two parts: the off-line parameter analyzer that extracts the repetitive patterns in the 3D tensor of parameters, and the dataflow accelerator. The proposed accelerator at first preprocesses the weight patterns and the dynamically generated activations, and then cache these intermediate results in special P2-cache banks for further usage in convolution or full-connection stage. It is evaluated in experiments that the proposed Cavoluche architecture removes up to 89% of the repetitive operations from the layer inference process and reduce 77% of on-chip storage space to store both redundancy-free weight and activations. It is seen in experiments that the implementation of Cavoluche outperforms the state-of-the-art mobile GPGPU in both performance and energy-efficiency. When compared to the latest sparsity base accelerators, Cavoluche also achieves better operation elimination effects.

3D convolutional neural networks (CNN) are gaining popularity in action/activity analysis. Compared to 2D convolutions that share the filters in 2D spatial domain, 3D convolutions further reuse filters in the temporal dimension to capture time-domain features. Prior works on specialized 3D-CNN accelerators employ additional on-chip memories and multi-cluster architecture to reuse data among the process element (PE) arrays, which is too expensive for low-power chips. Instead of harvesting in-memory locality, we propose a 3D systolic cube architecture to exploit the spatial-and-temporal localities of 3D CNNs, which moves the reusable data in-between PEs connected via a 3D-cube Network-on-Chip. Evaluation shows that systolic-cube contributes to considerable energy-efficiency boost for activity-recognition benchmarks.

Accelerating deep neural networks on resource-constrained embedded devices is becoming increasingly important for real-time applications. However, in contrast to the intensive research works on specialized neural network inference architectures, there is a lack of study on the acceleration and parallelization of deep learning inference on embedded chip-multiprocessor architectures, which are favored by many real-time applications for superb energy-efficiency and scalability. In this work, we investigate the strategies of parallelizing single-pass deep neural network inference on embedded on-chip multi-core accelerators. These methods exploit the elasticity and noise-tolerance features of deep learning algorithms to circumvent the bottleneck of on-chip inter-core data moving and reduce the communication overhead aggravated as the core number scales up. The experimental results show that the communication-aware sparsified parallelization method improves the system performance by 1.6×−1.1× and achieves 4×−1.6× better interconnects energy efficiency for different neural networks.

Compute-centric architecture is suffering from the data moving overhead caused by memory wall, particularly for applications like large-scale data analysis based on deep learning technology. In this work, we designed an energy-efficient In-SSD Deep Learning Accelerator, InS-DLA, for Near-Data-Processing. InS-DLA directly operates on NAND Flash inside the Open Channel Solid-State-Drive where the target data are stored, eliminating the power and performance overhead caused by data movement. Experimental results reveal that the InS-DLA based FPGA prototype reduces energy consumption by 95.82% and 59.23%, compared to conventional CPU and GPU based deep learning systems.

Precision-tuning is a popular approach of approximate computing to trade-off excessive computation exactness for power and efficiency gains. Particularly, it has been proved useful to reduce the computation and memory overhead for the deep neural networks on embedded and IoT usage. However, the switching overhead of precision tuning in hardware severely impacts its applicability and effectiveness to save more energy by quickly reacting to the change of environment, user constraint or input quality. This work for the first time investigates the feasibility of agile and cost-free precision tuning for neural network accelerators to benefit from approximate computing. The proposed Processing in Memory (PIM) CNN accelerators fully utilize the normally-off characteristics of memristor crossbars to achieve instant network precision tuning without worrying about the model reloading penalty. The ReRAM-based accelerator, with the proposed neural parameter mapping policy and the novel mixed-model training method, involves negligible precision-switching latency and power consumption compared with traditional variable precision accelerators. The proposed mixed-model training perfectly unifies the neural models of different precision into a single ReRAM array without compromising the accuracy, and the ReRAM accelerator could save 58.3%-62.47% area overhead compared with conventional designs that have to program multiple independent models into ReRAM arrays for precision tuning.

The emerging memristor technology is considered a promising solution to the edge-oriented deep learning and neuromorphic processor chips because it enables power-efficient Computing-in-Memory (CiM) and normally-off architecture simultaneously. However, as the analog nature and the immature nano-scale fabrication technology, the memristive cells suffer from manufacturing defects, process variations and aging-induced variations, which may incur system and function failures in applications. How to detect and rescue from the permanent and soft faults poses a significant challenge to the edge ReRAM-based deep learning or neuromorphic chips. In this work, we propose an edge-cloud collaborative framework, RRAMedy, to achieve in-situ fault detection and network remedy for memristor-based neural accelerators. In this framework, we present Adversarial Example Testing, a lifetime on-device fault detection technique, which can accurately detect defected cells and memristor soft faults with high probability and at a low cost. Furthermore, the model accuracy can be restored by the proposed edge-cloud collaborative fault-masking retraining and model updating mechanism with a minimized edge-cloud communication overhead. The experimental results show that RRAMedy can effectively detect the memristor permanent and soft faults, protecting the neural accelerator from accuracy and performance degradation in its life cycle.

With the growing cost of powering and cooling, the Dynamic Voltage Frequency Scaling (DVFS) technique has been adopted in many mobiles and embedded devices nowadays. However, attackers are capable of maliciously manipulating the DVFS to threaten application programs including the security related ones. This paper proposes an instruction-level Automatic Test Program Generation (iATPG) framework, which generates test programs to test the vulnerabilities of CPU instructions under the DVFS attack. The conditions that the test program needs to meet, the testability of CPU instructions, and the iATPG algorithm are proposed. It is applied to an arm CPU in a mobile phone. Typical instructions are tested, and some are found vulnerable. The application programs using these instructions are then attacked to prove the effectiveness of the proposed framework.

With the growing cost of powering and cooling, the Dynamic Voltage Frequency Scaling (DVFS) technique has been adopted in many mobiles and embedded devices nowadays. However, attackers are capable of maliciously manipulating the DVFS to threaten application programs including the security related ones. This paper first proposes a test method to test the vulnerabilities of CPU instructions under the DVFS attack. The test program feature, the testability of CPU instructions, and the Test Program Generation Algorithm (TPGA) are proposed. It is applied to an arm CPU in a mobile phone. Typical instructions are tested, and some are found vulnerable. Then, based on the test result, a method for code optimization by instruction substitution is proposed. The application program using vulnerable instructions are then attacked and optimized to prove the effectiveness of the proposed methods.

Neural networks especially the convolution neural networks (CNN) have become prevalent and numerous CNN accelerators have been developed to achieve higher performance. While clock frequency determines the operation speed and has direct influence on the performance of the accelerators, we propose to apply overclocking, a circuit optimization approach that enables higher clock frequency, on general CNN accelerators. This technique brings significant performance improvement, but it leads to moderate timing errors, wrong computing results and low prediction accuracy. By taking advantage of the inherent fault tolerance of neural networks, we opt to learn the computing errors together with the application data with additional on-accelerator training. In this case, the resulting models can be resilient to the errors and do not necessarily suffer considerable prediction accuracy loss. In addition, we also take the worst case of overclocking into consideration with a series of approaches ranging from fault detection to fault recovery in case of hardware crash. Finally, we demonstrate the use of overclocking on a CNN accelerator implemented on Xilinx KCU1500 with comprehensive experiments. The experiments show that overclocking in combination with the on-accelerator neural network training improves both the neural network performance and energy efficiency with small prediction accuracy loss.

The reconfigurability of FPGA makes it flexible for different applications. However, an FPGA may be delivered, designed, and deployed by different persons during its lifecycle, so anyone who can access the FPGA may bring in security issues. This paper proposes an implementation method of a parametric hardware Trojan in the FPGA. This hardware Trojan does not add any extra circuits, so many existing detection methods based on analyzing the design files are invalid.

The year of 2019 marks the 50thIEEE International Test Conference (ITC) - the world's first and premier conference dedicated to electronic test technology. As one of the participating conferences of the ITC global test forum (GTF), China Test Conference (CTC) was invited to join the celebration of the ITC's 50thanniversary. CTC was initiated in Beijing by the test community in China in year of 2000, in the background that China began to highly encourage the developing of its integrated circuit (IC) industry, while test plays a major role in guaranteeing IC's quality and reliability. CTC has been held biennially for ten times and been included into the technical meetings of the IEEE Computer Society Test Technology Technical Council (TTTC). It has been a connection of the test community in China with the international test communities and conferences. The 10thCTC was very successful and was selected as the TTTC Affiliated Most Populous Technical Meeting in 2018.

In the horizontal semiconductor business mode, the foundry can tamper or overbuild the integrated circuits (ICs) while the owner of the IC knows nothing about it. IC metering technique has been proposed to solve this problem. In this paper, we propose a new external active IC metering method. The physical unclonable function (PUF) is used to generate a unique key for each chip. We first propose to modify the finite state machine (FSM) so that the PUF-based key can be securely retrieved from the FSM. With regards to overhead and security, this retrieval scheme takes advantage over the existing scheme with encryption module to safeguard the PUF-based key. The experimental results show that the proposed retrieval scheme incurs negligibly low overhead to the original FSM. Also, the overhead due to the metering method accounts for small percentage to the overall design while the proposed scheme can resist typical attacks.

There is a sheer growth of attention on the issue of deep learning attacks launched by adversaries. Especially with the spread of edge computing devices that cooperate with the central cloud, how to protect the neural network models and private data from being attacked becomes a hot topic. In this paper, we consider two collaborative edge-cloud deep learning scenarios. The first is that deep learning models are trained on resource-rich cloud and deployed on the terminal deep learning accelerators for delay-sensitive tasks. While in the second scenario, edge collected data is offloaded to the cloud for computationally-intensive tasks. In both scenarios, the valuable pre-trained neural network models and the private data are exposed to the risks of being attacked if they are transmitted and processed in an unencrypted way. To tackle this security problem, we present a lightweight protection scheme towards data-oriented attacks and model-oriented attacks. With the use of on-chip memory Physical Unclonable Functions (PUFs) and Processing-In-Memory (PIM), our method limits the model execution only on specific edge devices and also prevents the unauthorized analysis of private data. Experiments on state-of-the-art deep learning networks show that our method secures edge deep learning models and user-data with a negligible performance overhead.

Recently the development of deep learning has been propelling the sheer growth of vision and speech applications on lightweight embedded and mobile systems. However, the limitation of computation resource and power delivery capability in embedded platforms is recognized as a significant bottleneck that prevents the systems from providing real-time deep learning ability, since the inference of deep convolutional neural networks (CNNs) and recurrent neural networks (RNNs) involves large quantities of weights and operations. Particularly, how to provide quality-of-services (QoS)-guaranteed neural network inference ability in the multitask execution environment of multicore SoCs is even more complicated due to the existence of resource contention. In this article, we present a novel deep neural network architecture, MV-Net, which provides performance elasticity and contention-aware self-scheduling ability for QoS enhancement in mobile computing systems. When the constraints of QoS, output accuracy, and resource contention status of the system change, MV-Net can dynamically reconfigure the corresponding neural network propagation paths and thus achieves an effective tradeoff between neural network computational complexity and prediction accuracy via approximate computing. The experimental results show that (1) MV-Net significantly improves the performance flexibility of current CNN models and makes it possible to provide always-guaranteed QoS in a multitask environment, and (2) it satisfies the quality-of-results (QoR) requirement, outperforming the baseline implementation significantly, and improves the system energy efficiency at the same time.

Recently powerful convolutional neural network (CNN) accelerators are emerging as energy-efficient solutions for real-time vision/speech processing, recognition and a wide spectrum of approximate computing applications. In addition to the broad applicability scope of such deep learning (DL) accelerators, we found that the fascinating feature of deterministic performance makes them ideal candidates as application-processors in embedded SoCs concerned with real-time processing. However, unlike traditional accelerator designs, DL accelerators introduce the new aspect of design tradeoff between real-time processing [quality of service (QoS)] and computation approximation [quality of result (QoR)] into embedded systems. This paper proposes an elastic CNN acceleration architecture that automatically adapts to the user-specified QoS constraint by exploiting the error-resilience in typical approximate computing workloads. For the first time, the proposed design, including the network tuning-and-mapping software and reconfigurable accelerator hardware, aims to reconcile the design constraint of QoS and QoR, which are respectively, the critical concerns in real-time and approximate computing. It is shown in experiments the proposed architecture enables the embedded system to work flexibly in an expanded operating space, significantly enhances its real-time ability, and maximizes the system energy-efficiency within the user-specified QoS-QoR constraint through self-reconfiguration. Also, we showcase the application of the proposed design approach to lower power image recognition challenge (LPIRC) and how it is employed to forge an energy-efficient solution to the LPIRC contest.

Trace signal selection is of great importance for post-silicon debug. Debuggers traditionally use state restoration to improve the observability of the trace data, and state restoration ratio (SRR) is computed after state restoration. In this paper, we exploit the combination of snapshot states and trace states to improve the observability. First, we propose a novel state restoration method, called cluster restoration. It uses both the snapshot states of flip-flop clusters at the beginning of tracing, and the tracing states of the clusters' inputs during the tracing window to deterministically restore all states of these clusters during the tracing window. We also present a cluster restoration-based trace signal selection method to select clusters instead of trace signals directly, which includes two stages: 1) cluster generation and 2) cluster evaluation. For cluster generation, feedback loop-based cluster generation and backward tracing-based cluster generation techniques are proposed. For cluster evaluation, a new metric, called the global state restoration improvement is proposed to evaluate the candidate clusters. The experimental results show that in comparison to prior trace signal selection methods, our method can improve the SRR and reduce the runtime of trace signal selection as well.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

Physical unclonable function (PUF) is a promising security primitive. Most existing delay based PUF designs are independent of the original circuit. The extra PUF circuitry not only makes PUF vulnerable to removal attack, but also incurs high area overhead. In this paper, we propose to reuse the parallel scan design existing in the original circuit to implement PUF. The basic idea is to pass the same input signal to two scannable flip-flops and to use the discrepancy in the two output signals' arrival time to generate a PUF bit. Symmetrical SR-latches are used as arbiters to reduce PUF design cost. Compared to the previous scan based PUF using single scan chain, the proposed approach avoids the requirement of a rigorous clock of high frequency. It simultaneously reduces the area overhead and improves the robustness against removal attack. The proposed PUF design is implemented on XILINX Virtex-5 FPGA boards. Experimental results show that it has a high level of uniqueness of 49.86%, very good randomness, and acceptable reliability under temperature and voltage variations.

The resurrection of Processing in memory (PIM) architectures is expected to address the ever-worsening memory wall issue in big data era. In this work, we propose XORiM, an inexpensive PIM design to achieve fast bulky bitwise XOR operation in commodity DRAM devices for memory-intensive workloads. Instead of resorting to 3D-integration or emerging memory technology, we reuse and adapt the peripheral circuits and row-buffers in memory to enable within-DRAM data manipulation. The implemented mechanism can also be employed to conduct high-throughput bulky data operations including memory initialization, AND, OR and INV. We present the detailed circuitry design and transistor-level simulation to evaluate the proposed method, and demonstrate the application of XO-RiM to realistic workloads by conducting full-system level simulation. The experimental results on data-intensive applications such as deduplication and data encryption show that about 1.5× and 5.1× overall performance benefits and 4.9× and 9.1× overall energy savings are achieved respectively by XORiM over conventional computing systems.

Physical unclonable function (PUF) has been widely investigated as a potential security primitive. The unexpected and unclonable PUF information usually serves as a unique ID or secret key in various application scenarios. How to retrieve the PUF information securely at a reasonably low cost is then a concern. In this paper, we propose a new scheme to extract the PUF information by scan chain. PUF information is used to monitor the test control port (tc) of some specific scan cells at certain time. The output response under a designer-specific test vector is hence obfuscated. The difference between the obfuscated output and the normal output can be used to deduce the PUF information. By reusing the existing scan chain design, the design for PUF extraction cannot be removed easily and it incurs negligibly low overhead. As the specific test vector and related design detail are both unknown to others except designer, the probability for an attacker to figure out the PUF information is sufficiently low. This scheme to extract PUF information can be applied in metering technique or other security-sensitive scenarios.

Hardware Trojan has attracted more and more attention from academia and industry because of its significant potential threat. Long activation time is a major concern during Trojan detection process. Traditional pre-silicon verification and post-silicon testing cannot be extended to detect hardware Trojans efficiently because Trojan is usually activated under specific rare conditions. In this paper, we propose a novel approach to expose Trojans efficiently by increasing the transition activities of ASIC logic regions hard to reach. Specifically, the proposed approach detects the "local" regions with low reachability by calculating signals statistical correlation, and detect the "local" regions with low reachability. In addition, by analyzing the global correlations between primary inputs and these rare regions, a retrospective test stimulus generation algorithm is developed to better control the internal logic alteration. Besides, we propose an output sequence model based on CRC check. The experiment results show that the Trojan activation time can be significantly decreased and the Trojans being exposed can be increased dramatically with the proposed method.

The field of image and video recognition has been propelled by the rapid development of deep learning in recent years. With its fascinating accuracy and generalization ability, deep CNNs have shown remarkable performance in large-scale and real-life image dataset. However, accommodating computation-intensive CNN-based image detection frameworks on power-constrained devices is considered more challenging than desktop or warehouse computing systems. Instead of emphasizing purely on detection accuracy, Low Power Image Recognition Challenge (LPIRC) is initiated to highlight the energy-efficiency of different image recognition solutions, and it witnesses the advancement of cost-effective image recognition technology in aspects of both algorithmic and architecture innovation. This paper introduces the cost-effective CNN-based object detection solutions that reached an improved tradeoff between energy and accuracy for mobile CPU+GPU SoCs, which is the winner of LPIRC2016, and it also analyzes the implications of both recent hardware and algorithm advancement on such a technique. It is demonstrated in our evaluation that the performance growth of embedded SoCs and CNN models have clearly contributed to a sheer growth of mAP/WH in current CNN-based object detection solutions, and also shifted the balance between accuracy and energy-cost in the contest solution design when we seek to maximize the efficiency score defined by LPIRC through design parameter exploration.

Unlike standard Convolutional Neural Networks (CNNs) with fully-connected layers, Fully Convolutional Neural Networks (FCN) are prevalent in computer vision applications such as object detection, semantic/image segmentation, and the most popular generative tasks based on Generative Adversarial Networks (GAN). In an FCN, traditional convolutional layers and deconvolutional layers contribute to the majority of the computation complexity. However, prior deep learning accelerator designs mostly focus on CNN optimization. They either use independent compute-resources to handle deconvolution or convert deconvolutional layers (Deconv) into general convolution operations, which arouses considerable overhead. To address this problem, we propose a unified fully convolutional accelerator aiming to handle both the deconvolutional and convolutional layers with a single processing element (PE) array. We re-optimize the conventional CNN accelerator architecture of regular 2D processing elements array, to enable it more efficiently support the data flow of deconvolutional layer inference. By exploiting the locality in deconvolutional filters, this architecture reduces the consumption of on-chip memory communication from 24.79 GB to 6.56 GB and improves the power efficiency significantly. Compared to prior baseline deconvolution acceleration scheme, the proposed accelerator achieves 1.3X–44.9X speedup and reduces the energy consumption by 14.60/0-97.6% on a set of representative benchmark applications. Meanwhile, it keeps similar CNN inference performance to that of an optimized CNN-only accelerator with negligible power consumption and chip area overhead.

The shared memory controllers of single-chip cloud computing (SCC) processors are vulnerable to timing-channel attacks. Existing protection strategies based on fixed memory bandwidth assignment degrade processor performance and severely harm the experience of cloud-users. This paper proposes a novel light-weight timing channel protection scheme against both side channel and covert channel attacks to the shared memory controllers of cloud chip multi-processors (CMPs). Instead of enforcing a fixed time-slot assignment to the applications, we go an entirely different technical route and utilize the background DRAM refresh as a free noise source to eliminate the time correlation between victim and attacker applications. The proposed protection framework, MemJam, relies on the emerging fine-grained refresh technology to achieve the effects of timing channel obfuscation. Multi-programmed workloads running in a cloud CMP were used to evaluate the protection method. The results show that the light-weight refresh-based noise can effectively block the timing-channel between user applications, and achieve up to 1.61~2.49X memory performance boost compared to prior solutions.

With the widely using of VLSI circuits, their security issue has been a critical factor to the security of the modern system. In this paper, we propose a testing method using Bounded Model Checking (BMC) to test the small Trojan that is injected by slightly modifying the original design. First, we implement physical inspection on the training chip set that has the same function but from different sources, and extract suspicious circuit pairs by pairwise comparison on the chips. Second, we use BMC to detect the inconsistent functions on the suspicious circuit pairs. Third, we collects these inconsistent functions as well as their corresponding input sequences into a vulnerability scanner library, and test the other chips using that library. Experimental results show the proposed method can detect the small Trojan in sequential circuits with large sequential depth using an optimized computing time. Furthermore, the method can accurately distinguish small Trojans from circuit optimizations in logic synthesis.

The shared memory controllers of Single-Chip Cloud computing processors are vulnerable to timing-channel attacks. Existing protection strategies based on fixed memory bandwidth assignment degrade processor performance and severely harm the experience of cloud-users. This paper proposes a novel light-weight timing channel protection scheme against both side channel and covert channel attacks to the shared memory controllers of cloud Chip Multi-Processors (CMPs). Instead of enforcing a fixed time-slot assignment to the applications, we go an entirely different technical route and utilize the background DRAM refresh as a free noise source to eliminate the time correlation between victim and attacker applications. The proposed protection framework, MemJam, relies on emerging Fine-Grained Refresh technology to achieve the effects of timing channel obfuscation. Multi-programmed workloads running in a cloud CMP were used to evaluate the protection method. The results show that the light-weight refresh-based noise can effectively block the timing-channel between user applications, and achieve up to 1.69~3X memory performance boost compared to prior solutions.

The IP session focuses on challenges, opportunities, and solutions to hardware security. The first contribution discusses design for security and security validation challenges needed to be considered by EDA industry. The second presentation then talks about security verification technologies throughout the design lifecycle. The last contribution discusses a solution that can improve the security of electronic hardware manufacturing.

Physical Unclonable Function (PUF) is a promising hardware security primitive. One important category of PUFs is the strong PUF with numerous Challenge-Response Pairs (CRPs). Since the typical strong PUFs, the arbiter PUF and several its variants, were broken by modeling attacks, many new designs for resisting modeling attacks have been proposed. Do they really achieve their promise, or are they only another pipe dream? This paper targets two PUF designs: the randomized PUF and the obfuscation PUF, which strengthen the arbiter PUF by leveraging the random number and the weak PUF, respectively. A heuristic algorithm is proposed for attacking these PUFs. The algorithm is implemented in CUDA. Some PUFs that cannot be broken in several months by CPU show their vulnerabilities in days by leveraging the GPU acceleration. The experimental results show that, for certain scales of objective PUFs, the prediction accuracy is beyond the reliability of CRPs, indicating successful attacks.

The trigger circuitry is critical for trace-based post-silicon debug, which detects specified events or event sequences to initiate or stop the tracing. In this paper, we propose a resource efficient trigger design for the post-silicon debug which integrates several different detection schemes to improve the detect ability. The design reuses the trace buffer to store the trigger set for event detection or store the transitions of the generated finite state machine for event sequence detection, which converts the trigger detection into simple read operations to the trace buffer and equality matching operations. Simulation and emulation are both used to validate the usability of the design. In comparison with the prior trigger circuits with the same trigger width, the proposed method provides much more powerful detect ability and configurability for complicated trigger conditions, and needs lower area overhead.

Data compression has been intensively studied to increase the utility of cache, network-on-chip (NoC), and main memory in energy-efficient processors. However, prior solutions to data compression often add remarkable compression and decompression delay to the critical path of memory access, which is thought as the major factor limiting its application to commodity processors. Unlike prior work that deals with memory compression or network compression separately, this paper proposes a unified on-chip distributed data compressor (DISCO), to enable near-zero-latency cache and memory block compression for chip multiprocessors adopting nonuniform cache access. DISCO integrates a multimode cache compressor into the NoC routers and overlaps the de/compression latency with the queuing delay in the network. In addition, cache block evicted to or fetched from the main memory can also be compressed or decompressed during the network queuing time in this unified DISCO compressor. With the support of congestion-awareness, it is shown in the evaluation that DISCO, which unifies the compression solution of the memory hierarchy, dramatically decreases the compression overhead of isolated techniques, and significantly boosts the efficiency of data moving and store.

The rapid development of machine learning is enabling a plenty of novel applications, such as image and speech recognition for embedded and mobile devices. However, state-of-the-art deep learning models like convolutional neural networks (CNNs) are demanding so much on-chip storage and compute resources that they cannot be smoothly handled by low-power mobile or embedded systems. In order to fit large CNN models into mobile or more cutting-edge devices for IoT or cyberphysics applications, we proposed an efficient on-chip memory architecture for CNN inference acceleration, and showed its application to in-house single-instruction multiple-data structure machine learning processor. The redesigned on-chip memory subsystem, Memsqueezer, includes an active weight buffer and data buffer set that embraces specialized compression methods to reduce the footprint of CNN parameters (weights) and activation data, respectively. Memsqueezer buffer can compress the data and weight set according to the dataflow in computation, and it also includes a built-in redundancy detection mechanism that actively scans through the working-set of CNNs to boost their inference performance by eliminating the computation redundancy in CNN models. In our experiments, it is shown that the CNN processors with Memsqueezer buffers achieve more than 2× performance improvement and reduces 85% energy consumption on average over the conventional buffer design with the same area budget.

Hardware Trojans (HTs) are emerging threats for integrated circuits. In this paper, we propose a novel scheme, named LMDet, to detect HTs through distinguishing the “unnaturalness” of HTs from the “naturalness” of normal circuits using the natural language processing technology. The key insight of LMDet is that we find clean circuits tend to be “natural” (i.e., to be highly repetitive in structure) and HTs appear to be “unnatural” (i.e., to be rare in structure) in some sense. LMDet models circuit gates sequentially, using the n-gram language model. Gate sequences from the circuit under detection (CUD) are assessed according to their probability in the model, and lowprobability sequences are marked as suspected Trojan-related gates. Evaluation with benchmarks and industrial circuits shows that LMDet is capable of detecting Trojan logic without the HT-free reference of CUD. LMDet has short execution time on large commercial circuits with acceptable space overhead. It is a promising method in real industry since plenty of HT-free designs are available as training corpus to ensure good statistical effects.

Processing-in-Memory (PIM), has recently been revisited as one of the most promising solutions to deal with the issue of bandwidth and power wall between processor and memory. In this paper, we propose a light-weight PIM architecture, approxPIM, which leverages approximate computing techniques to enable InMemory Processing in a realistic 3D-stacked DRAM, Micron's Hybrid Memory Cube (HMC). Using the newly-released atomic instruction support of the HMC, approxPIM can process a wide range of data-intensive applications without adding any logic resources into the memory devices. Furthermore, we propose to approximate those accuracy-insensitive applications with the limited functioning set of HMC commands so that they could be smoothly mapped to the HMCs without the inference from processors, therefore enabling energy-efficient Processing-in-Memory and greatly expanding the scope of target PIM applications with HMC. In general, approxPIM gives a comprehensive study on HMC's potential and weakness in the application of Processing-in-Memory. Evaluation results show that our approxPIM significantly boosts the energy-efficiency and performance of the whole system.

Mining from simulation data has been introduced as an effective solution to assertion generation for the design under verification (DUV) in prior work. As the simulation data is inherently incomplete, the quality of mined assertions is to be measured. In this paper, we propose a Belief-failRate framework to evaluate the success possibility of mined assertions, by taking both occurrences of free variable assignments and conflicts of absent scenarios into consideration. Meanwhile, a success possibility guided assertion constraining method is given to improve the quality of generated assertions. Experimental results show that assertions with high ranking using the proposed Belief-failRate framework are likely to have high possibility to be true assertions. Furthermore, guided by the success possibility, the proposed assertion constraining procedure can find assertions that cover new design functionality.

In this paper, we propose a new external active metering technique. Physical unclonable function (PUF) is used to generate a unique key for each IC. The PUF key is encrypted by public-key cryptography (PKC) algorithm and passed to the design house for decryption with private key. Only when the foundry inputs correct key into the design, can the design be unlocked and work normally. A new locking scheme is implemented by controlling the working mode of some specific scan cells in scan chain. Such locking scheme will not affect the timing of the functional path. Also, this metering method allows multiple input of key friendly. After the first successful activation, the unlocking circuitry will not function any more, which overcomes the weakness of multiple queries of correct key from design house due to the variation of PUF key with environmental change or aging. The metering method just incurs acceptably low area overhead and no compromise of testability. It can resist typical attacks.

The search for alternative memory technologies has attracted significant attention toward emerging non-volatile memories. Among them, STT-MRAM, PCM, RRAM have shown promising characteristic to gain a position inside the memory hierarchy of computing platforms, and even enable new computing paradigms. However like any other emerging technology these devices are affected by concerns to be resolved before they could become a mainstream. This paper reviews the main reliability and testability challenges of aforementioned emerging non-volatile memories and highlights the main future considerations toward them.

Scan-based design-for-testability (DfT) structure has been widely adopted in integrated circuit (IC) design. It enables high testability for circuit under test (CUT). However, security concerns are also caused. For a cryptographic chip or module, an adversary can use scan chain as a side channel to collect sensitive information for the retrieval of cipher key. This poses a high threat for the fields where the cryptographic chips are applied. Effective countermeasures should be explored to solve this problem. In this paper, we survey the existing work on secure scan designs and highlight their merits and weaknesses. Our recent work is presented to illustrate how the weaknesses in existing countermeasures can be overcome. All these work are compared in terms of the area overhead, security and impact on testability. Our ongoing work is briefly introduced to indicate the promising future work in this area.

Due to the recent progress in deep learning and neural acceleration architectures, specialized deep neural network or convolutional neural network (CNNs) accelerators are expected to provide an energy-efficient solution for real-time vision/speech processing. recognition and a wide spectrum of approximate computing applications. In addition to their wide applicability scope, we also found that the fascinating feature of deterministic performance and high energy-efficiency, makes such deep learning (DL) accelerators ideal candidates as application-processor IPs in embedded SoCs concerned with real-time processing. However, unlike traditional accelerator designs, DL accelerators introduce a new aspect of design trade-off between real-time processing (QoS) and computation approximation (QoR) into embedded systems. This work proposes an elastic CNN acceleration architecture that automatically adapts to the hard QoS constraint by exploiting the error-resilience in typical approximate computing workloads For the first time, the proposed design, including network tuning-and-mapping software and reconfigurable accelerator hardware, aims to reconcile the design constraint of QoS and Quality of Result (QoR). which are respectively the key concerns in real-time and approximate computing. It is shown in experiments that the proposed architecture enables the embedded system to work flexibly in an expanded operating space, significantly enhances its real-time ability. and maximizes the energy-efficiency of system within the user-specified QoS-QoR constraint through self-reconfiguration.

Online testing is critical to ensure reliable operation of manycore systems based on a network-on-chip (NoC) interconnection fabric. We present a software-based online NoC self-testing solution based on bounded model checking (BMC). The proposed method first implements BMC on a sliced extended finite-state machine, and extracts the leading sequences necessary to excite NoC functions. Next, it targets the structural faults within every function excited by the leading sequence through constrained ATPG. Finally, a test protocol is developed to make the test responses observable. Experimental results show that the proposed method achieves high fault coverage in functional mode and outperforms previously proposed solutions. In addition, the fault coverage is very close to that of full-scan testing, but without any area overhead.

The lack of observability of prototype chips makes post silicon debug extremely difficult and time consuming. Trace based debug techniques can improve the observability by acquiring some internal states at runtime through a dedicated on-chip trace buffer. In this paper, we propose a flip-flop clustering based trace signal selection method, which uses the forward tracing to generate flip-flop clusters and evaluates the global state restoration improvement to select the clusters for state capturing. The predecessor flip-flops of the selected cluster are used as trace signals, and the internal flip-flops of the selected clusters are used as snapshot signals. The experimental results show that in comparison with the prior methods, our method can increase the state restoration ratio by 74.8% on average with no more than 1.58% storage overhead for storing snapshots. The runtime for trace signal selection is also much less than those of prior methods.

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Refresh operations consume substantial energy and bandwidth in high-density dynamic random-access memory (DRAM) memory. The trend of increasing refresh overhead limits the scalability of DRAM memory that refreshes all cells at the same rate, because the refresh rate setting depends on the worst-case weak cell manufactured in unstable process technology. To cope with this issue, fine-grained refresh (FGR) is proposed to eliminate the unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR, which is likely to evolve and become a standard in future DRAM. Unfortunately, according to our key observation, the effectiveness of FGR is greatly confined by the procedure of refresh-oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this paper, we are the first to propose a holistic FGR-oriented DRAM optimization framework, retention-aware DRAM assembly and repair (RADAR), to enhance the effectiveness of FGR in DRAM modules. RADAR includes two novel techniques applicable at the stage of DRAM assembly. The first one is retention-aware device clustering that integrates the “compatible” devices to achieve low refresh rate through a preassembly testing and retention-aware matching method. The second technique, Microfix, exploits the hierarchical DRAM array structure and its redundancy to fix critical weak DRAM rows through fine-grained row and subarray remapping. With this optimization architecture, RADAR, the refresh overhead of DRAM dual in-line memory modules can be dramatically reduced as implied in the experiments.

As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

Multilevel spin toque transfer RAM (STT-RAM) is a suitable storage device for energy-efficient neural network accelerators (NNAs), which relies on large-capacity on-chip memory to support brain-inspired large-scale learning models from conventional artificial neural networks to current popular deep convolutional neural networks. In this paper, we investigate the application of multilevel STT-RAM to general-purpose NNAs. First, the error-resilience feature of neural networks is leveraged to tolerate the read/write reliability issue in multilevel cell STT-RAM using approximate computing. The induced read/write failures at the expense of higher storage density can be effectively masked by a wide spectrum of NN applications with intrinsic forgiveness. Second, we present a precision-tunable STT-RAM buffer for the popular general-purpose NNA. The targeted STT-RAM memory design is able to transform between multiple working modes and adaptable to meet the varying quality constraint of approximate applications. Lastly, the reconfigurable STT-RAM buffer not only enables precision scaling in NNA but also provides adaptiveness to the demand for different learning models with distinct working-set sizes. Particularly, we demonstrate the concept of capacity/precision-tunable STT-RAM memory with the emerging reconfigurable deep NNA and elaborate on the data mapping and storage mode switching policy in STT-RAM memory to achieve the best energy efficiency of approximate computing.

Unlike conventional ICs, approximate computing chips are less sensitive to hardware errors. This fascinating feature can be utilized to improve the performance of chip design and even change the timing closure procedure of digital circuit design flow. In this paper, we study the potential of resilience-aware circuit clocking scheme, and demonstrate the methodology with advanced neural network (NN)-based accelerator. We propose a novel timing analysis and frequency setting method for NN-based approximate computing circuits based on in-field NN retraining. With the proposed iterative retiming-and-retraining framework, NN-based accelerator can be retrained to operate safely at aggressive operating frequencies compared with the frequency decided purely by statistical timing analysis or Monto Carlo analysis. For nanometer process technology with increasing threats of timing errors induced by process variation, noises, and so on, our retiming-and-retraining method enables higher circuit operating frequency and enables dynamic precision/frequency adjustment for approximate computing circuits. We evaluate the methodology with both the neural and deep learning accelerators in experiments. The experimental results show that timing errors in neural circuits can be effectively tamed for different applications, so that the circuits can operate at higher clocking rates under the specified quality constraint or be dynamically scaled to work at a wide range of frequency states with only minor accuracy losses.

Trustworthiness of a hardware design has caused great concerns, including the malicious modifications on the design made by Electrical Design Automation (EDA) tools of third-party. In this paper, a novel hardware Trojan (HT) detection method based on the property coverage analysis is proposed to verify the synthesized netlist. The proposed method is motivated by the observation that the malicious modification on the design would threaten the predesigned properties, either by invalidating the properties or by lowering their state coverage, which can be verified by model checking in principle. The proposed method has generality and can be applied to a variety of hardware Trojans. With HTs inserted in the netlists, the experimental results show the proposed method can detect the malicious Trojans effectively.

Data compression has been proposed to increase the utility of on-chip memory space or Network-on-Chip (NoC) bandwidth in energy-efficient processors. However, such techniques usually add additional compression and decompression latency to the critical path of memory access, which is one of the major factors limiting their application to processors. In contrast to prior work that deals with either cache compression or network compression separately, this study proposes a unified on-chip DIStributed data COmpressor, DISCO, to enable near-zero latency cache/NoC compression for chip multi-processors (CMPs) adopting Non-Uniform Cache Access (NUCA). DISCO integrates data compressors into NoC routers and seeks opportunity to overlap the de/compression latency with the NoC queuing delay through a coordinated NoC scheduling and cache compression mechanism With the support of DISCO that unifies the solutions of on-chip data compression, it is shown in evaluation that DISCO significantly boosts the efficiency of on-chip data caching and data moving.

Recent advances in Neural Networks (NN) are enabling more and more innovative applications. As an energy-efficient hardware solution, machine learning accelerators for CNNs or traditional ANNs are also gaining popularity in the area of embedded vision, robotics and cyberphysics. However, the design parameters of NN models vary significantly from application to application. Hence, it's hard to provide one general and highly-efficient hardware solution to accommodate all of them, and it is also impractical for the domain-specific developers to customize their flown hardware targeting on a specific NN model. To deal with this dilemma, this study proposes a design automation tool, DeepBurning, allowing the application developers to build from scratch learning accelerators that targets their specific NN models with custom configurations and optimized performance. DeepBurning includes a RTL-level accelerator generator and a coordinated compiler that generates the control flow and data layout under the user-specified constraints. The results can be used to implement FPGA-based NN accelerator or help generate chip design for early design stage. In general, DeepBurning supports a large family of NN models, and greatly simplifies the design flow of NN accelerators for the machine learning or AI application developers. The evaluation shows that the generated learning accelerators burnt to our FPGA board exhibit great power efficiency compared to state-of-the-art FPGA-based solutions.

The rapid development of deep learning are enabling a plenty of novel applications such as image and speech recognition for embedded systems, robotics or smart wearable devices. However, typical deep learning models like deep convolutional neural networks (CNNs) consume so much on-chip storage and high-throughput compute resources that they cannot be easily handled by mobile or embedded devices with thrifty silicon and power budget. In order to enable large CNN models in mobile or more cutting-edge devices for IoT or cyberphysics applications, we proposed an efficient on-chip memory architecture for CNN inference acceleration, and showed its application to our in-house general-purpose deep learning accelerator. The redesigned on-chip memory subsystem, Memsqueezer, includes an active weight buffer set and data buffer set that embrace specialized compression methods to reduce the footprint of CNN weight and data set respectively. The Memsqueezer buffer can compress the data and weight set according to their distinct features, and it also includes a built-in redundancy detection mechanism that actively scans through the work-set of CNNs to boost their inference performance by eliminating the data redundancy. In our experiment, it is shown that the CNN accelerators with Memsqueezer buffers achieves more than 2× performance improvement and reduces 80% energy consumption on average over the conventional buffer design with the same area budget.

Scan design has been widely used to facilitate the testing of integrated circuits (ICs). However, it also provides attackers a side-channel to access the internal states of crypto chips and thus becomes a great threat to the security of the cipher keys. We propose a secure scan design scheme to protect crypto chips against such scan-based side-channel attacks. In this scheme, we introduce a shift register to control the working mode of certain scan cells. Only when the user configures the shift register correctly, can the scan design work normally under testing mode. We show that the proposed secure scan design can effectively resist the existing scan-based attacks. We also demonstrate that this approach has low area overhead while maintaining the testability of original design.

Property coverage is an important way to evaluate the completeness of model checking. Most of the property coverage metrics are based on mutation coverage, obtained by mutating the design and checking the property's ability to detect the mutation. Due to the complexity of computing mutation coverage in model checking, the previous methods resort to some approximate algorithms which tend to give pessimistic estimation of state coverage, and can only deal with a limited subset of Computation Tree Logic (CTL). In this paper, we present an improved algorithm to compute mutation coverage for arbitrary CTL formulas with high accuracy. Experimental results show that the proposed algorithm can identify a great number of covered states missed by a previous method. Meanwhile, the extension to the complete CTL set makes it easy to write all kinds of properties to describe the features of the design better.

Traditional coverage metrics in verification focus on controllability without taking observability into account, which may result in an artificially high coverage and a false sense of confidence. In this paper, we present a path constraint solving based test generation method at register-transfer level (RTL) for observability-enhanced branch coverage. The branches executed but not observed by a test sequence are identified as our target branches. The test generation for each target branch is converted to the process of covering multiple intermediate sub-target states sequentially to guarantee the execution and observation of the target branch. Valid input vectors are automatically generated by multicycle path constraint solving and simulation is guided by the abstract distance information to reach the sub-target states. Experimental results show that our approach can reduce the gap between branch coverage and observability-enhanced branch coverage.

In field degradation of manycore processors poses a grand challenge to core management, largely because the degradation is hard to quantify. We propose a novel core-level degradation quantification scheme, CoreRank, to facilitate the management. We first develop a new degradation metric, called “healthy condition”, to capture the implication of performance degradation of a core with specific degraded components. Then, we propose a performance sampling scheme by using micro-operation streams, called snippet, to statistically quantify cores’ healthy condition. We find that similar snippets exhibit stable performance distribution, which makes them ideal micro-benchmarks to testify the core-level healthy conditions. We develop a hardware-implemented version of CoreRank based on bloom filter and hash table. Unlike the traditional “faulty” or “fault-free” judgement, CoreRank provides a key facility to make better use of those imperfect cores that suffered from various progressive aging mechanisms such as NBTI, HCI. Experimental results show that CoreRank successfully hides significant performance degradation of a defective manycore processor in which even more than half of the cores are salvaged from various defects.

This paper presents a novel abstraction-guided simulation approach for functional verification. The results of Markov analysis of the abstract model of the design under verification are used as the guidance of simulation on the concrete design. The results of the Markov analysis can offer the information about how hard it is to reach each abstract state from the initial state, and how hard it is to reach certain target states from each abstract state. Such information is able to guide the simulation in two aspects: 1) in exploring abstract state space and 2) in exercising target state. Assuming a good abstract model, experimental results show that the simulation using Markov analysis as guidance is highly efficient in both aspects.

Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods.

Voltage-frequency island (VFI)-based design has been widely exploited for optimizing system energy of embedded multicore chip in recent years. The existing work either constructed a single static VFI partition for all kinds of applications or required per-core voltage domain configuration. However, the former solution is hard to find one optimal VFI partition for diverse applications while the latter one suffers from high hardware cost. In this article, we propose a cost effective energy optimization framework based on dynamically reconfigurable VFI (D-VFI). Our framework treats a small number of cores as dynamic cores (D-cores) and configures each of them with an independent voltage domain. At runtime, the D-cores can be pieced together with neighboring static VFIs by scaling their operating voltages. This can dynamically construct the optimal VFI partitions for different kinds of applications, thus achieving more aggressive energy optimization under low cost. To identify the D-cores, we propose a rules constrained task scheduling and VFI partitioning algorithm. Moreover, we analyze the task schedules to determine the optimal scaling intervals which can accommodate voltage scaling induced latency. Experimental results demonstrate that the effectiveness of the proposed scheme.

In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache, and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that exploits near-threshold computing and multivoltage domain to approach the limit of Vddin a low-power cache. However, the adoption of near-threshold voltage (NTV) leads to a rocketing error probability in SRAM arrays, which has to be addressed by effective fault-tolerant techniques. Instead of using error correction code or data duplication, the VANUCA exploits the natural data redundancy across the whole memory hierarchy to enable fast fault recovery in the NTV cache. Based on the discovered data resilience and the multi-Vddarchitecture, the VANUCA is able to match vulnerable/invulnerable data clusters to available high-/low-voltage domains by utilizing the data migration mechanism in dynamic NUCA. The proposed VANUCA includes two important architectural techniques: 1) static assignment that assumes a fixed voltage domain partitioning and 2) DataMotion that dynamically fits the working set into heterogeneous cache banks through Vddswitching. Experimental results show that the VANUCA achieves considerable improvements in energy efficiency over the conventional single-voltage domain NUCA cache.

In 3-D-stacked memory chips, the problem of power supply integrity (PSI) is aggravating due to the additional through-silicon-via resistance and the higher current density in 3-D power delivery network. In particular, for the 3-D phase-change memory (PCM) well known for its high-amplitude programming current, IR-drop violation poses a serious threat that enforces a strict guard band of requesting concurrence, and consequently reduces the write throughput. This paper presents the implication of an IR-drop phenomenon in a 3-D PCM cube, and investigates IR-drop's impacts on write management in the PCM. From the obtained SPICE simulation results, we find that the issued writes have to meet the IR-drop constraint to be reliably processed, and then propose a PSI conscious write scheduler to improve the write performance within the constraint of the IR-drops and the power budget in the 3-D PCM cube. First, a Bloom-filter-based method is proposed to avoid the invalid write decisions for the PCM. Second, to support fine-grained write management in the cutting-edge PCM, we develop an inexpensive approach, weighted token assignment (WTA), to filter out PSI-unsafe write decisions by employing a support vector machine-based learning model. Last, a write reordering policy is proposed to cooperate with WTA and optimize the total write throughput for better memory performance. In the simulated hybrid main memory composed of both dynamic random access memory and 3-D PCM, the proposed scheduler significantly improves the write throughput.

On-chip faster-than-at-speed delay testing provides a promising way for small delay defect detection. However, the frequency of on-chip generated test clock would be impacted by process variations. Hence, it requires determining the actual frequency of generated test clock to ensure the effectiveness of faster-than-at-speed delay testing. In this paper, we present a novel test clock generation scheme, namely Enhanced LCCG, for faster-than-at-speed delay testing. In the proposed scheme, faster-than-at-speed test clock is firstly generated by configuring the corresponding control information specified in the test pattern into Enhanced LCCG. Then, by constructing oscillation paths and counting the corresponding oscillation iteration numbers, the actual frequency of test clock can be measured and calculated with high resolution. Experimental results are presented to validate the proposed method.

With the growth of cloud computing, security and privacy is becoming more and more important. Timing channel attack is one of the most remarkable security threads for memory controllers due to competition for shared resources. However, the existing protection strategies that ensure the deterministic of memory accesses by dividing bandwidth introduce great latency and performance degradation. This paper proposes a refresh hiding approach that adjusts the refresh operations to multiplex refresh time with additional latency introduced by those bandwidth division strategies. The experiment results show refresh hiding can reduce more than 20% of program runtime, and it will be more efficient as DRAM density increases.

Network-on-chip (NoC) is a major communication technique for 3D integrated circuits (ICs). In order to achieve higher throughput and lower latency with less system cost, horizontal and vertical wireless links are adopted to apply in the 3D NoCs. So far, the reliable routing scheme has been regarded as a lightweight and high-efficiency mechanism to guarantee the performance of the faulty 2D/3D NoCs. In this paper, we propose a low-overhead turn-guided reliable routing scheme named TWiN for the vertical link faults in wireless 3D NoCs. TWiN is deadlock-free without any virtual channels (VCs). Experimental results show that TWiN possesses higher performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing scheme for wireless 3D NoCs.

Emerging highly-parallel and big data applications have renewed the research interest in Processing-in-Memory (PIM) architectures. However, moving powerful processing unit into the CMOS-incompatible DRAM chips is not cost-effective for large capacity memory. In this work, we observe that Non-Volatile Memory is often naturally incorporated with basic logics like Data Comparison Write or Flip-n-Write modules that are essential for cell SET/REST operation. In contrast to other conventional PIM or Near Data Computing (NDC) architectures, ProPRAM, as a typical Active NVM, abandons the design approach of moving accelerators or customized processors into memory devices, but begins with exploiting the existing resources inside the memory chips to accelerate the key non-compute-intensive functions for emerging big data applications. With slight hardware and architectural modification, we succeed to expose the transparent peripheral logics to the application layer through instruction set extension and exploit them for in-field bulk data processing with limited hardware cost. Compared to conventional CPU-centric systems, ProPRAM achieves an excellent optimization on energy-efficiency (15x) for important data-intensive micro-benchmarks and kernels.

Refresh operations consume substantial energy and bandwidth in high-density DRAM memory. To cope with this issue, Fine-Grained Refresh (FGR) is recently proposed to eliminate unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR to make DRAM refresh more scalable. Unfortunately, we observe that the effectiveness of FGR is greatly confined by the procedure of refresh-oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this work, we firstly propose to intelligently integrate the "compatible" devices through a pre-assembly testing and retention-aware matching method. Second, we reuse the reconfiguration structure from yield-oriented remapping mechanism in memory chips and propose Microfix to create a balanced distribution of retention time in memory banks through fine-grained row-address tuning. With this optimization architecture, RADAR, we can eliminate the refresh overhead of produced memory modules by 28% on average.

Multi-level STT-RAM cell is able to boost the memory density at the expense of read/write reliability. However, the induced data integrity issue in STT-RAM memory can be effectively masked by a wide spectrum of applications with intrinsic forgiveness, which belong to the specific domain such as multimedia, synthesis and mining. In this work, we leverage the reconfigurable capability of MLC STT-RAM to provide variable-precision data storage for popular machine learning architectures. The targeted STT-RAM memory design is able to transform between multiple work modes and adaptable to meet the varying quality constraint of approximate applications. Particularly, we demonstrate the concept of precision-tunable STT-RAM memory with the emerging Convolution Neural Network accelerators and elaborate on the data mapping policy in STT-RAM memory to achieve the best energy-efficiency.

The confluence of 3-D integration and network-on-chip (NoC) provides an effective solution to the scalability problem of on-chip interconnects. In 3-D integration, through-silicon via (TSV) is considered to be the most promising bonding technology. However, TSVs are also precious link resources because they consume significant chip area and possibly lead to routing congestion in the physical design stage. In addition, TSVs suffer from serious yield losses that shrink the effective TSV density. Thus, it is necessary to implement a TSV-economical 3-D NoC architecture in cost-effective design. For symmetric 3-D mesh NoCs, we observe that the TSVs bandwidth utilization is low and they rarely become the contention spots in networks as planar links. Based on this observation, we propose the TSV sharing (TS) scheme to save TSVs in 3-D NoC by enabling neighboring routers to share the vertical channels in a time division multiplexing way. We also investigate different TS implementation alternatives and show how TS improves TSV-effectiveness (TE) in multicore processors through a design space exploration. In experiments, we comprehensively evaluate TSs influence on all layers of system. It is shown that the proposed method significantly promotes TE with negligible performance overhead.

In chip multiprocessors (CMPs), nonuniform cache architecture (NUCA) is often employed to organize last-level cache (LLC) banks through network-on-chip (NoC). Because of the shrinking feature size and unstable operating environment, severe reliability problems unavoidably emerge and cause frequent on-chip component (e.g., cores, cache banks, routers) failures. Typical fault-tolerant CMPs should possess the feature of graceful degradation and function normally with deactivated tiles. However, for CMPs adopting static NUCA, certain physical address areas will become inaccessible when cache banks in a CMP node are isolated from the system. To protect cache from such threats induced by either online or offline faults, we survey several potential solutions and propose the utility-driven node remapping technique by reusing the resources in NoC. In our NoC-assisted remapping scheme, cache accesses to isolated banks are so redirected that cache space contention are successfully balanced and relieved in shared-LLC, thus ensuring the least performance penalty caused by fault isolation. Our experimental results show significant performance improvement over conventional resizing approaches such as set reduction.

Error detection and locating during the post-silicon stage is a critical concern in modern IC industry. Especially timing errors caused by uncertain variations and electrical bugs are by far lacking effective methods to debug. In order to meet this challenge, we propose an on-line timing error detection method, which uses the on-chip storage to hold the golden execution trace by running the test program under the lower frequency condition, followed by comparison of the stored golden trace against runtime trace acquired under the specified test condition. Timing errors are founded after some differences appeared during the trace comparison. This self-checking approach can detect tricky timing errors without the time-consuming software simulation and trace dumping, which accelerates the detection procedure by orders of magnitude. Besides, tracing internal key signals will find timing errors as soon as the error occurs, which can decrease the latency of error detection. The experiments on FPGA show it is effective to detect timing errors for a core-based system on chip (SoC) design and speeds up the timing error debug process with less than 2% hardware cost.

This paper presents a novel method for functional test generation aiming at exploring control state space of the design. The steady-state probabilities (SP's) of the abstract design's control FSM are used to guide test generation. The SP's of the states can reflect how hard the states can be reached, and the hard-to-reach states are assigned with high priority to be exercised. Experimental results show that our method has better performance in test generation in comparison with constrained random simulation, and demonstrate that SP's provide good guidance on traversing hard-to-reach states of the design under validation.

With the increase of storage density, DRAM refresh leads to higher overhead of power and bandwidth, particularly in emerging 3D stacked memory design like Hybrid Memory Cube (HMC). To exploit the hardware resources for a smarter solution, we propose a data-aware refresh control scheme, Trial and Error (Trial-n-Error), which leverages the data-pattern dependence characteristics of the cells' retention time to reduce refresh operations. Trial-n-Error is a systematic approach that employs our proposed Synergy Testing to capture the refresh bottleneck of DRAM memory: “weak” cells that have a relatively shorter retention time. By locating the dominant weak cells sensitized by applications, Trial-n-Error can avoid the worst-case refresh setting, and adjust the refresh rate under the control of our self-tuning algorithm. Thus, Trial-n-Error can gradually approach to the possible lower-bound of refresh rate for less energy and memory bandwidth consumption. In experiments of 3D-stacked DRAMs, we successfully eliminate an average of 28% refresh operations and save 21% refresh energy for a set of pre-profiled synthetic data patterns and real benchmarks.

Because of tight power and energy constraints, industry is progressively shifting toward heterogeneous system-on-chip (SoC) architectures composed of a mix of general-purpose cores along with a number of accelerators. However, such SoC architectures can be very challenging to efficiently program for the vast majority of programmers, due to numerous programming approaches and languages. Libraries, on the other hand, provide a simple way to let programmers take advantage of complex architectures, which does not require programmers to acquire new accelerator-specific or domain-specific languages. Increasingly, library-based, also called algorithm-centric, programming approaches propose to generalize the usage of libraries and to compose programs around these libraries, instead of using libraries as mere complements. In this article, we present a software framework for achieving performance portability by leveraging a generalized library-based approach. Inspired by the notion of a component, as employed in software engineering and HW/SW codesign, we advocate nonexpert programmers to write simple wrapper code around existing libraries to provide simple but necessary semantic information to the runtime. To achieve performance portability, the runtime employs machine learning (simulated annealing) to select the most appropriate accelerator and its parameters for a given algorithm. This selection factors in the possibly complex composition of algorithms used in the application, the communication among the various accelerators, and the tradeoff between different objectives (i.e., accuracy, performance, and energy). Using a set of benchmarks run on a real heterogeneous SoC composed of a multicore processor and a GPU, we show that the runtime overhead is fairly small at 5.1% for the GPU and 6.4% for the multi-core. We then apply our accelerator selection approach to a simulated SoC platform containing multiple inexact accelerators. We show that accelerator selection together with hardware parameter tuning achieves an average 46.2% energy reduction and a speedup of 2.1× while meeting the desired application error target.

Emerging nonvolatile memories such as phase change memory (PCM) have the potential to replace internal memories in embedded devices. In this brief, we propose to use PCM as image buffer in application-specific multimedia systems. To improve the lifetime of PCM-based image buffer, we first eliminate redundant writes using data comparison. After redundant write elimination, PCM cells with respect to lower order bits of pixels are written more frequently than those corresponding to higher order. Based on this observation, we show that the lifetime can be further improved either by wear leveling using periodical data reversion to make write traffic even across PCM cells or by application-level error tolerance evaluation without leveling. Experimental results demonstrate that with the proposed techniques, the lifetime of PCM-based image buffer can be improved significantly.

Fault-tolerant routing is usually used to provide reliable on-chip communication for many-core processors. This paper focuses on a special class of algorithms that do not use virtual channels. One of the major challenges is to keep the network deadlock free in the presence of faults, especially those locating on network edges. State-of-the-art solutions address this problem by either disabling all nodes of the faulty network edges or including all faults into one faulty block. Therefore, a large number of fault-free nodes will be sacrificed. To address this problem, the proposed ZoneDefense routing not only includes faults into convex faulty blocks but also spreads the faulty blocks' position information in corresponding columns. The nodes, which know the position of faulty blocks, form the defense zones. Therefore, packets can find the faulty blocks and route around them in advance. Exploiting the defense zones, the proposed ZoneDefense routing could tolerate many more faults with significantly reduced sacrificed fault-free nodes compared with the state-of-the-art algorithms. Furthermore, the ZoneDefense routing does not degrade the network performance in the absence of faults, and could get similar performance as its counterparts in the presence of faults.

Aggressive technology scaling in modern chips resulted in complicated faulty timing behaviors, which necessitate undesirable long development cycle and high test volumes to ensure product quality. To reduce the test time, cost-effective and timing-efficient test selection algorithms are used to choose optimal test inputs from a large-volume test set. In this paper, we define an approximate longest sensitized path (ALSP) metric to derive the longest sensitized path for all transition faults (TFs) from the detectability of TFs with very low computational complexity. With the ALSP metric, a general public utilities-based parallel test selection method is proposed to choose a small test set with high delay test quality from the timing-unaware n-detection test set. Our results demonstrate the comparison with a commercial automatic test pattern generation tool and a previous timing-aware test selection method targeting small delay defects, and confirm that our test selection algorithm can achieve better delay test coverage and higher n -detection fault coverage with steeper fault coverage curves of ordered patterns, for the same pattern count.

Test generation for hard-to-reach states has been one of the hardest tasks in functional verification. In this paper, we present PACOST, a PAth Constraint Solving based Test generation method which operates in an abstraction-guided simulation framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation in a path constraint solver to generate a set of valid input vectors for exploring different simulation paths, followed by next state selection considering abstract distances. In addition, two backtracking strategies are proposed to alleviate the dead end problem and ensure fast converge to the target state. Experimental results show that PACOST is effective in covering hard-to-reach states.

Power constraint for modern processors becomes a very serious problem with the increasing core counts and cache capacity in multi/many core processors. Compared with processing cores with mature techniques like DVFS to alleviate the situation, last level cache which consume largest portion of processor chip needs effective power management strategy. In this paper, we explore the feasibility of Near-Threshold Voltage(NTV) SRAM and Multi-Voltage Domain (Multi-VDD) for power reduction in large capacity cache. To prevent data corruption in cache, we propose redundancy-based data salvaging technique for fault recovery. To solve the dilemma of power reduction and reliability guarantee, we try to match vulnerable/invulnerable data sets to high/low voltage domains. Different from previous work, we take into consideration multi-bit errors and redundancy masking effects in Multi-VDD cache. Experimental results show that our Multi-VDD cache achieves considerable improvements in energy efficiency.

As an emerging non-volatile memory technology, phase change memory (PCM) is promising as an alternative for traditional memories such as DRAM. In spite of its non-volatility, high density, low standby power, and resilience to soft errors, PCM has a limited write endurance or lifetime, which means that each PCM cell can only be overwritten finite times. More importantly, limited lifetime potentially provides malicious attackers an opportunity to intentionally aggravate write traffic into PCM. In this paper, from the standpoint of attackers, we propose random stream attacks (RSAK) methods for phase change memory used in video applications. Experimental results show that compared to natural video sequences, RSAK incurs higher total write traffic or worsened lifetime. RSAK also gives hints on how to build a more secure PCM in video applications to counter malicious write streams.

This paper proposes a test path selection approach for capturing delay failures caused by the accumulated distributed small delay variations. First, a universal path candidate setU, which contains testable long paths, is generated. Second, given a path number threshold, path selection fromUis performed with the objective of maximizing the capability to capture potential delay failures. The path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that all the paths in a specified path set meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time efficient and achieves higher probability of capturing delay failures than traditional path selection approaches.

Small delay defect (SDD) and aging-induced circuit failure are both prominent reliability concerns for nanoscale integrated circuits. Faster-than-at-speed testing is effective on SDD detection in manufacturing testing, which is always implemented by designing a suite of test signal generation circuits on the chip. Meanwhile, the integration of online aging sensors is becoming attractive in monitoring aging-induced delay degradation in the runtime. These design requirements, if implemented in separate ways, will increase the complexity of a reliable design and consume more die area. In this paper, a unified capture scheme is proposed to generate programmable clock signals for the detection of both SDDs and circuit aging. Our motivation arises from the observations that SDD detection and online aging prediction both need to capture circuit response ahead of the functional clock. The proposed aging-resistant design method enables the offline test circuit to be reused in online operations. Reversed short channel effect is also exploited to make the underlying circuit resilient to process variations. The proposed scheme is validated by intensive HSPICE simulations. Experimental results demonstrate the effectiveness in terms of low area, power, and performance overheads.

Software-based self-testing (SBST) has been a promising method for processor testing, but the complexity of the state-of-art processors still poses great challenges for SBST. This paper utilizes the executing trace collected during executing training programs on the processor under test to simplify mappings and functional constraint extraction for ports of inner components, which facilitate structural test generation with constraints at gate level, and automatic test instruction generation (ATIG) even for hidden control logic (HCL). In addition, for sequential HCL, we present a test routine generation technique on the basis of an extended finite state machine, so that structural patterns for combinational subcircuits in the sequential HCL can be mapped into the test routines to form a test program. Experimental results demonstrate that the proposed ATIG method can achieve good structural fault coverage with compact test programs on modern processors.

Modern video applications such as video codecs are memory-intensive. As an emerging non-volatile memory technology, phase change memory (PCM) will benefit video applications due to its high density, low leakage power and superior scalability. However, PCM consumes high write energy and can only sustain a limited write number. Hence it is necessary to reduce the write number of PCM for video applications. In this paper, we propose SoftPCM to enhance both energy efficiency and lifetime of PCM. SoftPCM utilizes the error tolerance characteristic of video applications to relax the accuracy of write operations. Experimental results show that SoftPCM can reduce 22% writes and thus improve energy efficiency and lifetime of PCM with slight video quality degradation.

Faster than at-speed testing provides an efficient way for testing of small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is managed to be applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing based on path delay fault (PDF) model and single path sensitization criterion. An effective testable path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

In this paper, we present a novel on-chip path delay measurement architecture for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed on-chip path delay measurement (OCDM) circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed OCDM circuit can achieve a large delay measurement range with a small quantity of delay stages. A calibration circuit is incorporated into the proposed on-chip path delay measurement technique to calibrate the delay range of the delay stage under process variations. In addition, delay calibration for import lines is conducted to improve the precision of path delay measurement. Experimental results are presented to validate the proposed path delay measurement architecture.

We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells. Relative measures are presented to reflect the gains when controlling a scan cell to a certain value, and guide the scan cell selection. Experimental results on larger IWLS 2005 benchmark circuits show that, to achieve the same fault coverage of the pure launch on capture (LOC) approach, the volume of test data can be reduced to a half on average by replacing only 1% of regular scan cells to enhanced scan cells. The transition delay fault coverage can also be improved using the proposed method with equally low area overhead.

Error tolerance is evolving into a new computing paradigm with further technology scaling, cost constraint, system scalability and emerging applications. Distinguished from defect tolerance and fault tolerance, error tolerance is based on application characteristics and relaxes the constraint of 100 percent functional correctness. From the viewpoint of error tolerance, this paper proposes a framework across multiple layers for fault criticality evaluation. Furthermore, taking an H.264/AVC decoder as an example, fault injection experiments demonstrate that for different functional modules, the faults in them bear different fault criticalities because of their unbalanced effects on applications, the faults in the same module also have diverse fault criticalities. The information that which faults are most critical can aid in test for yield and design for cost-effective fault tolerance. Error control techniques can be used to suppress error propagation and make more faults acceptable.

The emerging nanophotonic technology can avoid the limitation of I/O pin count, and provide abundant memory bandwidth. However, current DRAM organization has mainly been optimized for a higher storage capacity and package pin utilization. The resulted data fetching mechanism is quite inefficient in performance and energy saving, and cannot effectively utilize the abundant optical bandwidth in off-chip communication. This paper inspects the opportunity brought by optical communication, and revisits the DRAM memory architecture considering the technology trend towards multiprocessors. In our FlexMemory design, super-line prefetching is proposed to boost system performance and promote energy efficiency, which leverages the abundant photonic bandwidth to enlarge the effective data fetch size per memory cycle. To further preserve locality and maintain service parallelism for different workloads, page folding technique is employed to achieve adaptive data mapping in photonics-connected DRAM chips via optical wavelengths allocation. By combining both techniques, surplus off-chip bandwidth can be utilized and effectively managed adapting to the workloads intensity. Experimental results show that our FlexMemory achieves considerable improvements in performance and energy efficiency.

Applications' traffic tends to be bursty and the location of hot-spot nodes moves as time goes by. This will significantly aggregate the blocking problem of wormhole-routed Network-on-Chip (NoC). Most of state-of-the-art traffic balancing solutions are based on fully adaptive routing algorithms which may introduce large time/space overhead to routers. Partially adaptive routing algorithms, on the other hand, are time/space efficient, but lack of even or sufficient routing adaptiveness. Reconfigurable routing algorithms could provide on-demand routing adaptiveness for reducing blocking, but most of them are off-line solutions due to the lack of a practical model to dynamically generate deadlock-free routing algorithms.

This paper proposes a unified delay test architecture, in which the design resources for on-line delay fault detection can be reused to support off-line delay testing. A stability checker, which has low hardware overhead, is presented to monitor the stability violation from each critical combinational output. A global error generator, which is shared among stability checkers, can produce a global error signal from individual stability checkers to indicate whether a delay fault appears. A local scan enable generator is incorporated into the scan chain to support scan-based off-line delay testing. Experimental results are presented to validate the effectiveness of the proposed approach.

As the feature size scales down, crosstalk noise on circuit timing becomes increasingly significant. In this paper, we propose a path delay test generation method toward activation of worst case crosstalk effects, in order to decrease the test escape of delay testing. The proposed method performs transition-map-based timing analysis to identify crosstalk-sensitive critical paths, followed by a deterministic test generation process. Using the transition map instead of the timing window to manage the timing information, the proposed method can identify many false coupling sites and thus reduce the pessimism in crosstalk-induced fault collection caused by inaccurate timing analysis. It can also efficiently calculate the accumulative crosstalk-induced delay, and find the sub-paths which cause worst case crosstalk effects during test generation. By converting the timing constraints of coupling lines into logic constraints, complex timing processing for crosstalk effect activation is avoided during test generation. In addition, the tradeoff between accuracy and efficiency can be explored by varying the size of timescale used in the transition map.

With the shrink of technology to the nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting many cores on a single chip. It suffers however from increasingly serious interconnect crosstalk effects, which constrain the overall performance of NOC systems. In this paper, a crosstalk tolerance method is proposed for reducing bus delay on NOC interconnects. Crosstalk-induced latency is predicted by analyzing the possible crosstalk effects of adjacent patterns stored in an NOC router. Transition times of selected bits are then adjusted to relieve these predicted crosstalk-induced effects. Experimental results on interconnects show that the proposed method can achieve the same bus delay reduction as the insertion of extra shielding wires into two adjacent wires, while the proposed method requires no extra wires. Compared with previous methods using a dual rail code, a crosstalk avoidance code, and/or a variable clock, the proposed approach provides a larger reduction of bus delay with less area overhead.

Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated to implicitly enumerate almost all candidate critical paths, and then the CPG is partitioned into several sub graphs which contain limited numbers of paths using two graph partition approaches. After that, Monte Carlo simulation is applied on each sub graph for path selection. At last, according to the partition topology of the CPG and path sets selected from each sub graph, a path set for the original CPG is generated using Union and Cartesian product operations for testing SDDs. Experimental results show that for circuits containing large numbers of candidate critical paths, the proposed path selection approach can reduce the CPU time significantly and maintain a higher probability of capturing delay failures compared to path selection methods based on general Monte Carlo simulation.

Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

In this paper, we focus on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth first search approach.

Statistical static timing analysis (SSTA) considering process variation and aging effects is usually used to analyze circuit lifetime reliability at design phase. A key challenge for statistical lifetime reliability analysis is that an accurate statistical timing model is needed to carefully model practical variation distribution as well as delay correlation. In this work, P2CLRAF, a circuit lifetime reliability analysis framework is proposed. It calibrates pre-silicon SSTA result by learning the collected data from path delay testing at post-silicon timing validation phase. A neural network inside P2CLRAF is trained to learn variation distribution and delay correlation based on the statistic of path delay testing. The learned information is then fed back to SSTA to further improve the accuracy of circuit lifetime reliability analysis. Experimental results demonstrate the effectiveness of the proposed analysis framework.

In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based self-testing (SBST) of processors. First, mappings between expanded instructions and signals are obtained through data mining, and they are used to impose value ranges of expanded instructions on component signals and generate instruction-level constraints. Second, virtual circuits are established based on the instruction-level constraints, and test patterns are generated for the constrained components. Third, test patterns are translated into test instructions according to the values of controlling signals and constraints for their mappings to instructions, and an SBST program is produced after assembling the test instructions. Experimental results on the Parwan processor show that the proposed ATIG technique can achieve 94.8% stuck-at fault coverage, which is close to that of the full scan test generation method. In addition, it can cut down 57% test volume of the previous random pattern generation based SBST technique, while the test time reduces to one thirteenth of the previous SBST technique.

In this paper, we propose a binary-tree waveguide connected Optical-Network-on-Chip (ONoC) to accelerate the establishment of the lightpath. By broadcasting the control data in the proposed power-efficient binary-tree waveguide, the maximal hops for establishing lightpath is reduced to two. With extensive simulations and analysis, we demonstrate that the proposed ONoC significantly reduces the setup time, and then the packet latency.

Faster-than-at-speed testing provides an effective way for detecting and debugging small delay defects in modern fabricated chips. However, the use of external automatic test equipment for faster-than-at-speed delay testing could be costly. In this paper, we present an on-chip clock generation scheme which facilitates faster-than-at-speed delay testing for both launch on capture and launch on shift test frameworks. The required test clock frequency with a high resolution can be obtained by specifying the information in the test patterns, which is then shifted into the delay control stages to configure the launch and capture clock generation circuit (LCCG) embedded on-chip. Similarly, the control information for selecting various test frameworks and clock signals can also be embedded in the test patterns. Experimental results are presented to validate the proposed scheme.

We propose an efficient algorithm on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth-first search procedure of U generation, targeting the reduction of checking times of sensitization criteria. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth-first search approach.

We present nGFSIM, a GPU-based fault simulator for stuck-at faults which can report the fault coverage of one-to n-detection for any specified integer n using only a single run of fault simulation. nGFSIM, which explores the massive parallelism in the GPU architecture and optimizes the memory access and usage, enables accelerated fault simulation without the need of fault dropping. We show that nGFSIM offers a 25X speedup in comparison with a commercial tool and enables new applications in test selection.

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme.

Statistical timing models have been proposed to describe delay variations in very deep sub-micron process technologies, which have increasingly significant influence on circuit performance. Under a statistical timing model, testing of a path can detect potential delay failures caused by different small delay defects. Due to path correlations, the potential delay failures captured by two different paths overlap between each other more or less. It is difficult to find a given number of paths that can capture most potential delay failures. In this paper, the path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that the paths in a specified path set all meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time-efficient and achieves a higher probability of capturing delay failures in comparison with conventional path selection approaches.

Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit performance. NBTI degradation has strong dependence on input pattern and duty cycles. Based on this observation, we propose to apply multiple input vectors to the combination circuit in a non-uniform way during standby mode. Multiple input vectors can enhance the capability to control the circuit nodes, achieve smaller duty cycles to reduce the stress time of gates and thus mitigate static NBTI. A constrained multi-object optimization model is formalized to find the optimal combination of duty cycles for timing-critical paths, which in turn minimizes the increase of path delay. An ATPG-like procedure is then presented to generate the corresponding input vectors. Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors.

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.

This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (test access mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a data-synchronous-comparator (DSC) is proposed for comparing the scan responses of the identical cores.

The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free by utilizing restricted intermediate nodes rather than adding virtual channels (VC). This characteristic leads to an area-efficient router. Second, in the proposed routing algorithm, the rounds of DOR are not limited by the number of VC's anymore. As a consequence, the number of sacrificed non-faulty routers is significantly reduced. We demonstrate above advantages through extensive simulations. The experimental results show that under the limitation of VC's, the proposed routing algorithm always sacrifices the minimal number of non-faulty routers compared to previous solutions.

Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation delay in an inverter. By a waveform simulation based on Boolean process, the simulator is able to show the time interval that the fault affects and determine whether the propagation delay exceeds the system clock cycle. It might give ATPG a little of useful information.

Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (LOC) approach is relatively low, the generated pattern set for testing delay faults is typically very large. In this paper, we present a novel flip-flop selection method to combine the respective advantages of the two approaches, by replacing a small number of selected regular scan cells with enhanced scan cells, thus to reduce the overall volume of transition delay test patterns effectively. Moreover, higher fault coverage can also be obtained by this approach compared to the standard LOC approach. Experimental results on larger ISCAS-89 and ITC-99 benchmark circuits using a commercial test generation tool show that the volume of test patterns can be reduced by over 70% and the transition delay fault coverage can be improved by up to 8.7%.

Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capability on SDD detection. A new signal transition probability calculation method is presented to calculate output deviation more practical than that without considering hazards. Patterns from an N-detect test set for transition faults are then selected according to their output deviations. Experimental results show that, for the same pattern count, the patterns selected by the proposed method excite more long paths, and are capable of detecting more small delay defects at the early stage of delay testing compared to the method without considering hazards.

As the design complexity increases dramatically, results of functional simulation are usually checked through only a part of signals during design verification. It is important, therefore, to consider the observability of internal signals for effective checking. This paper proposes a static observability analysis method to automatically select internal observation signals, which improves the quality of functional verification. A series of formulas are defined to evaluate observability of internal signals, and an algorithm is proposed to locate the sources of low-observability. Such sources, rather than general hard-to-observe signals, are desirable internal observation signals. Experimental results indicate that signals selected by this method can improve the observability of designs more than those randomly selected from hard-to-observe signals.

Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.

In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS’89 circuits showed test generation can be finished in a few seconds.

The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.

With the shrink of the technology into nanometer scale, network-on-chip (NOC) has becoming a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk and SEU errors, which affect its proper function. Therefore, it is desirable to design a reliable NOC under acceptable overhead. In this paper, an SCAC-TMR scheme is provided for NOC design, which maps data into selected crosstalk avoidance code (SCAC) for message transmission and preserves state and controlling registers of routers with triple modular redundancy (TMR). This scheme can avoid large crosstalk-induced delay in GHz circuits, because SCAC forbids relevant signal transitions on channels. Besides, due to low power dissipation of SCAC, routers of this scheme consume lower power. Experimental result shows that this scheme can save nearly 18% area overhead and 31% power dissipation compared with former method.

Scan chain failure diagnosis has become an important means for silicon debug and yield improvement. Although plenty of prior work discussed how to perform scan chain diagnosis, most of the previously proposed techniques made an assumption that the system logic is fault-free, which could be an impractical assumption leading to incorrect diagnostic results. In this paper, we propose a scan chain deterministic diagnostic pattern generation (DDPG) method that can tolerate the faults in the system logic without degradation of chain diagnostic resolution and precision. The entire flow includes three steps. In the first step, patterns are created to propagate the state of a targeted scan cell to as many reliable observation points as possible. In the second step, the load error probability of each targeted scan cell is calculated based on the hamming distances between the observed responses and the expected good or faulty responses. In the last step, a suspect profile is plotted, which can be used to identify the suspect scan cell(s) based on ranking scores. Experimental results show that the diagnostic resolution and precision are not degraded even with dozens of faults injected into the system logic.

We propose a two-phase test generation method to generate patterns targeting maximal path delay caused by multiple crosstalk effects. A timing analysis method based on transition map is proposed to manage the timing information of aggressor lines and victim lines in the first phase, followed by an ordinary ATPG engine with a few alterations in the second phase. This two-phase method avoids complex timing processing in ATPG algorithm. Using transition map instead of timing window in timing analysis, our method can more efficiently calculate the accumulative crosstalk-induced delay and find the sub-paths which cause maximal coupling effects. We can trade off accuracy and efficiency by controlling the size of timescale used in transition map, which makes this approach highly scalable.

Crosstalk effects and soft errors on interconnects have been increasingly serious, which affects normal communication among cores. Therefore, it is desirable to design a reliable bus system without causing unacceptable performance reduction. In this paper, a new bus encoding method based on codeword selection is presented for enduring crosstalk-induced effects, which can avoid crosstalk and provide error correction as well. This method finds a subset from crosstalk avoidance code (CAC) to provide error correction. It can avoid crosstalk induced by late signal transition on checking bits in the previous methods. Extra wires for checking bus are never required in the proposed method. Experiment shows that the method reduces 6% wire overhead compared to the former methods. And it can also improve bus performance and reduce power dissipation.

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals.

An embedded test stimulus decompressor is presented for the test patterns decompression, which can reduce the required channels and vector memory of automatic test equipment (ATE) for complex processor circuit. The proposed decompressor mainly consists of a periodically alterable MUX network which has multiple configurations to decode the input information flexibly and efficiently. In order to reduce the number of test patterns and configurations, a test patterns compaction algorithm, using CI-Graph merging, is proposed. With the proposed periodically alterable MUX network and the patterns compaction algorithm, smaller test data volume and required external pins can be achieved as compared to previous techniques

We proposed clustered random access scan (CRAS) architecture to reduce test data volume. CRAS makes use of the compatibility of the test stimuli to cluster the scan cells, and assigns every cluster a unique address. The compression ratio upper bound of CRAS is analyzed based on the random graph theory. Experimental results on ISCAS'89 benchmarks and two industry designs show that the proposed CRAS architecture can yield on average 67.3% reduction in test data volume, with reasonable area and routing overhead than scan design

In this paper we propose an observability branch coverage metric (OBCM) based on dynamic factored use-define chains, along with its evaluation method. This technique exploits the efficiency of data-flow analysis rather than methods like fault simulation. Hence it can be easily integrated into HDL compilers or simulators. Experimental results show that OBCM can provide more meaningful coverage data for functional verification than traditional branch coverage metric (BCM).

Packet classification is important in fulfilling the requirements of new services such as policy-based routing in next generation networks. In this paper, we propose a novel bit vector based two-dimensional packet classification algorithm called Group Bit Vector. The key feature of the proposed algorithm is its ability to set the length of the bit vector to perform AND operation (the operation bit vector) regardless of the size of rule databases by effectively aggregating the rules and constructing particular groups of a limited number of members. Moreover, the proposed algorithm avoids the problem of false matches, which may be brought by rules aggregation. Thus, the length of the operation bit vector can be adjusted to be suitable to the width of memories to improve the performance. Experimental results demonstrate the flexibility and effectiveness of the proposed algorithm.

Crosstalk-induced delay should be tested for high-speed circuits. We propose a robust test generation technique based on a single precise crosstalk-induced path delay fault model, S-PCPDF model. The path sensitization criterion of robust test generation for a target S-PCPDF is defined separately for sensitizing the path under test and sensitizing the sub-path to propagate aggressor transitions. Experimental results showed that the proposed technique can be applied to circuits of reasonable sizes within an acceptable time. The average test efficiency is high.

The rapid growth of backbone network traffic increases the gaps among the available network bandwidth, the CPU computation power and the memory bandwidth. The memory bandwidth has become the main performance bottleneck of network processor. In this paper, an efficient memory subsystem design is proposed which combines dynamic memory allocation and a novel page-based memory access algorithm. The dynamic memory allocation achieves fast random packet access and flexible queue management. Utilizing the paged-based memory access algorithm, an efficient design of memory controller is proposed and high throughput can be implemented in the network processor.

This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n-1, m, 3) convolutional code is proposed. Theoretic analysis for this encoder is presented to avoid two and any odd erroneous bit cancellations, handle one unknown bit(X bit) and diagnose one erroneous bit. The X-bits tolerance capacity can be enhanced by choosing a proper memory size and weight of check matrix, which can also be obtained by an optimized input assignment algorithm. The theoretic analysis and experimental results on aliasing shows the efficiency of the proposed encoder.

Crosstalk issues in deep sub-micron (DSM) cause severe design validation and test problems. This paper addresses the problems of delay test considering crosstalkinduced effects, and proposes a non-robust delay test generation method based on single precise crosstalkinduced path delay fault (S-PCPDF) model. With some necessary static timing analysis, the target crosstalkinduced delay fault set was reduced. And the delay test generation for crosstalk-induced delay faults can be implemented by few alterations of non-robust path delay test generation algorithms whereas the timing information is only considered during the selection of target faults. Experimental results on ISCAS’89 and ITC’99 benchmark circuits showed that the proposed method does efficiently for circuits of reasonable sizes, and the CPU time is acceptable.

Testing chips is very critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-test technique for LSI design and testing, the need for reducing the test data volume, scan-in power dissipation and test application time (VPT) of the full-scan designed chip is imperative. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme tackling all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3% and 85.5% reduction in test data volume, average scan-in power dissipation, peak scan-in power dissipation and test application time, respectively.

Conventional serial connection of internal scan chains brings the power and time penalty. A parallel core wrapper design (pCWD) approach is presented in this paper for reducing test power and test application time. The pCWD utilizes overlapping scan slices to reduce the number of scan slices loading. Experimental results on d695 of ITC2002 benchmark demonstrated that, about 2/spl times/ shift time and 20/spl times/ test power reduction can be achieved.

Along with more pre-designed and pre-verified cores are integrated into a single chip to construct an entire system, the test application time increases significantly. This paper presents a novel test scheduling solution, unlike previous techniques that take advantage of balanced scan chains of every single core, utilizing the balance of pairwise combined cores. Experimental results for two ITC '02 SOC benchmarks show that the pair balance-based test scheduling technique achieves less test time compared to the previous approaches.

This paper presents a test resource partitioning technique based on an efficient single-output response compaction design called quotient compactor (q-Compactor). Some design theorems of quotient compactor are presented to achieve full diagnostics ability, minimize error cancellation and handle the X bits in the outputs of the CUT The quotient compactor can also be moved to the load-board to reduce the number of ATE channels required. Our experimental results on the ISCA S89 benchmark circuits and an MPEG 2 decoder SOC show that the proposed compaction scheme is very efficient.

Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems. This paper addresses the problem of delay testing considering crosstalk-induced delay effects. A delay test pattern generation technique is proposed based on waveform sensitization. Crosstalk-induced effects on critical paths are targeted to improve test effectiveness of delay testing. Experimental results show the efficiency of this technique. It can be applied to circuits of reasonable sizes by generating delay tests considering crosstalk-induced effects within an acceptable amount of time.

Three efficient test power optimization algorithms for CMOS circuits are studied in this paper. First, for delay-fault test pattern sets of ISCAS89 benchmarks, this algorithm can cut down 37.5% or more test power than the simulation-based annealing algorithm. Second, because approaches which use the Hamming distance between two input test patterns, to optimize the test power, cannot reduce as much power for ISCAS85 benchmarks as expected, a novel optimization approach that uses the power of an ideal circuit without delay, to optimize the test power is presented. Experimental results demonstrate that our approach can cut down 70.8% more test power than present approaches. Third, the influence of undetermined test bits on test power optimization is studied by changing the number of undetermined bits in test patterns. Experimental results demonstrate that with the increase of undetermined test bits, the un-optimized test power markedly decreases.

This paper presents a new level of description between behavioral and state descriptions of a finite-state machine (FSM). The description is termed behavioral phase clustering description. New concepts of behavioral phase and clustering of behavioral phases in an FSM are introduced. The new description simplifies functional analysis, verification and test of FSM designs. If an FSM is described at low level, some states can be clustered into behavioral phases directly. If it is described at behavioral level, behavioral phases can be extracted from the behavioral description, and clustering of behavioral phases can be performed through easy functional analysis. As one application of behavioral phase clustering descriptions, a new technique employed in a test generation system, ATCLUB, at Register Transfer (RT)-level based on a behavioral phase transition fault model is introduced in this paper. In ATCLUB, test generation process is accelerated through clustering of behavioral phases. Experimental results show that ATCLUB generates test sequence efficiently, with a sharp decrease in vector count at the penalty of a slightly decrease in fault coverage comparing to other ATPG tools.

This paper introduces a new technique employed in a test generation system, ATCLUB, at RT-level, based on clustering of circuit states. States or some sets of states in a low-level description are mapped to high levels in terms of a particular variable in a behavioral description, and termed behavioral phases. Further clustering of behavioral phases is performed to represent the function of a circuit more explicitly and refinedly. Such a refined representation is then used in the test generation algorithm to simplify and speed up search process of test sequences. Experimental results demonstrate the computational efficiency of the clustering process and test pattern generation.

Delay testing is important for high speed ICs. The main difficulty for delay testing comes from the huge number of paths and the large percentage of delay untestable paths. This paper presents an approach to delay testing with double observations, which provides a high path delay fault coverage by testing a small number of paths. But, for each test pair, it is necessary to sample the primary output twice, one before and another after the transition. The paper explains how to select the very limited number of paths, termed sample paths, and how to generate the test pair and the observation times for the sample paths. Furthermore, the number of sample paths is linear to the number of gates in the circuit under test, despite exponential growth in the number of single paths. Based on the analytical delay model, most of the paths are delay testable which makes the delay test generation easier than that based on single path sensitization.