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Meir Mor

dblp:70/5995 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1976
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% Integrated circuit design · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.011976
On the Three-Valued Simulation of Digital Systems · IEEE Trans. Computers 1976
Electronic design automation › hardware verification and test › functional verification
simulation-based verification		 0.011976
On the Three-Valued Simulation of Digital Systems · IEEE Trans. Computers 1976
Electronic design automation › hardware verification and test › logic simulation
ternary simulation		 0.011976
On the Three-Valued Simulation of Digital Systems · IEEE Trans. Computers 1976
Integrated circuit design
digital circuit design		 0.011976
On the Three-Valued Simulation of Digital Systems · IEEE Trans. Computers 1976

Methods — techniques the papers use, named apart from their topics

three-valued logic · 0.0gate modeling · 0.0
YearPublicationVenuePosition
1976 On the Three-Valued Simulation of Digital Systems
abstract
The problem of the so-called "pessimistic" results, obtained by usingg three-valued (0,1,u) simulation for design verification of digital systems, is discussed. A complete three-valued model for the sequential portion of the digital systems is suggested. The conventional gate model is replaced by the new model, which reduces the problem considerably.
Meir Mor
 IEEE Trans. Computers1